Qualcomm Technologies, Inc. GPU Graphics Management Unit (GMU)

Required properties:
- compatible :
	- "qcom,gpu-gmu"
- reg:		Specifies the PDC register base address and size.
- reg-names:		Resource names used for the physical address
		and length of PDC registers.
- interrupts:	Interrupt mapping for GMU and HFI IRQs.
- interrupt-names:	String property to describe the name of each interrupt.

Bus Scaling Data:
qcom,msm-bus,name: String property to describe the name of bus client.
qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.
qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.
qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:
		<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1
		<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2
		<..  ..  .. ..>, <..  ..  .. ..>; // For Bus Scaling Usecase n
		This property is a series of all vectors for all Bus Scaling Usecases.
		Each set of vectors for each usecase describes bandwidth votes for a combination
		of src/dst ports.  The driver will set the desired use case based on the selected
		power level and the desired bandwidth vote will be registered for the port pairs.

GMU GDSC/regulators:
- regulator-names:	List of regulator name strings
- vddcx-supply:		Phandle for vddcx regulator device node.
- vdd-supply:		Phandle for vdd regulator device node.

- clock:	List of clocks to be used for GMU register access and DCVS. See
		  Documentation/devicetree/bindings/clock/clock-bindings.txt
		  for information about the format. For each clock specified
		  here, there must be a corresponding entry in clock-names
		  (see below).

- clock-names:	List of clock names corresponding to the clocks specified in
		  the "clocks" property (above). See
		  Documentation/devicetree/bindings/clock/clock-bindings.txt
		  for more info. Currently GMU required these clock names:
			"gmu_clk", "ahb_clk", "cxo_clk", "axi_clk", "memnoc_clk",
			"rbcpr_clk"

- qcom,gmu-pwrlevels: device node defines a set of GMU power levels. It has
		following required properties:

		- compatible : "qcom,gmu-pwrlevels"
		- qcom,gmu-pwrlevel: a single power level. Each power level has
		  below properties:
			- reg: index of the powerlevel (0 = highest perf)
			- qcom, gmu-freq: GMU frequency for the power level in Hz.

- List of sub nodes, one for each of the translation context banks needed
		for GMU to access system memory in different operating mode. Currently
		supported names are:
		- gmu_user: used for GMU 'user' mode address space.
		- gmu_kernel: used for GMU 'kernel' mode address space.
		Each sub node has the following required properties:

		- compatible : "qcom,smmu-gmu-user-cb" or "qcom,smmu-gmu-kernel-cb"
		- iommus : Specifies the SID's used by this context bank, this
			needs to be <kgsl_smmu SID> pair, kgsl_smmu is the string
			parsed by iommu driver to match this context bank with the
			kgsl_smmu device defined in iommu device tree. On targets
			where the msm iommu driver is used rather than the arm smmu
			driver, this property may be absent.

Example:

gmu: qcom,gmu {
	label = "kgsl-gmu";
	compatible = "qcom,gpu-gmu";

	reg = <0xb200000 0x300000>;
	reg-names = "kgsl_gmu_pdc_reg";

	interrupts = <0 301 0>, <0 302 0>;
	interrupt-names = "kgsl_gmu_irq", "kgsl_hfi_irq";

	qcom,msm-bus,name = "cnoc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<26 10036 0 0>,		// CNOC off
			<26 10036 0 100>;	// CNOC on

	regulator-name = "vddcx", "vdd";
	vddcx-supply = <&gpu_cx_gdsc>;
	vdd-supply = <&gpu_gx_gdsc>;

	clocks = <&clock_gpugcc clk_gcc_gmu_clk>,
		<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
		<&clock_gpucc GPU_CC_CXO_CLK>,
		<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
		<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
		<&clock_gpucc GPU_CC_RBCPR_CLK>;

	clock-names = "gmu_clk", "ahb_clk", "cxo_clk",
				"axi_clk", "memnoc_clk", "rbcpr_clk";

	qcom,gmu-pwrlevels {

	      compatible = "qcom,gmu-pwrlevels";
	      qcom,gpu-pwrlevel@0 {
	          reg = <0>;
	          qcom,gmu-freq = <500000000>;
	      };

	      qcom,gpu-pwrlevel@1 {
	          reg = <1>;
	          qcom,gmu-freq = <200000000>;
	      };

	      qcom,gpu-pwrlevel@2 {
	          reg = <2>;
	          qcom,gmu-freq = <0>;
	      };
	};

	gmu_user: gmu_user {
	      compatible = "qcom,smmu-gmu-user-cb";
	      iommus = <&kgsl_smmu 4>;
	};

	gmu_kernel: gmu_kernel {
	      compatible = "qcom,smmu-gmu-kernel-cb";
	      iommus = <&kgsl_smmu 5>;
	};
};