qcom,gpucc.txt 1010 B

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  1. Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding
  2. --------------------------------------------------------------------
  3. Required properties :
  4. - compatible : shall contain only one of the following:
  5. "qcom,gpucc-sdm845",
  6. "qcom,gpucc-sdm845-v2",
  7. "qcom,gfxcc-sdm845",
  8. "qcom,gfxcc-sdm845-v2"
  9. "qcom,gpucc-sdm670",
  10. "qcom,gfxcc-sdm670"
  11. - reg : shall contain base register offset and size.
  12. - #clock-cells : shall contain 1.
  13. - #reset-cells : shall contain 1.
  14. - #vdd_<rail>-supply : The logic rail supply.
  15. Optional properties :
  16. - #power-domain-cells : shall contain 1.
  17. Example:
  18. clock_gfx: qcom,gfxcc@5090000 {
  19. compatible = "qcom,gfxcc-sdm845";
  20. reg = <0x5090000 0x9000>;
  21. vdd_gfx-supply = <&pm8005_s1_level>;
  22. vdd_mx-supply = <&pm8998_s6_level>;
  23. #clock-cells = <1>;
  24. #reset-cells = <1>;
  25. };
  26. clock_gpucc: qcom,gpucc@5090000 {
  27. compatible = "qcom,gpucc-sdm845";
  28. reg = <0x5090000 0x9000>;
  29. vdd_cx-supply = <&pm8998_s9_level>;
  30. #clock-cells = <1>;
  31. #reset-cells = <1>;
  32. };