icnss.txt 2.7 KB

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  1. * Qualcomm Technologies Inc Q6 Integrated connectivity Platform Driver
  2. This platform driver adds support for the Integrated WLAN that runs
  3. on Q6 based platforms. WLAN FW on these architecture runs on Q6. This
  4. platform driver communicates with WLAN FW over QMI, WLAN on/off messages
  5. to FW are communicated thru this interface. This driver also listens to
  6. WLAN PD restart notifications.
  7. Required properties:
  8. - compatible: "qcom,icnss"
  9. - reg: Memory regions defined as starting address and size
  10. - reg-names: Names of the memory regions defined in reg entry
  11. - interrupts: Copy engine interrupt table
  12. - qcom,wlan-msa-memory: MSA memory size
  13. - clocks: List of clock phandles
  14. - clock-names: List of clock names corresponding to the "clocks" property
  15. - iommus: SMMUs and corresponding Stream IDs needed by WLAN
  16. - qcom,wlan-smmu-iova-address: I/O virtual address range as <start length>
  17. format to be used for allocations associated between WLAN and SMMU
  18. Optional properties:
  19. - <supply-name>-supply: phandle to the regulator device tree node
  20. optional "supply-name" is "vdd-0.8-cx-mx".
  21. - qcom,<supply>-config: Specifies voltage levels for supply. Should be
  22. specified in pairs (min, max), units uV. There can
  23. be optional load in uA and Regulator settle delay in
  24. uS.
  25. - qcom,icnss-vadc: VADC handle for vph_pwr read APIs.
  26. - qcom,icnss-adc_tm: VADC handle for vph_pwr notification APIs.
  27. - qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass
  28. - qcom,wlan-msa-fixed-region: phandle, specifier pairs to children of /reserved-memory
  29. - qcom,gpio-force-fatal-error: SMP2P bit triggered by WLAN FW to force error fatal.
  30. - qcom,gpio-early-crash-ind: SMP2P bit triggered by WLAN FW to indicate FW is in assert.
  31. Example:
  32. qcom,icnss@0a000000 {
  33. compatible = "qcom,icnss";
  34. reg = <0x0a000000 0x1000000>;
  35. reg-names = "membase";
  36. clocks = <&clock_gcc clk_aggre2_noc_clk>;
  37. clock-names = "smmu_aggre2_noc_clk";
  38. iommus = <&anoc2_smmu 0x1900>,
  39. <&anoc2_smmu 0x1901>;
  40. qcom,wlan-smmu-iova-address = <0 0x10000000>;
  41. interrupts =
  42. <0 130 0 /* CE0 */ >,
  43. <0 131 0 /* CE1 */ >,
  44. <0 132 0 /* CE2 */ >,
  45. <0 133 0 /* CE3 */ >,
  46. <0 134 0 /* CE4 */ >,
  47. <0 135 0 /* CE5 */ >,
  48. <0 136 0 /* CE6 */ >,
  49. <0 137 0 /* CE7 */ >,
  50. <0 138 0 /* CE8 */ >,
  51. <0 139 0 /* CE9 */ >,
  52. <0 140 0 /* CE10 */ >,
  53. <0 141 0 /* CE11 */ >;
  54. qcom,wlan-msa-memory = <0x200000>;
  55. qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
  56. qcom,smmu-s1-bypass;
  57. vdd-0.8-cx-mx-supply = <&pm8998_l5>;
  58. qcom,vdd-0.8-cx-mx-config = <800000 800000 2400 1000>;
  59. qcom,gpio-forced-fatal-error = <&smp2pgpio_wlan_1_in 0 0>;
  60. qcom,gpio-early-crash-ind = <&smp2pgpio_wlan_1_in 1 0>;
  61. };