mediatek,hdmi.txt 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148
  1. Mediatek HDMI Encoder
  2. =====================
  3. The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
  4. its parallel input.
  5. Required properties:
  6. - compatible: Should be "mediatek,<chip>-hdmi".
  7. - reg: Physical base address and length of the controller's registers
  8. - interrupts: The interrupt signal from the function block.
  9. - clocks: device clocks
  10. See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
  11. - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
  12. - phys: phandle link to the HDMI PHY node.
  13. See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
  14. - phy-names: must contain "hdmi"
  15. - mediatek,syscon-hdmi: phandle link and register offset to the system
  16. configuration registers. For mt8173 this must be offset 0x900 into the
  17. MMSYS_CONFIG region: <&mmsys 0x900>.
  18. - ports: A node containing input and output port nodes with endpoint
  19. definitions as documented in Documentation/devicetree/bindings/graph.txt.
  20. - port@0: The input port in the ports node should be connected to a DPI output
  21. port.
  22. - port@1: The output port in the ports node should be connected to the input
  23. port of a connector node that contains a ddc-i2c-bus property, or to the
  24. input port of an attached bridge chip, such as a SlimPort transmitter.
  25. HDMI CEC
  26. ========
  27. The HDMI CEC controller handles hotplug detection and CEC communication.
  28. Required properties:
  29. - compatible: Should be "mediatek,<chip>-cec"
  30. - reg: Physical base address and length of the controller's registers
  31. - interrupts: The interrupt signal from the function block.
  32. - clocks: device clock
  33. HDMI DDC
  34. ========
  35. The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
  36. The Mediatek's I2C controller is used to interface with I2C devices.
  37. Required properties:
  38. - compatible: Should be "mediatek,<chip>-hdmi-ddc"
  39. - reg: Physical base address and length of the controller's registers
  40. - clocks: device clock
  41. - clock-names: Should be "ddc-i2c".
  42. HDMI PHY
  43. ========
  44. The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
  45. output and drives the HDMI pads.
  46. Required properties:
  47. - compatible: "mediatek,<chip>-hdmi-phy"
  48. - reg: Physical base address and length of the module's registers
  49. - clocks: PLL reference clock
  50. - clock-names: must contain "pll_ref"
  51. - clock-output-names: must be "hdmitx_dig_cts" on mt8173
  52. - #phy-cells: must be <0>
  53. - #clock-cells: must be <0>
  54. Optional properties:
  55. - mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
  56. - mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
  57. Example:
  58. cec: cec@10013000 {
  59. compatible = "mediatek,mt8173-cec";
  60. reg = <0 0x10013000 0 0xbc>;
  61. interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
  62. clocks = <&infracfg CLK_INFRA_CEC>;
  63. };
  64. hdmi_phy: hdmi-phy@10209100 {
  65. compatible = "mediatek,mt8173-hdmi-phy";
  66. reg = <0 0x10209100 0 0x24>;
  67. clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
  68. clock-names = "pll_ref";
  69. clock-output-names = "hdmitx_dig_cts";
  70. mediatek,ibias = <0xa>;
  71. mediatek,ibias_up = <0x1c>;
  72. #clock-cells = <0>;
  73. #phy-cells = <0>;
  74. };
  75. hdmi_ddc0: i2c@11012000 {
  76. compatible = "mediatek,mt8173-hdmi-ddc";
  77. reg = <0 0x11012000 0 0x1c>;
  78. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
  79. clocks = <&pericfg CLK_PERI_I2C5>;
  80. clock-names = "ddc-i2c";
  81. };
  82. hdmi0: hdmi@14025000 {
  83. compatible = "mediatek,mt8173-hdmi";
  84. reg = <0 0x14025000 0 0x400>;
  85. interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
  86. clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
  87. <&mmsys CLK_MM_HDMI_PLLCK>,
  88. <&mmsys CLK_MM_HDMI_AUDIO>,
  89. <&mmsys CLK_MM_HDMI_SPDIF>;
  90. clock-names = "pixel", "pll", "bclk", "spdif";
  91. pinctrl-names = "default";
  92. pinctrl-0 = <&hdmi_pin>;
  93. phys = <&hdmi_phy>;
  94. phy-names = "hdmi";
  95. mediatek,syscon-hdmi = <&mmsys 0x900>;
  96. assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
  97. assigned-clock-parents = <&hdmi_phy>;
  98. ports {
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. port@0 {
  102. reg = <0>;
  103. hdmi0_in: endpoint {
  104. remote-endpoint = <&dpi0_out>;
  105. };
  106. };
  107. port@1 {
  108. reg = <1>;
  109. hdmi0_out: endpoint {
  110. remote-endpoint = <&hdmi_con_in>;
  111. };
  112. };
  113. };
  114. };
  115. connector {
  116. compatible = "hdmi-connector";
  117. type = "a";
  118. ddc-i2c-bus = <&hdmiddc0>;
  119. port {
  120. hdmi_con_in: endpoint {
  121. remote-endpoint = <&hdmi0_out>;
  122. };
  123. };
  124. };