i2c-msm-v2.txt 2.1 KB

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  1. Qualcomm I2C controller
  2. Required properties:
  3. - reg : Offset and length of the register region for the device named in
  4. reg-names and has the same index.
  5. - reg-names : Register region name(s) referenced in reg above
  6. "qup_phys_addr" : Physical address of QUP register space.
  7. - compatible : should be "qcom,i2c-msm-v2"
  8. - interrupts : Interrupt number which correspond to the entry with the same
  9. index in interrupt-names.
  10. - interrupt-names: QUP core interrupt name(s) referenced in interrupts above
  11. "qup_irq" : QUP interrupt used by the controller.
  12. - dmas : DMA engine API's parameters for blsp.
  13. <[phandle of the dma controller] [pipe index] [number of descriptors]
  14. [sps_connect flags] [sps_register_event flags]>;
  15. - dma-names : dma channel names.
  16. - qcom,clk-freq-out : Desired I2C bus clock frequency in Hz
  17. - qcom,clk-freq-in : Supplied core clock frequency in Hz.
  18. Required alias:
  19. - The desired bus-number is specified by an alias with the following format:
  20. 'i2c{n}' where n is the bus number.
  21. Optional property:
  22. - qcom,noise-rjct-scl : number of low samples on clock line to consider it low.
  23. When missing default to 0.
  24. - qcom,noise-rjct-sda : number of low samples on data line to consider it low.
  25. When missing default to 0.
  26. - qcom,disable-dma : disables DMA transfer mode.
  27. - qcom,master-id : Master-port value used on voting for the clock path.
  28. - qcom,high-time-clk-div : high time divider value to configure clk-ctl
  29. register. When missing, default to the value given in driver.
  30. - qcom,fs-clk-div: fs divider value to configure clk-ctl register. When
  31. missing, default to the value given in driver.
  32. Example:
  33. aliases {
  34. i2c10 = &i2c_10;
  35. };
  36. i2c_10: i2c@f9966000 {
  37. compatible = "qcom,i2c-msm-v2";
  38. reg-names = "qup_phys_addr", "dma_phys_addr";
  39. reg = <0xf9966000 0x1000>;
  40. interrupt-names = "qup_irq";
  41. interrupts = <0 104 0>;
  42. dmas = <&dma_blsp1 14 32 0x20000020 0x20>,
  43. <&dma_blsp1 15 64 0x20000020 0x20>;
  44. dma-names = "tx", "rx";
  45. qcom,clk-freq-out = <100000>;
  46. qcom,clk-freq-in = <24000000>;
  47. qcom,noise-rjct-scl = <0>;
  48. qcom,noise-rjct-sda = <0>;
  49. };