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- GENI based Qualcomm Technologies Inc Universal Peripheral version 3 (QUPv3)
- I2C controller
- Required properties:
- - compatible: Should be:
- * "qcom,i2c-geni.
- - reg: Should contain QUP register address and length.
- - interrupts: Should contain I2C interrupt.
- - clocks: Serial engine core clock, and AHB clocks needed by the device.
- - pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
- should be "active" and "sleep" for the pin confuguration when core is active
- or when entering sleep state.
- - #address-cells: Should be <1> Address cells for i2c device address
- - #size-cells: Should be <0> as i2c addresses have no size component
- - qcom,wrapper-core: Wrapper QUPv3 core containing this I2C controller.
- Optional property:
- - qcom,clk-freq-out : Desired I2C bus clock frequency in Hz.
- When missing default to 400000Hz.
- Child nodes should conform to i2c bus binding.
- Example:
- i2c@a94000 {
- compatible = "qcom,i2c-geni";
- reg = <0xa94000 0x4000>;
- interrupts = <GIC_SPI 358 0>;
- clock-names = "se-clk", "m-ahb", "s-ahb";
- clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
- <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
- <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qup_1_i2c_5_active>;
- pinctrl-1 = <&qup_1_i2c_5_sleep>;
- #address-cells = <1>;
- #size-cells = <0>;
- qcom,wrapper-core = <&qupv3_0>;
- qcom,clk-freq-out = <400000>;
- };
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