qcom,i2c-qcom-geni.txt 1.4 KB

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  1. GENI based Qualcomm Technologies Inc Universal Peripheral version 3 (QUPv3)
  2. I2C controller
  3. Required properties:
  4. - compatible: Should be:
  5. * "qcom,i2c-geni.
  6. - reg: Should contain QUP register address and length.
  7. - interrupts: Should contain I2C interrupt.
  8. - clocks: Serial engine core clock, and AHB clocks needed by the device.
  9. - pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names
  10. should be "active" and "sleep" for the pin confuguration when core is active
  11. or when entering sleep state.
  12. - #address-cells: Should be <1> Address cells for i2c device address
  13. - #size-cells: Should be <0> as i2c addresses have no size component
  14. - qcom,wrapper-core: Wrapper QUPv3 core containing this I2C controller.
  15. Optional property:
  16. - qcom,clk-freq-out : Desired I2C bus clock frequency in Hz.
  17. When missing default to 400000Hz.
  18. Child nodes should conform to i2c bus binding.
  19. Example:
  20. i2c@a94000 {
  21. compatible = "qcom,i2c-geni";
  22. reg = <0xa94000 0x4000>;
  23. interrupts = <GIC_SPI 358 0>;
  24. clock-names = "se-clk", "m-ahb", "s-ahb";
  25. clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
  26. <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
  27. <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
  28. pinctrl-names = "default", "sleep";
  29. pinctrl-0 = <&qup_1_i2c_5_active>;
  30. pinctrl-1 = <&qup_1_i2c_5_sleep>;
  31. #address-cells = <1>;
  32. #size-cells = <0>;
  33. qcom,wrapper-core = <&qupv3_0>;
  34. qcom,clk-freq-out = <400000>;
  35. };