qcom,lpi-pinctrl.txt 3.9 KB

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  1. Qualcomm Technologies, Inc. LPI GPIO controller driver
  2. This DT bindings describes the GPIO controller driver
  3. being added for supporting LPI (Low Power Island) TLMM
  4. from QTI chipsets.
  5. Following properties are for LPI GPIO controller device main node.
  6. - compatible:
  7. Usage: required
  8. Value type: <string>
  9. Definition: must be "qcom,lpi-pinctrl"
  10. - reg:
  11. Usage: required
  12. Value type: <prop-encoded-array>
  13. Definition: Register base of the GPIO controller and length.
  14. - qcom,num-gpios:
  15. Usage: required
  16. Value type: <u32>
  17. Definition: Number of GPIOs supported by the controller.
  18. - gpio-controller:
  19. Usage: required
  20. Value type: <none>
  21. Definition: Used to mark the device node as a GPIO controller.
  22. - #gpio-cells:
  23. Usage: required
  24. Value type: <u32>
  25. Definition: Must be 2;
  26. The first cell will be used to define gpio number and the
  27. second denotes the flags for this gpio.
  28. Please refer to ../gpio/gpio.txt for general description of GPIO bindings.
  29. Please refer to pinctrl-bindings.txt in this directory for details of the
  30. common pinctrl bindings used by client devices, including the meaning of the
  31. phrase "pin configuration node".
  32. The pin configuration nodes act as a container for an arbitrary number of
  33. subnodes. Each of these subnodes represents some desired configuration for a
  34. pin or a list of pins. This configuration can include the
  35. mux function to select on those pin(s), and various pin configuration
  36. parameters, as listed below.
  37. SUBNODES:
  38. The name of each subnode is not important; all subnodes should be enumerated
  39. and processed purely based on their content.
  40. Each subnode only affects those parameters that are explicitly listed. In
  41. other words, a subnode that lists a mux function but no pin configuration
  42. parameters implies no information about any pin configuration parameters.
  43. Similarly, a pin subnode that describes a pullup parameter implies no
  44. information about e.g. the mux function.
  45. The following generic properties as defined in pinctrl-bindings.txt are valid
  46. to specify in a pin configuration subnode:
  47. - pins:
  48. Usage: required
  49. Value type: <string-array>
  50. Definition: List of gpio pins affected by the properties specified in
  51. this subnode. Valid pins are: gpio0-gpio31 for LPI.
  52. - function:
  53. Usage: required
  54. Value type: <string>
  55. Definition: Specify the alternative function to be configured for the
  56. specified pins. Valid values are:
  57. "gpio",
  58. "func1",
  59. "func2",
  60. "func3",
  61. "func4",
  62. "func5"
  63. - bias-disable:
  64. Usage: optional
  65. Value type: <none>
  66. Definition: The specified pins should be configured as no pull.
  67. - bias-pull-down:
  68. Usage: optional
  69. Value type: <none>
  70. Definition: The specified pins should be configured as pull down.
  71. - bias-bus-hold:
  72. Usage: optional
  73. Value type: <none>
  74. Definition: The specified pins should be configured as bus-keeper mode.
  75. - bias-pull-up:
  76. Usage: optional
  77. Value type: <empty>
  78. Definition: The specified pins should be configured as pull up.
  79. - input-enable:
  80. Usage: optional
  81. Value type: <none>
  82. Definition: The specified pins are put in input mode.
  83. - output-high:
  84. Usage: optional
  85. Value type: <none>
  86. Definition: The specified pins are configured in output mode, driven
  87. high.
  88. - output-low:
  89. Usage: optional
  90. Value type: <none>
  91. Definition: The specified pins are configured in output mode, driven
  92. low.
  93. - qcom,drive-strength:
  94. Usage: optional
  95. Value type: <u32>
  96. Definition: Selects the drive strength for the specified pins.
  97. Example:
  98. lpi_tlmm: lpi_pinctrl@152c000 {
  99. compatible = "qcom,lpi-pinctrl";
  100. qcom,num-gpios = <32>;
  101. reg = <0x152c000 0>;
  102. gpio-controller;
  103. #gpio-cells = <2>;
  104. hph_comp_active: hph_comp_active {
  105. mux {
  106. pins = "gpio22";
  107. function = "func1";
  108. };
  109. config {
  110. pins = "gpio22";
  111. output-high;
  112. qcom,drive-strength = <8>;
  113. };
  114. };
  115. hph_comp_sleep: hph_comp_sleep {
  116. mux {
  117. pins = "gpio22";
  118. function = "func1";
  119. };
  120. config {
  121. pins = "gpio22";
  122. qcom,drive-strength = <2>;
  123. };
  124. };
  125. };