qcom,msm8996-pinctrl.txt 7.2 KB

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  1. Qualcomm MSM8996 TLMM block
  2. This binding describes the Top Level Mode Multiplexer block found in the
  3. MSM8996 platform.
  4. - compatible:
  5. Usage: required
  6. Value type: <string>
  7. Definition: must be "qcom,msm8996-pinctrl"
  8. - reg:
  9. Usage: required
  10. Value type: <prop-encoded-array>
  11. Definition: the base address and size of the TLMM register space.
  12. - interrupts:
  13. Usage: required
  14. Value type: <prop-encoded-array>
  15. Definition: should specify the TLMM summary IRQ.
  16. - interrupt-controller:
  17. Usage: required
  18. Value type: <none>
  19. Definition: identifies this node as an interrupt controller
  20. - #interrupt-cells:
  21. Usage: required
  22. Value type: <u32>
  23. Definition: must be 2. Specifying the pin number and flags, as defined
  24. in <dt-bindings/interrupt-controller/irq.h>
  25. - gpio-controller:
  26. Usage: required
  27. Value type: <none>
  28. Definition: identifies this node as a gpio controller
  29. - #gpio-cells:
  30. Usage: required
  31. Value type: <u32>
  32. Definition: must be 2. Specifying the pin number and flags, as defined
  33. in <dt-bindings/gpio/gpio.h>
  34. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
  35. a general description of GPIO and interrupt bindings.
  36. Please refer to pinctrl-bindings.txt in this directory for details of the
  37. common pinctrl bindings used by client devices, including the meaning of the
  38. phrase "pin configuration node".
  39. The pin configuration nodes act as a container for an arbitrary number of
  40. subnodes. Each of these subnodes represents some desired configuration for a
  41. pin, a group, or a list of pins or groups. This configuration can include the
  42. mux function to select on those pin(s)/group(s), and various pin configuration
  43. parameters, such as pull-up, drive strength, etc.
  44. PIN CONFIGURATION NODES:
  45. The name of each subnode is not important; all subnodes should be enumerated
  46. and processed purely based on their content.
  47. Each subnode only affects those parameters that are explicitly listed. In
  48. other words, a subnode that lists a mux function but no pin configuration
  49. parameters implies no information about any pin configuration parameters.
  50. Similarly, a pin subnode that describes a pullup parameter implies no
  51. information about e.g. the mux function.
  52. The following generic properties as defined in pinctrl-bindings.txt are valid
  53. to specify in a pin configuration subnode:
  54. - pins:
  55. Usage: required
  56. Value type: <string-array>
  57. Definition: List of gpio pins affected by the properties specified in
  58. this subnode.
  59. Valid pins are:
  60. gpio0-gpio149
  61. Supports mux, bias and drive-strength
  62. sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
  63. sdc2_data sdc1_rclk
  64. Supports bias and drive-strength
  65. - function:
  66. Usage: required
  67. Value type: <string>
  68. Definition: Specify the alternative function to be configured for the
  69. specified pins. Functions are only valid for gpio pins.
  70. Valid values are:
  71. blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
  72. bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
  73. qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
  74. dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
  75. blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
  76. mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
  77. atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
  78. cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
  79. pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
  80. qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
  81. qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
  82. atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
  83. atest_usb20, atest_char0, dac_calib10, qdss_stm10,
  84. qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
  85. blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
  86. qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
  87. qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
  88. dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
  89. qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
  90. dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
  91. dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
  92. dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
  93. dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
  94. sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
  95. qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
  96. uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
  97. blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
  98. qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
  99. blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
  100. cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
  101. blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
  102. qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
  103. isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
  104. qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
  105. sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
  106. gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
  107. qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
  108. tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
  109. qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
  110. sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
  111. sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
  112. ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
  113. blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
  114. pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
  115. qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
  116. qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
  117. gpio
  118. - bias-disable:
  119. Usage: optional
  120. Value type: <none>
  121. Definition: The specified pins should be configued as no pull.
  122. - bias-pull-down:
  123. Usage: optional
  124. Value type: <none>
  125. Definition: The specified pins should be configued as pull down.
  126. - bias-pull-up:
  127. Usage: optional
  128. Value type: <none>
  129. Definition: The specified pins should be configued as pull up.
  130. - output-high:
  131. Usage: optional
  132. Value type: <none>
  133. Definition: The specified pins are configured in output mode, driven
  134. high.
  135. Not valid for sdc pins.
  136. - output-low:
  137. Usage: optional
  138. Value type: <none>
  139. Definition: The specified pins are configured in output mode, driven
  140. low.
  141. Not valid for sdc pins.
  142. - drive-strength:
  143. Usage: optional
  144. Value type: <u32>
  145. Definition: Selects the drive strength for the specified pins, in mA.
  146. Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
  147. Example:
  148. tlmm: pinctrl@01010000 {
  149. compatible = "qcom,msm8996-pinctrl";
  150. reg = <0x01010000 0x300000>;
  151. interrupts = <0 208 0>;
  152. gpio-controller;
  153. #gpio-cells = <2>;
  154. interrupt-controller;
  155. #interrupt-cells = <2>;
  156. uart_console_active: uart_console_active {
  157. mux {
  158. pins = "gpio4", "gpio5";
  159. function = "blsp_uart8";
  160. };
  161. config {
  162. pins = "gpio4", "gpio5";
  163. drive-strength = <2>;
  164. bias-disable;
  165. };
  166. };
  167. };