pwm-mtk-disp.txt 1.5 KB

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  1. MediaTek display PWM controller
  2. Required properties:
  3. - compatible: should be "mediatek,<name>-disp-pwm":
  4. - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
  5. - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
  6. - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
  7. - reg: physical base address and length of the controller's registers.
  8. - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
  9. the cell format.
  10. - clocks: phandle and clock specifier of the PWM reference clock.
  11. - clock-names: must contain the following:
  12. - "main": clock used to generate PWM signals.
  13. - "mm": sync signals from the modules of mmsys.
  14. - pinctrl-names: Must contain a "default" entry.
  15. - pinctrl-0: One property must exist for each entry in pinctrl-names.
  16. See pinctrl/pinctrl-bindings.txt for details of the property values.
  17. Example:
  18. pwm0: pwm@1401e000 {
  19. compatible = "mediatek,mt8173-disp-pwm",
  20. "mediatek,mt6595-disp-pwm";
  21. reg = <0 0x1401e000 0 0x1000>;
  22. #pwm-cells = <2>;
  23. clocks = <&mmsys CLK_MM_DISP_PWM026M>,
  24. <&mmsys CLK_MM_DISP_PWM0MM>;
  25. clock-names = "main", "mm";
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&disp_pwm0_pins>;
  28. };
  29. backlight_lcd: backlight_lcd {
  30. compatible = "pwm-backlight";
  31. pwms = <&pwm0 0 1000000>;
  32. brightness-levels = <
  33. 0 16 32 48 64 80 96 112
  34. 128 144 160 176 192 208 224 240
  35. 255
  36. >;
  37. default-brightness-level = <9>;
  38. power-supply = <&mt6397_vio18_reg>;
  39. enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
  40. };