spi-fsl-dspi.txt 1.7 KB

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  1. ARM Freescale DSPI controller
  2. Required properties:
  3. - compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
  4. "fsl,ls2085a-dspi"
  5. or
  6. "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
  7. - reg : Offset and length of the register set for the device
  8. - interrupts : Should contain SPI controller interrupt
  9. - clocks: from common clock binding: handle to dspi clock.
  10. - clock-names: from common clock binding: Shall be "dspi".
  11. - pinctrl-0: pin control group to be used for this controller.
  12. - pinctrl-names: must contain a "default" entry.
  13. - spi-num-chipselects : the number of the chipselect signals.
  14. - bus-num : the slave chip chipselect signal number.
  15. Optional property:
  16. - big-endian: If present the dspi device's registers are implemented
  17. in big endian mode.
  18. Optional SPI slave node properties:
  19. - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
  20. select and the start of clock signal, at the start of a transfer.
  21. - fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
  22. signal and deactivating chip select, at the end of a transfer.
  23. Example:
  24. dspi0@4002c000 {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. compatible = "fsl,vf610-dspi";
  28. reg = <0x4002c000 0x1000>;
  29. interrupts = <0 67 0x04>;
  30. clocks = <&clks VF610_CLK_DSPI0>;
  31. clock-names = "dspi";
  32. spi-num-chipselects = <5>;
  33. bus-num = <0>;
  34. pinctrl-names = "default";
  35. pinctrl-0 = <&pinctrl_dspi0_1>;
  36. big-endian;
  37. status = "okay";
  38. sflash: at26df081a@0 {
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. compatible = "atmel,at26df081a";
  42. spi-max-frequency = <16000000>;
  43. spi-cpol;
  44. spi-cpha;
  45. reg = <0>;
  46. linux,modalias = "m25p80";
  47. modal = "at26df081a";
  48. fsl,spi-cs-sck-delay = <100>;
  49. fsl,spi-sck-cs-delay = <50>;
  50. };
  51. };