setup.c 6.2 KB

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  1. /*
  2. * Renesas Technology Europe SDK7786 Support.
  3. *
  4. * Copyright (C) 2010 Matt Fleming
  5. * Copyright (C) 2010 Paul Mundt
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/io.h>
  14. #include <linux/regulator/fixed.h>
  15. #include <linux/regulator/machine.h>
  16. #include <linux/smsc911x.h>
  17. #include <linux/i2c.h>
  18. #include <linux/irq.h>
  19. #include <linux/clk.h>
  20. #include <linux/clkdev.h>
  21. #include <mach/fpga.h>
  22. #include <mach/irq.h>
  23. #include <asm/machvec.h>
  24. #include <asm/heartbeat.h>
  25. #include <asm/sizes.h>
  26. #include <asm/clock.h>
  27. #include <asm/reboot.h>
  28. #include <asm/smp-ops.h>
  29. static struct resource heartbeat_resource = {
  30. .start = 0x07fff8b0,
  31. .end = 0x07fff8b0 + sizeof(u16) - 1,
  32. .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
  33. };
  34. static struct platform_device heartbeat_device = {
  35. .name = "heartbeat",
  36. .id = -1,
  37. .num_resources = 1,
  38. .resource = &heartbeat_resource,
  39. };
  40. /* Dummy supplies, where voltage doesn't matter */
  41. static struct regulator_consumer_supply dummy_supplies[] = {
  42. REGULATOR_SUPPLY("vddvario", "smsc911x"),
  43. REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  44. };
  45. static struct resource smsc911x_resources[] = {
  46. [0] = {
  47. .name = "smsc911x-memory",
  48. .start = 0x07ffff00,
  49. .end = 0x07ffff00 + SZ_256 - 1,
  50. .flags = IORESOURCE_MEM,
  51. },
  52. [1] = {
  53. .name = "smsc911x-irq",
  54. .start = evt2irq(0x2c0),
  55. .end = evt2irq(0x2c0),
  56. .flags = IORESOURCE_IRQ,
  57. },
  58. };
  59. static struct smsc911x_platform_config smsc911x_config = {
  60. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  61. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  62. .flags = SMSC911X_USE_32BIT,
  63. .phy_interface = PHY_INTERFACE_MODE_MII,
  64. };
  65. static struct platform_device smsc911x_device = {
  66. .name = "smsc911x",
  67. .id = -1,
  68. .num_resources = ARRAY_SIZE(smsc911x_resources),
  69. .resource = smsc911x_resources,
  70. .dev = {
  71. .platform_data = &smsc911x_config,
  72. },
  73. };
  74. static struct resource smbus_fpga_resource = {
  75. .start = 0x07fff9e0,
  76. .end = 0x07fff9e0 + SZ_32 - 1,
  77. .flags = IORESOURCE_MEM,
  78. };
  79. static struct platform_device smbus_fpga_device = {
  80. .name = "i2c-sdk7786",
  81. .id = 0,
  82. .num_resources = 1,
  83. .resource = &smbus_fpga_resource,
  84. };
  85. static struct resource smbus_pcie_resource = {
  86. .start = 0x07fffc30,
  87. .end = 0x07fffc30 + SZ_32 - 1,
  88. .flags = IORESOURCE_MEM,
  89. };
  90. static struct platform_device smbus_pcie_device = {
  91. .name = "i2c-sdk7786",
  92. .id = 1,
  93. .num_resources = 1,
  94. .resource = &smbus_pcie_resource,
  95. };
  96. static struct i2c_board_info __initdata sdk7786_i2c_devices[] = {
  97. {
  98. I2C_BOARD_INFO("max6900", 0x68),
  99. },
  100. };
  101. static struct platform_device *sh7786_devices[] __initdata = {
  102. &heartbeat_device,
  103. &smsc911x_device,
  104. &smbus_fpga_device,
  105. &smbus_pcie_device,
  106. };
  107. static int sdk7786_i2c_setup(void)
  108. {
  109. unsigned int tmp;
  110. /*
  111. * Hand over I2C control to the FPGA.
  112. */
  113. tmp = fpga_read_reg(SBCR);
  114. tmp &= ~SCBR_I2CCEN;
  115. tmp |= SCBR_I2CMEN;
  116. fpga_write_reg(tmp, SBCR);
  117. return i2c_register_board_info(0, sdk7786_i2c_devices,
  118. ARRAY_SIZE(sdk7786_i2c_devices));
  119. }
  120. static int __init sdk7786_devices_setup(void)
  121. {
  122. int ret;
  123. ret = platform_add_devices(sh7786_devices, ARRAY_SIZE(sh7786_devices));
  124. if (unlikely(ret != 0))
  125. return ret;
  126. return sdk7786_i2c_setup();
  127. }
  128. device_initcall(sdk7786_devices_setup);
  129. static int sdk7786_mode_pins(void)
  130. {
  131. return fpga_read_reg(MODSWR);
  132. }
  133. /*
  134. * FPGA-driven PCIe clocks
  135. *
  136. * Historically these include the oscillator, clock B (slots 2/3/4) and
  137. * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove
  138. * everything under a single PCIe clocks enable bit that happens to map
  139. * to the same bit position as the oscillator bit for earlier FPGA
  140. * versions.
  141. *
  142. * Given that the legacy clocks have the side-effect of shutting the CPU
  143. * off through the FPGA along with the PCI slots, we simply leave them in
  144. * their initial state and don't bother registering them with the clock
  145. * framework.
  146. */
  147. static int sdk7786_pcie_clk_enable(struct clk *clk)
  148. {
  149. fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR);
  150. return 0;
  151. }
  152. static void sdk7786_pcie_clk_disable(struct clk *clk)
  153. {
  154. fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
  155. }
  156. static struct sh_clk_ops sdk7786_pcie_clk_ops = {
  157. .enable = sdk7786_pcie_clk_enable,
  158. .disable = sdk7786_pcie_clk_disable,
  159. };
  160. static struct clk sdk7786_pcie_clk = {
  161. .ops = &sdk7786_pcie_clk_ops,
  162. };
  163. static struct clk_lookup sdk7786_pcie_cl = {
  164. .con_id = "pcie_plat_clk",
  165. .clk = &sdk7786_pcie_clk,
  166. };
  167. static int sdk7786_clk_init(void)
  168. {
  169. struct clk *clk;
  170. int ret;
  171. /*
  172. * Only handle the EXTAL case, anyone interfacing a crystal
  173. * resonator will need to provide their own input clock.
  174. */
  175. if (test_mode_pin(MODE_PIN9))
  176. return -EINVAL;
  177. clk = clk_get(NULL, "extal");
  178. if (IS_ERR(clk))
  179. return PTR_ERR(clk);
  180. ret = clk_set_rate(clk, 33333333);
  181. clk_put(clk);
  182. /*
  183. * Setup the FPGA clocks.
  184. */
  185. ret = clk_register(&sdk7786_pcie_clk);
  186. if (unlikely(ret)) {
  187. pr_err("FPGA clock registration failed\n");
  188. return ret;
  189. }
  190. clkdev_add(&sdk7786_pcie_cl);
  191. return 0;
  192. }
  193. static void sdk7786_restart(char *cmd)
  194. {
  195. fpga_write_reg(0xa5a5, SRSTR);
  196. }
  197. static void sdk7786_power_off(void)
  198. {
  199. fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR);
  200. /*
  201. * It can take up to 20us for the R8C to do its job, back off and
  202. * wait a bit until we've been shut off. Even though newer FPGA
  203. * versions don't set the ACK bit, the latency issue remains.
  204. */
  205. while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0)
  206. cpu_sleep();
  207. }
  208. /* Initialize the board */
  209. static void __init sdk7786_setup(char **cmdline_p)
  210. {
  211. pr_info("Renesas Technology Europe SDK7786 support:\n");
  212. regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
  213. sdk7786_fpga_init();
  214. sdk7786_nmi_init();
  215. pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
  216. machine_ops.restart = sdk7786_restart;
  217. pm_power_off = sdk7786_power_off;
  218. register_smp_ops(&shx3_smp_ops);
  219. }
  220. /*
  221. * The Machine Vector
  222. */
  223. static struct sh_machine_vector mv_sdk7786 __initmv = {
  224. .mv_name = "SDK7786",
  225. .mv_setup = sdk7786_setup,
  226. .mv_mode_pins = sdk7786_mode_pins,
  227. .mv_clk_init = sdk7786_clk_init,
  228. .mv_init_irq = sdk7786_init_irq,
  229. };