ns87303.h 3.2 KB

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  1. /* ns87303.h: Configuration Register Description for the
  2. * National Semiconductor PC87303 (SuperIO).
  3. *
  4. * Copyright (C) 1997 Eddie C. Dost ([email protected])
  5. */
  6. #ifndef _SPARC_NS87303_H
  7. #define _SPARC_NS87303_H 1
  8. /*
  9. * Control Register Index Values
  10. */
  11. #define FER 0x00
  12. #define FAR 0x01
  13. #define PTR 0x02
  14. #define FCR 0x03
  15. #define PCR 0x04
  16. #define KRR 0x05
  17. #define PMC 0x06
  18. #define TUP 0x07
  19. #define SID 0x08
  20. #define ASC 0x09
  21. #define CS0CF0 0x0a
  22. #define CS0CF1 0x0b
  23. #define CS1CF0 0x0c
  24. #define CS1CF1 0x0d
  25. /* Function Enable Register (FER) bits */
  26. #define FER_EDM 0x10 /* Encoded Drive and Motor pin information */
  27. /* Function Address Register (FAR) bits */
  28. #define FAR_LPT_MASK 0x03
  29. #define FAR_LPTB 0x00
  30. #define FAR_LPTA 0x01
  31. #define FAR_LPTC 0x02
  32. /* Power and Test Register (PTR) bits */
  33. #define PTR_LPTB_IRQ7 0x08
  34. #define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */
  35. #define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controls direction */
  36. /* of the parallel port */
  37. /* Function Control Register (FCR) bits */
  38. #define FCR_LDE 0x10 /* Logical Drive Exchange */
  39. #define FCR_ZWS_ENA 0x20 /* Enable short host read/write in ECP/EPP */
  40. /* Printer Control Register (PCR) bits */
  41. #define PCR_EPP_ENABLE 0x01
  42. #define PCR_EPP_IEEE 0x02 /* Enable EPP Version 1.9 (IEEE 1284) */
  43. #define PCR_ECP_ENABLE 0x04
  44. #define PCR_ECP_CLK_ENA 0x08 /* If 0 ECP Clock is stopped on Power down */
  45. #define PCR_IRQ_POLAR 0x20 /* If 0 IRQ is level high or negative pulse, */
  46. /* if 1 polarity is inverted */
  47. #define PCR_IRQ_ODRAIN 0x40 /* If 1, IRQ is open drain */
  48. /* Tape UARTs and Parallel Port Config Register (TUP) bits */
  49. #define TUP_EPP_TIMO 0x02 /* Enable EPP timeout IRQ */
  50. /* Advanced SuperIO Config Register (ASC) bits */
  51. #define ASC_LPT_IRQ7 0x01 /* Always use IRQ7 for LPT */
  52. #define ASC_DRV2_SEL 0x02 /* Logical Drive Exchange controlled by TDR */
  53. #define FER_RESERVED 0x00
  54. #define FAR_RESERVED 0x00
  55. #define PTR_RESERVED 0x73
  56. #define FCR_RESERVED 0xc4
  57. #define PCR_RESERVED 0x10
  58. #define KRR_RESERVED 0x00
  59. #define PMC_RESERVED 0x98
  60. #define TUP_RESERVED 0xfb
  61. #define SIP_RESERVED 0x00
  62. #define ASC_RESERVED 0x18
  63. #define CS0CF0_RESERVED 0x00
  64. #define CS0CF1_RESERVED 0x08
  65. #define CS1CF0_RESERVED 0x00
  66. #define CS1CF1_RESERVED 0x08
  67. #ifdef __KERNEL__
  68. #include <linux/spinlock.h>
  69. #include <asm/io.h>
  70. extern spinlock_t ns87303_lock;
  71. static inline int ns87303_modify(unsigned long port, unsigned int index,
  72. unsigned char clr, unsigned char set)
  73. {
  74. static unsigned char reserved[] = {
  75. FER_RESERVED, FAR_RESERVED, PTR_RESERVED, FCR_RESERVED,
  76. PCR_RESERVED, KRR_RESERVED, PMC_RESERVED, TUP_RESERVED,
  77. SIP_RESERVED, ASC_RESERVED, CS0CF0_RESERVED, CS0CF1_RESERVED,
  78. CS1CF0_RESERVED, CS1CF1_RESERVED
  79. };
  80. unsigned long flags;
  81. unsigned char value;
  82. if (index > 0x0d)
  83. return -EINVAL;
  84. spin_lock_irqsave(&ns87303_lock, flags);
  85. outb(index, port);
  86. value = inb(port + 1);
  87. value &= ~(reserved[index] | clr);
  88. value |= set;
  89. outb(value, port + 1);
  90. outb(value, port + 1);
  91. spin_unlock_irqrestore(&ns87303_lock, flags);
  92. return 0;
  93. }
  94. #endif /* __KERNEL__ */
  95. #endif /* !(_SPARC_NS87303_H) */