mt9m111.c 28 KB

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  1. /*
  2. * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina
  3. *
  4. * Copyright (C) 2008, Robert Jarzmik <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/videodev2.h>
  11. #include <linux/slab.h>
  12. #include <linux/i2c.h>
  13. #include <linux/log2.h>
  14. #include <linux/gpio.h>
  15. #include <linux/delay.h>
  16. #include <linux/v4l2-mediabus.h>
  17. #include <linux/module.h>
  18. #include <media/v4l2-async.h>
  19. #include <media/v4l2-clk.h>
  20. #include <media/v4l2-common.h>
  21. #include <media/v4l2-ctrls.h>
  22. #include <media/v4l2-device.h>
  23. /*
  24. * MT9M111, MT9M112 and MT9M131:
  25. * i2c address is 0x48 or 0x5d (depending on SADDR pin)
  26. * The platform has to define struct i2c_board_info objects and link to them
  27. * from struct soc_camera_host_desc
  28. */
  29. /*
  30. * Sensor core register addresses (0x000..0x0ff)
  31. */
  32. #define MT9M111_CHIP_VERSION 0x000
  33. #define MT9M111_ROW_START 0x001
  34. #define MT9M111_COLUMN_START 0x002
  35. #define MT9M111_WINDOW_HEIGHT 0x003
  36. #define MT9M111_WINDOW_WIDTH 0x004
  37. #define MT9M111_HORIZONTAL_BLANKING_B 0x005
  38. #define MT9M111_VERTICAL_BLANKING_B 0x006
  39. #define MT9M111_HORIZONTAL_BLANKING_A 0x007
  40. #define MT9M111_VERTICAL_BLANKING_A 0x008
  41. #define MT9M111_SHUTTER_WIDTH 0x009
  42. #define MT9M111_ROW_SPEED 0x00a
  43. #define MT9M111_EXTRA_DELAY 0x00b
  44. #define MT9M111_SHUTTER_DELAY 0x00c
  45. #define MT9M111_RESET 0x00d
  46. #define MT9M111_READ_MODE_B 0x020
  47. #define MT9M111_READ_MODE_A 0x021
  48. #define MT9M111_FLASH_CONTROL 0x023
  49. #define MT9M111_GREEN1_GAIN 0x02b
  50. #define MT9M111_BLUE_GAIN 0x02c
  51. #define MT9M111_RED_GAIN 0x02d
  52. #define MT9M111_GREEN2_GAIN 0x02e
  53. #define MT9M111_GLOBAL_GAIN 0x02f
  54. #define MT9M111_CONTEXT_CONTROL 0x0c8
  55. #define MT9M111_PAGE_MAP 0x0f0
  56. #define MT9M111_BYTE_WISE_ADDR 0x0f1
  57. #define MT9M111_RESET_SYNC_CHANGES (1 << 15)
  58. #define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9)
  59. #define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8)
  60. #define MT9M111_RESET_RESET_SOC (1 << 5)
  61. #define MT9M111_RESET_OUTPUT_DISABLE (1 << 4)
  62. #define MT9M111_RESET_CHIP_ENABLE (1 << 3)
  63. #define MT9M111_RESET_ANALOG_STANDBY (1 << 2)
  64. #define MT9M111_RESET_RESTART_FRAME (1 << 1)
  65. #define MT9M111_RESET_RESET_MODE (1 << 0)
  66. #define MT9M111_RM_FULL_POWER_RD (0 << 10)
  67. #define MT9M111_RM_LOW_POWER_RD (1 << 10)
  68. #define MT9M111_RM_COL_SKIP_4X (1 << 5)
  69. #define MT9M111_RM_ROW_SKIP_4X (1 << 4)
  70. #define MT9M111_RM_COL_SKIP_2X (1 << 3)
  71. #define MT9M111_RM_ROW_SKIP_2X (1 << 2)
  72. #define MT9M111_RMB_MIRROR_COLS (1 << 1)
  73. #define MT9M111_RMB_MIRROR_ROWS (1 << 0)
  74. #define MT9M111_CTXT_CTRL_RESTART (1 << 15)
  75. #define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12)
  76. #define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10)
  77. #define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9)
  78. #define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8)
  79. #define MT9M111_CTXT_CTRL_XENON_EN (1 << 7)
  80. #define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3)
  81. #define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2)
  82. #define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1)
  83. #define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0)
  84. /*
  85. * Colorpipe register addresses (0x100..0x1ff)
  86. */
  87. #define MT9M111_OPER_MODE_CTRL 0x106
  88. #define MT9M111_OUTPUT_FORMAT_CTRL 0x108
  89. #define MT9M111_REDUCER_XZOOM_B 0x1a0
  90. #define MT9M111_REDUCER_XSIZE_B 0x1a1
  91. #define MT9M111_REDUCER_YZOOM_B 0x1a3
  92. #define MT9M111_REDUCER_YSIZE_B 0x1a4
  93. #define MT9M111_REDUCER_XZOOM_A 0x1a6
  94. #define MT9M111_REDUCER_XSIZE_A 0x1a7
  95. #define MT9M111_REDUCER_YZOOM_A 0x1a9
  96. #define MT9M111_REDUCER_YSIZE_A 0x1aa
  97. #define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a
  98. #define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b
  99. #define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14)
  100. #define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1)
  101. #define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9)
  102. #define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8)
  103. #define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14)
  104. #define MT9M111_OUTFMT_BYPASS_IFP (1 << 10)
  105. #define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9)
  106. #define MT9M111_OUTFMT_RGB (1 << 8)
  107. #define MT9M111_OUTFMT_RGB565 (0 << 6)
  108. #define MT9M111_OUTFMT_RGB555 (1 << 6)
  109. #define MT9M111_OUTFMT_RGB444x (2 << 6)
  110. #define MT9M111_OUTFMT_RGBx444 (3 << 6)
  111. #define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4)
  112. #define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4)
  113. #define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4)
  114. #define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4)
  115. #define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3)
  116. #define MT9M111_OUTFMT_AVG_CHROMA (1 << 2)
  117. #define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1)
  118. #define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0)
  119. /*
  120. * Camera control register addresses (0x200..0x2ff not implemented)
  121. */
  122. #define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg)
  123. #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val))
  124. #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val))
  125. #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val))
  126. #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \
  127. (val), (mask))
  128. #define MT9M111_MIN_DARK_ROWS 8
  129. #define MT9M111_MIN_DARK_COLS 26
  130. #define MT9M111_MAX_HEIGHT 1024
  131. #define MT9M111_MAX_WIDTH 1280
  132. struct mt9m111_context {
  133. u16 read_mode;
  134. u16 blanking_h;
  135. u16 blanking_v;
  136. u16 reducer_xzoom;
  137. u16 reducer_yzoom;
  138. u16 reducer_xsize;
  139. u16 reducer_ysize;
  140. u16 output_fmt_ctrl2;
  141. u16 control;
  142. };
  143. static struct mt9m111_context context_a = {
  144. .read_mode = MT9M111_READ_MODE_A,
  145. .blanking_h = MT9M111_HORIZONTAL_BLANKING_A,
  146. .blanking_v = MT9M111_VERTICAL_BLANKING_A,
  147. .reducer_xzoom = MT9M111_REDUCER_XZOOM_A,
  148. .reducer_yzoom = MT9M111_REDUCER_YZOOM_A,
  149. .reducer_xsize = MT9M111_REDUCER_XSIZE_A,
  150. .reducer_ysize = MT9M111_REDUCER_YSIZE_A,
  151. .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A,
  152. .control = MT9M111_CTXT_CTRL_RESTART,
  153. };
  154. static struct mt9m111_context context_b = {
  155. .read_mode = MT9M111_READ_MODE_B,
  156. .blanking_h = MT9M111_HORIZONTAL_BLANKING_B,
  157. .blanking_v = MT9M111_VERTICAL_BLANKING_B,
  158. .reducer_xzoom = MT9M111_REDUCER_XZOOM_B,
  159. .reducer_yzoom = MT9M111_REDUCER_YZOOM_B,
  160. .reducer_xsize = MT9M111_REDUCER_XSIZE_B,
  161. .reducer_ysize = MT9M111_REDUCER_YSIZE_B,
  162. .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B,
  163. .control = MT9M111_CTXT_CTRL_RESTART |
  164. MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B |
  165. MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B |
  166. MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B |
  167. MT9M111_CTXT_CTRL_HBLANK_SEL_B,
  168. };
  169. /* MT9M111 has only one fixed colorspace per pixelcode */
  170. struct mt9m111_datafmt {
  171. u32 code;
  172. enum v4l2_colorspace colorspace;
  173. };
  174. static const struct mt9m111_datafmt mt9m111_colour_fmts[] = {
  175. {MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_SRGB},
  176. {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_SRGB},
  177. {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB},
  178. {MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_SRGB},
  179. {MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
  180. {MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
  181. {MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
  182. {MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
  183. {MEDIA_BUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB},
  184. {MEDIA_BUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB},
  185. {MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
  186. {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
  187. };
  188. struct mt9m111 {
  189. struct v4l2_subdev subdev;
  190. struct v4l2_ctrl_handler hdl;
  191. struct v4l2_ctrl *gain;
  192. struct mt9m111_context *ctx;
  193. struct v4l2_rect rect; /* cropping rectangle */
  194. struct v4l2_clk *clk;
  195. unsigned int width; /* output */
  196. unsigned int height; /* sizes */
  197. struct mutex power_lock; /* lock to protect power_count */
  198. int power_count;
  199. const struct mt9m111_datafmt *fmt;
  200. int lastpage; /* PageMap cache value */
  201. };
  202. /* Find a data format by a pixel code */
  203. static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111,
  204. u32 code)
  205. {
  206. int i;
  207. for (i = 0; i < ARRAY_SIZE(mt9m111_colour_fmts); i++)
  208. if (mt9m111_colour_fmts[i].code == code)
  209. return mt9m111_colour_fmts + i;
  210. return mt9m111->fmt;
  211. }
  212. static struct mt9m111 *to_mt9m111(const struct i2c_client *client)
  213. {
  214. return container_of(i2c_get_clientdata(client), struct mt9m111, subdev);
  215. }
  216. static int reg_page_map_set(struct i2c_client *client, const u16 reg)
  217. {
  218. int ret;
  219. u16 page;
  220. struct mt9m111 *mt9m111 = to_mt9m111(client);
  221. page = (reg >> 8);
  222. if (page == mt9m111->lastpage)
  223. return 0;
  224. if (page > 2)
  225. return -EINVAL;
  226. ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page);
  227. if (!ret)
  228. mt9m111->lastpage = page;
  229. return ret;
  230. }
  231. static int mt9m111_reg_read(struct i2c_client *client, const u16 reg)
  232. {
  233. int ret;
  234. ret = reg_page_map_set(client, reg);
  235. if (!ret)
  236. ret = i2c_smbus_read_word_swapped(client, reg & 0xff);
  237. dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret);
  238. return ret;
  239. }
  240. static int mt9m111_reg_write(struct i2c_client *client, const u16 reg,
  241. const u16 data)
  242. {
  243. int ret;
  244. ret = reg_page_map_set(client, reg);
  245. if (!ret)
  246. ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data);
  247. dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret);
  248. return ret;
  249. }
  250. static int mt9m111_reg_set(struct i2c_client *client, const u16 reg,
  251. const u16 data)
  252. {
  253. int ret;
  254. ret = mt9m111_reg_read(client, reg);
  255. if (ret >= 0)
  256. ret = mt9m111_reg_write(client, reg, ret | data);
  257. return ret;
  258. }
  259. static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg,
  260. const u16 data)
  261. {
  262. int ret;
  263. ret = mt9m111_reg_read(client, reg);
  264. if (ret >= 0)
  265. ret = mt9m111_reg_write(client, reg, ret & ~data);
  266. return ret;
  267. }
  268. static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg,
  269. const u16 data, const u16 mask)
  270. {
  271. int ret;
  272. ret = mt9m111_reg_read(client, reg);
  273. if (ret >= 0)
  274. ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data);
  275. return ret;
  276. }
  277. static int mt9m111_set_context(struct mt9m111 *mt9m111,
  278. struct mt9m111_context *ctx)
  279. {
  280. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  281. return reg_write(CONTEXT_CONTROL, ctx->control);
  282. }
  283. static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111,
  284. struct mt9m111_context *ctx, struct v4l2_rect *rect,
  285. unsigned int width, unsigned int height)
  286. {
  287. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  288. int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, rect->width);
  289. if (!ret)
  290. ret = mt9m111_reg_write(client, ctx->reducer_yzoom, rect->height);
  291. if (!ret)
  292. ret = mt9m111_reg_write(client, ctx->reducer_xsize, width);
  293. if (!ret)
  294. ret = mt9m111_reg_write(client, ctx->reducer_ysize, height);
  295. return ret;
  296. }
  297. static int mt9m111_setup_geometry(struct mt9m111 *mt9m111, struct v4l2_rect *rect,
  298. int width, int height, u32 code)
  299. {
  300. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  301. int ret;
  302. ret = reg_write(COLUMN_START, rect->left);
  303. if (!ret)
  304. ret = reg_write(ROW_START, rect->top);
  305. if (!ret)
  306. ret = reg_write(WINDOW_WIDTH, rect->width);
  307. if (!ret)
  308. ret = reg_write(WINDOW_HEIGHT, rect->height);
  309. if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
  310. /* IFP in use, down-scaling possible */
  311. if (!ret)
  312. ret = mt9m111_setup_rect_ctx(mt9m111, &context_b,
  313. rect, width, height);
  314. if (!ret)
  315. ret = mt9m111_setup_rect_ctx(mt9m111, &context_a,
  316. rect, width, height);
  317. }
  318. dev_dbg(&client->dev, "%s(%x): %ux%u@%u:%u -> %ux%u = %d\n",
  319. __func__, code, rect->width, rect->height, rect->left, rect->top,
  320. width, height, ret);
  321. return ret;
  322. }
  323. static int mt9m111_enable(struct mt9m111 *mt9m111)
  324. {
  325. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  326. return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE);
  327. }
  328. static int mt9m111_reset(struct mt9m111 *mt9m111)
  329. {
  330. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  331. int ret;
  332. ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
  333. if (!ret)
  334. ret = reg_set(RESET, MT9M111_RESET_RESET_SOC);
  335. if (!ret)
  336. ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
  337. | MT9M111_RESET_RESET_SOC);
  338. return ret;
  339. }
  340. static int mt9m111_set_selection(struct v4l2_subdev *sd,
  341. struct v4l2_subdev_pad_config *cfg,
  342. struct v4l2_subdev_selection *sel)
  343. {
  344. struct i2c_client *client = v4l2_get_subdevdata(sd);
  345. struct mt9m111 *mt9m111 = to_mt9m111(client);
  346. struct v4l2_rect rect = sel->r;
  347. int width, height;
  348. int ret, align = 0;
  349. if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
  350. sel->target != V4L2_SEL_TGT_CROP)
  351. return -EINVAL;
  352. if (mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 ||
  353. mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
  354. /* Bayer format - even size lengths */
  355. align = 1;
  356. /* Let the user play with the starting pixel */
  357. }
  358. /* FIXME: the datasheet doesn't specify minimum sizes */
  359. v4l_bound_align_image(&rect.width, 2, MT9M111_MAX_WIDTH, align,
  360. &rect.height, 2, MT9M111_MAX_HEIGHT, align, 0);
  361. rect.left = clamp(rect.left, MT9M111_MIN_DARK_COLS,
  362. MT9M111_MIN_DARK_COLS + MT9M111_MAX_WIDTH -
  363. (__s32)rect.width);
  364. rect.top = clamp(rect.top, MT9M111_MIN_DARK_ROWS,
  365. MT9M111_MIN_DARK_ROWS + MT9M111_MAX_HEIGHT -
  366. (__s32)rect.height);
  367. width = min(mt9m111->width, rect.width);
  368. height = min(mt9m111->height, rect.height);
  369. ret = mt9m111_setup_geometry(mt9m111, &rect, width, height, mt9m111->fmt->code);
  370. if (!ret) {
  371. mt9m111->rect = rect;
  372. mt9m111->width = width;
  373. mt9m111->height = height;
  374. }
  375. return ret;
  376. }
  377. static int mt9m111_get_selection(struct v4l2_subdev *sd,
  378. struct v4l2_subdev_pad_config *cfg,
  379. struct v4l2_subdev_selection *sel)
  380. {
  381. struct i2c_client *client = v4l2_get_subdevdata(sd);
  382. struct mt9m111 *mt9m111 = to_mt9m111(client);
  383. if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
  384. return -EINVAL;
  385. switch (sel->target) {
  386. case V4L2_SEL_TGT_CROP_BOUNDS:
  387. case V4L2_SEL_TGT_CROP_DEFAULT:
  388. sel->r.left = MT9M111_MIN_DARK_COLS;
  389. sel->r.top = MT9M111_MIN_DARK_ROWS;
  390. sel->r.width = MT9M111_MAX_WIDTH;
  391. sel->r.height = MT9M111_MAX_HEIGHT;
  392. return 0;
  393. case V4L2_SEL_TGT_CROP:
  394. sel->r = mt9m111->rect;
  395. return 0;
  396. default:
  397. return -EINVAL;
  398. }
  399. }
  400. static int mt9m111_get_fmt(struct v4l2_subdev *sd,
  401. struct v4l2_subdev_pad_config *cfg,
  402. struct v4l2_subdev_format *format)
  403. {
  404. struct v4l2_mbus_framefmt *mf = &format->format;
  405. struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
  406. if (format->pad)
  407. return -EINVAL;
  408. mf->width = mt9m111->width;
  409. mf->height = mt9m111->height;
  410. mf->code = mt9m111->fmt->code;
  411. mf->colorspace = mt9m111->fmt->colorspace;
  412. mf->field = V4L2_FIELD_NONE;
  413. return 0;
  414. }
  415. static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111,
  416. u32 code)
  417. {
  418. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  419. u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
  420. MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB |
  421. MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 |
  422. MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 |
  423. MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
  424. MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
  425. int ret;
  426. switch (code) {
  427. case MEDIA_BUS_FMT_SBGGR8_1X8:
  428. data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
  429. MT9M111_OUTFMT_RGB;
  430. break;
  431. case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
  432. data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB;
  433. break;
  434. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
  435. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 |
  436. MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
  437. break;
  438. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
  439. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555;
  440. break;
  441. case MEDIA_BUS_FMT_RGB565_2X8_LE:
  442. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
  443. MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
  444. break;
  445. case MEDIA_BUS_FMT_RGB565_2X8_BE:
  446. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565;
  447. break;
  448. case MEDIA_BUS_FMT_BGR565_2X8_BE:
  449. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
  450. MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
  451. break;
  452. case MEDIA_BUS_FMT_BGR565_2X8_LE:
  453. data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
  454. MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
  455. MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
  456. break;
  457. case MEDIA_BUS_FMT_UYVY8_2X8:
  458. data_outfmt2 = 0;
  459. break;
  460. case MEDIA_BUS_FMT_VYUY8_2X8:
  461. data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
  462. break;
  463. case MEDIA_BUS_FMT_YUYV8_2X8:
  464. data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
  465. break;
  466. case MEDIA_BUS_FMT_YVYU8_2X8:
  467. data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
  468. MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
  469. break;
  470. default:
  471. dev_err(&client->dev, "Pixel format not handled: %x\n", code);
  472. return -EINVAL;
  473. }
  474. ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2,
  475. data_outfmt2, mask_outfmt2);
  476. if (!ret)
  477. ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2,
  478. data_outfmt2, mask_outfmt2);
  479. return ret;
  480. }
  481. static int mt9m111_set_fmt(struct v4l2_subdev *sd,
  482. struct v4l2_subdev_pad_config *cfg,
  483. struct v4l2_subdev_format *format)
  484. {
  485. struct v4l2_mbus_framefmt *mf = &format->format;
  486. struct i2c_client *client = v4l2_get_subdevdata(sd);
  487. struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
  488. const struct mt9m111_datafmt *fmt;
  489. struct v4l2_rect *rect = &mt9m111->rect;
  490. bool bayer;
  491. int ret;
  492. if (format->pad)
  493. return -EINVAL;
  494. fmt = mt9m111_find_datafmt(mt9m111, mf->code);
  495. bayer = fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 ||
  496. fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE;
  497. /*
  498. * With Bayer format enforce even side lengths, but let the user play
  499. * with the starting pixel
  500. */
  501. if (bayer) {
  502. rect->width = ALIGN(rect->width, 2);
  503. rect->height = ALIGN(rect->height, 2);
  504. }
  505. if (fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
  506. /* IFP bypass mode, no scaling */
  507. mf->width = rect->width;
  508. mf->height = rect->height;
  509. } else {
  510. /* No upscaling */
  511. if (mf->width > rect->width)
  512. mf->width = rect->width;
  513. if (mf->height > rect->height)
  514. mf->height = rect->height;
  515. }
  516. dev_dbg(&client->dev, "%s(): %ux%u, code=%x\n", __func__,
  517. mf->width, mf->height, fmt->code);
  518. mf->code = fmt->code;
  519. mf->colorspace = fmt->colorspace;
  520. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  521. cfg->try_fmt = *mf;
  522. return 0;
  523. }
  524. ret = mt9m111_setup_geometry(mt9m111, rect, mf->width, mf->height, mf->code);
  525. if (!ret)
  526. ret = mt9m111_set_pixfmt(mt9m111, mf->code);
  527. if (!ret) {
  528. mt9m111->width = mf->width;
  529. mt9m111->height = mf->height;
  530. mt9m111->fmt = fmt;
  531. }
  532. return ret;
  533. }
  534. #ifdef CONFIG_VIDEO_ADV_DEBUG
  535. static int mt9m111_g_register(struct v4l2_subdev *sd,
  536. struct v4l2_dbg_register *reg)
  537. {
  538. struct i2c_client *client = v4l2_get_subdevdata(sd);
  539. int val;
  540. if (reg->reg > 0x2ff)
  541. return -EINVAL;
  542. val = mt9m111_reg_read(client, reg->reg);
  543. reg->size = 2;
  544. reg->val = (u64)val;
  545. if (reg->val > 0xffff)
  546. return -EIO;
  547. return 0;
  548. }
  549. static int mt9m111_s_register(struct v4l2_subdev *sd,
  550. const struct v4l2_dbg_register *reg)
  551. {
  552. struct i2c_client *client = v4l2_get_subdevdata(sd);
  553. if (reg->reg > 0x2ff)
  554. return -EINVAL;
  555. if (mt9m111_reg_write(client, reg->reg, reg->val) < 0)
  556. return -EIO;
  557. return 0;
  558. }
  559. #endif
  560. static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask)
  561. {
  562. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  563. int ret;
  564. if (flip)
  565. ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask);
  566. else
  567. ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask);
  568. return ret;
  569. }
  570. static int mt9m111_get_global_gain(struct mt9m111 *mt9m111)
  571. {
  572. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  573. int data;
  574. data = reg_read(GLOBAL_GAIN);
  575. if (data >= 0)
  576. return (data & 0x2f) * (1 << ((data >> 10) & 1)) *
  577. (1 << ((data >> 9) & 1));
  578. return data;
  579. }
  580. static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain)
  581. {
  582. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  583. u16 val;
  584. if (gain > 63 * 2 * 2)
  585. return -EINVAL;
  586. if ((gain >= 64 * 2) && (gain < 63 * 2 * 2))
  587. val = (1 << 10) | (1 << 9) | (gain / 4);
  588. else if ((gain >= 64) && (gain < 64 * 2))
  589. val = (1 << 9) | (gain / 2);
  590. else
  591. val = gain;
  592. return reg_write(GLOBAL_GAIN, val);
  593. }
  594. static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int val)
  595. {
  596. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  597. if (val == V4L2_EXPOSURE_AUTO)
  598. return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
  599. return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
  600. }
  601. static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on)
  602. {
  603. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  604. if (on)
  605. return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
  606. return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
  607. }
  608. static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl)
  609. {
  610. struct mt9m111 *mt9m111 = container_of(ctrl->handler,
  611. struct mt9m111, hdl);
  612. switch (ctrl->id) {
  613. case V4L2_CID_VFLIP:
  614. return mt9m111_set_flip(mt9m111, ctrl->val,
  615. MT9M111_RMB_MIRROR_ROWS);
  616. case V4L2_CID_HFLIP:
  617. return mt9m111_set_flip(mt9m111, ctrl->val,
  618. MT9M111_RMB_MIRROR_COLS);
  619. case V4L2_CID_GAIN:
  620. return mt9m111_set_global_gain(mt9m111, ctrl->val);
  621. case V4L2_CID_EXPOSURE_AUTO:
  622. return mt9m111_set_autoexposure(mt9m111, ctrl->val);
  623. case V4L2_CID_AUTO_WHITE_BALANCE:
  624. return mt9m111_set_autowhitebalance(mt9m111, ctrl->val);
  625. }
  626. return -EINVAL;
  627. }
  628. static int mt9m111_suspend(struct mt9m111 *mt9m111)
  629. {
  630. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  631. int ret;
  632. v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111));
  633. ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
  634. if (!ret)
  635. ret = reg_set(RESET, MT9M111_RESET_RESET_SOC |
  636. MT9M111_RESET_OUTPUT_DISABLE |
  637. MT9M111_RESET_ANALOG_STANDBY);
  638. if (!ret)
  639. ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
  640. return ret;
  641. }
  642. static void mt9m111_restore_state(struct mt9m111 *mt9m111)
  643. {
  644. mt9m111_set_context(mt9m111, mt9m111->ctx);
  645. mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code);
  646. mt9m111_setup_geometry(mt9m111, &mt9m111->rect,
  647. mt9m111->width, mt9m111->height, mt9m111->fmt->code);
  648. v4l2_ctrl_handler_setup(&mt9m111->hdl);
  649. }
  650. static int mt9m111_resume(struct mt9m111 *mt9m111)
  651. {
  652. int ret = mt9m111_enable(mt9m111);
  653. if (!ret)
  654. ret = mt9m111_reset(mt9m111);
  655. if (!ret)
  656. mt9m111_restore_state(mt9m111);
  657. return ret;
  658. }
  659. static int mt9m111_init(struct mt9m111 *mt9m111)
  660. {
  661. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  662. int ret;
  663. ret = mt9m111_enable(mt9m111);
  664. if (!ret)
  665. ret = mt9m111_reset(mt9m111);
  666. if (!ret)
  667. ret = mt9m111_set_context(mt9m111, mt9m111->ctx);
  668. if (ret)
  669. dev_err(&client->dev, "mt9m111 init failed: %d\n", ret);
  670. return ret;
  671. }
  672. static int mt9m111_power_on(struct mt9m111 *mt9m111)
  673. {
  674. struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
  675. int ret;
  676. ret = v4l2_clk_enable(mt9m111->clk);
  677. if (ret < 0)
  678. return ret;
  679. ret = mt9m111_resume(mt9m111);
  680. if (ret < 0) {
  681. dev_err(&client->dev, "Failed to resume the sensor: %d\n", ret);
  682. v4l2_clk_disable(mt9m111->clk);
  683. }
  684. return ret;
  685. }
  686. static void mt9m111_power_off(struct mt9m111 *mt9m111)
  687. {
  688. mt9m111_suspend(mt9m111);
  689. v4l2_clk_disable(mt9m111->clk);
  690. }
  691. static int mt9m111_s_power(struct v4l2_subdev *sd, int on)
  692. {
  693. struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
  694. int ret = 0;
  695. mutex_lock(&mt9m111->power_lock);
  696. /*
  697. * If the power count is modified from 0 to != 0 or from != 0 to 0,
  698. * update the power state.
  699. */
  700. if (mt9m111->power_count == !on) {
  701. if (on)
  702. ret = mt9m111_power_on(mt9m111);
  703. else
  704. mt9m111_power_off(mt9m111);
  705. }
  706. if (!ret) {
  707. /* Update the power count. */
  708. mt9m111->power_count += on ? 1 : -1;
  709. WARN_ON(mt9m111->power_count < 0);
  710. }
  711. mutex_unlock(&mt9m111->power_lock);
  712. return ret;
  713. }
  714. static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = {
  715. .s_ctrl = mt9m111_s_ctrl,
  716. };
  717. static struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = {
  718. .s_power = mt9m111_s_power,
  719. #ifdef CONFIG_VIDEO_ADV_DEBUG
  720. .g_register = mt9m111_g_register,
  721. .s_register = mt9m111_s_register,
  722. #endif
  723. };
  724. static int mt9m111_enum_mbus_code(struct v4l2_subdev *sd,
  725. struct v4l2_subdev_pad_config *cfg,
  726. struct v4l2_subdev_mbus_code_enum *code)
  727. {
  728. if (code->pad || code->index >= ARRAY_SIZE(mt9m111_colour_fmts))
  729. return -EINVAL;
  730. code->code = mt9m111_colour_fmts[code->index].code;
  731. return 0;
  732. }
  733. static int mt9m111_g_mbus_config(struct v4l2_subdev *sd,
  734. struct v4l2_mbus_config *cfg)
  735. {
  736. cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
  737. V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
  738. V4L2_MBUS_DATA_ACTIVE_HIGH;
  739. cfg->type = V4L2_MBUS_PARALLEL;
  740. return 0;
  741. }
  742. static struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = {
  743. .g_mbus_config = mt9m111_g_mbus_config,
  744. };
  745. static const struct v4l2_subdev_pad_ops mt9m111_subdev_pad_ops = {
  746. .enum_mbus_code = mt9m111_enum_mbus_code,
  747. .get_selection = mt9m111_get_selection,
  748. .set_selection = mt9m111_set_selection,
  749. .get_fmt = mt9m111_get_fmt,
  750. .set_fmt = mt9m111_set_fmt,
  751. };
  752. static struct v4l2_subdev_ops mt9m111_subdev_ops = {
  753. .core = &mt9m111_subdev_core_ops,
  754. .video = &mt9m111_subdev_video_ops,
  755. .pad = &mt9m111_subdev_pad_ops,
  756. };
  757. /*
  758. * Interface active, can use i2c. If it fails, it can indeed mean, that
  759. * this wasn't our capture interface, so, we wait for the right one
  760. */
  761. static int mt9m111_video_probe(struct i2c_client *client)
  762. {
  763. struct mt9m111 *mt9m111 = to_mt9m111(client);
  764. s32 data;
  765. int ret;
  766. ret = mt9m111_s_power(&mt9m111->subdev, 1);
  767. if (ret < 0)
  768. return ret;
  769. data = reg_read(CHIP_VERSION);
  770. switch (data) {
  771. case 0x143a: /* MT9M111 or MT9M131 */
  772. dev_info(&client->dev,
  773. "Detected a MT9M111/MT9M131 chip ID %x\n", data);
  774. break;
  775. case 0x148c: /* MT9M112 */
  776. dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data);
  777. break;
  778. default:
  779. dev_err(&client->dev,
  780. "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n",
  781. data);
  782. ret = -ENODEV;
  783. goto done;
  784. }
  785. ret = mt9m111_init(mt9m111);
  786. if (ret)
  787. goto done;
  788. ret = v4l2_ctrl_handler_setup(&mt9m111->hdl);
  789. done:
  790. mt9m111_s_power(&mt9m111->subdev, 0);
  791. return ret;
  792. }
  793. static int mt9m111_probe(struct i2c_client *client,
  794. const struct i2c_device_id *did)
  795. {
  796. struct mt9m111 *mt9m111;
  797. struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
  798. int ret;
  799. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
  800. dev_warn(&adapter->dev,
  801. "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
  802. return -EIO;
  803. }
  804. mt9m111 = devm_kzalloc(&client->dev, sizeof(struct mt9m111), GFP_KERNEL);
  805. if (!mt9m111)
  806. return -ENOMEM;
  807. mt9m111->clk = v4l2_clk_get(&client->dev, "mclk");
  808. if (IS_ERR(mt9m111->clk))
  809. return -EPROBE_DEFER;
  810. /* Default HIGHPOWER context */
  811. mt9m111->ctx = &context_b;
  812. v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops);
  813. v4l2_ctrl_handler_init(&mt9m111->hdl, 5);
  814. v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
  815. V4L2_CID_VFLIP, 0, 1, 1, 0);
  816. v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
  817. V4L2_CID_HFLIP, 0, 1, 1, 0);
  818. v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
  819. V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
  820. mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
  821. V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32);
  822. v4l2_ctrl_new_std_menu(&mt9m111->hdl,
  823. &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
  824. V4L2_EXPOSURE_AUTO);
  825. mt9m111->subdev.ctrl_handler = &mt9m111->hdl;
  826. if (mt9m111->hdl.error) {
  827. ret = mt9m111->hdl.error;
  828. goto out_clkput;
  829. }
  830. /* Second stage probe - when a capture adapter is there */
  831. mt9m111->rect.left = MT9M111_MIN_DARK_COLS;
  832. mt9m111->rect.top = MT9M111_MIN_DARK_ROWS;
  833. mt9m111->rect.width = MT9M111_MAX_WIDTH;
  834. mt9m111->rect.height = MT9M111_MAX_HEIGHT;
  835. mt9m111->width = mt9m111->rect.width;
  836. mt9m111->height = mt9m111->rect.height;
  837. mt9m111->fmt = &mt9m111_colour_fmts[0];
  838. mt9m111->lastpage = -1;
  839. mutex_init(&mt9m111->power_lock);
  840. ret = mt9m111_video_probe(client);
  841. if (ret < 0)
  842. goto out_hdlfree;
  843. mt9m111->subdev.dev = &client->dev;
  844. ret = v4l2_async_register_subdev(&mt9m111->subdev);
  845. if (ret < 0)
  846. goto out_hdlfree;
  847. return 0;
  848. out_hdlfree:
  849. v4l2_ctrl_handler_free(&mt9m111->hdl);
  850. out_clkput:
  851. v4l2_clk_put(mt9m111->clk);
  852. return ret;
  853. }
  854. static int mt9m111_remove(struct i2c_client *client)
  855. {
  856. struct mt9m111 *mt9m111 = to_mt9m111(client);
  857. v4l2_async_unregister_subdev(&mt9m111->subdev);
  858. v4l2_clk_put(mt9m111->clk);
  859. v4l2_ctrl_handler_free(&mt9m111->hdl);
  860. return 0;
  861. }
  862. static const struct of_device_id mt9m111_of_match[] = {
  863. { .compatible = "micron,mt9m111", },
  864. {},
  865. };
  866. MODULE_DEVICE_TABLE(of, mt9m111_of_match);
  867. static const struct i2c_device_id mt9m111_id[] = {
  868. { "mt9m111", 0 },
  869. { }
  870. };
  871. MODULE_DEVICE_TABLE(i2c, mt9m111_id);
  872. static struct i2c_driver mt9m111_i2c_driver = {
  873. .driver = {
  874. .name = "mt9m111",
  875. .of_match_table = of_match_ptr(mt9m111_of_match),
  876. },
  877. .probe = mt9m111_probe,
  878. .remove = mt9m111_remove,
  879. .id_table = mt9m111_id,
  880. };
  881. module_i2c_driver(mt9m111_i2c_driver);
  882. MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver");
  883. MODULE_AUTHOR("Robert Jarzmik");
  884. MODULE_LICENSE("GPL");