ov9740.c 26 KB

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  1. /*
  2. * OmniVision OV9740 Camera Driver
  3. *
  4. * Copyright (C) 2011 NVIDIA Corporation
  5. *
  6. * Based on ov9640 camera driver.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/i2c.h>
  15. #include <linux/slab.h>
  16. #include <linux/v4l2-mediabus.h>
  17. #include <media/soc_camera.h>
  18. #include <media/v4l2-clk.h>
  19. #include <media/v4l2-ctrls.h>
  20. #define to_ov9740(sd) container_of(sd, struct ov9740_priv, subdev)
  21. /* General Status Registers */
  22. #define OV9740_MODEL_ID_HI 0x0000
  23. #define OV9740_MODEL_ID_LO 0x0001
  24. #define OV9740_REVISION_NUMBER 0x0002
  25. #define OV9740_MANUFACTURER_ID 0x0003
  26. #define OV9740_SMIA_VERSION 0x0004
  27. /* General Setup Registers */
  28. #define OV9740_MODE_SELECT 0x0100
  29. #define OV9740_IMAGE_ORT 0x0101
  30. #define OV9740_SOFTWARE_RESET 0x0103
  31. #define OV9740_GRP_PARAM_HOLD 0x0104
  32. #define OV9740_MSK_CORRUP_FM 0x0105
  33. /* Timing Setting */
  34. #define OV9740_FRM_LENGTH_LN_HI 0x0340 /* VTS */
  35. #define OV9740_FRM_LENGTH_LN_LO 0x0341 /* VTS */
  36. #define OV9740_LN_LENGTH_PCK_HI 0x0342 /* HTS */
  37. #define OV9740_LN_LENGTH_PCK_LO 0x0343 /* HTS */
  38. #define OV9740_X_ADDR_START_HI 0x0344
  39. #define OV9740_X_ADDR_START_LO 0x0345
  40. #define OV9740_Y_ADDR_START_HI 0x0346
  41. #define OV9740_Y_ADDR_START_LO 0x0347
  42. #define OV9740_X_ADDR_END_HI 0x0348
  43. #define OV9740_X_ADDR_END_LO 0x0349
  44. #define OV9740_Y_ADDR_END_HI 0x034a
  45. #define OV9740_Y_ADDR_END_LO 0x034b
  46. #define OV9740_X_OUTPUT_SIZE_HI 0x034c
  47. #define OV9740_X_OUTPUT_SIZE_LO 0x034d
  48. #define OV9740_Y_OUTPUT_SIZE_HI 0x034e
  49. #define OV9740_Y_OUTPUT_SIZE_LO 0x034f
  50. /* IO Control Registers */
  51. #define OV9740_IO_CREL00 0x3002
  52. #define OV9740_IO_CREL01 0x3004
  53. #define OV9740_IO_CREL02 0x3005
  54. #define OV9740_IO_OUTPUT_SEL01 0x3026
  55. #define OV9740_IO_OUTPUT_SEL02 0x3027
  56. /* AWB Registers */
  57. #define OV9740_AWB_MANUAL_CTRL 0x3406
  58. /* Analog Control Registers */
  59. #define OV9740_ANALOG_CTRL01 0x3601
  60. #define OV9740_ANALOG_CTRL02 0x3602
  61. #define OV9740_ANALOG_CTRL03 0x3603
  62. #define OV9740_ANALOG_CTRL04 0x3604
  63. #define OV9740_ANALOG_CTRL10 0x3610
  64. #define OV9740_ANALOG_CTRL12 0x3612
  65. #define OV9740_ANALOG_CTRL15 0x3615
  66. #define OV9740_ANALOG_CTRL20 0x3620
  67. #define OV9740_ANALOG_CTRL21 0x3621
  68. #define OV9740_ANALOG_CTRL22 0x3622
  69. #define OV9740_ANALOG_CTRL30 0x3630
  70. #define OV9740_ANALOG_CTRL31 0x3631
  71. #define OV9740_ANALOG_CTRL32 0x3632
  72. #define OV9740_ANALOG_CTRL33 0x3633
  73. /* Sensor Control */
  74. #define OV9740_SENSOR_CTRL03 0x3703
  75. #define OV9740_SENSOR_CTRL04 0x3704
  76. #define OV9740_SENSOR_CTRL05 0x3705
  77. #define OV9740_SENSOR_CTRL07 0x3707
  78. /* Timing Control */
  79. #define OV9740_TIMING_CTRL17 0x3817
  80. #define OV9740_TIMING_CTRL19 0x3819
  81. #define OV9740_TIMING_CTRL33 0x3833
  82. #define OV9740_TIMING_CTRL35 0x3835
  83. /* Banding Filter */
  84. #define OV9740_AEC_MAXEXPO_60_H 0x3a02
  85. #define OV9740_AEC_MAXEXPO_60_L 0x3a03
  86. #define OV9740_AEC_B50_STEP_HI 0x3a08
  87. #define OV9740_AEC_B50_STEP_LO 0x3a09
  88. #define OV9740_AEC_B60_STEP_HI 0x3a0a
  89. #define OV9740_AEC_B60_STEP_LO 0x3a0b
  90. #define OV9740_AEC_CTRL0D 0x3a0d
  91. #define OV9740_AEC_CTRL0E 0x3a0e
  92. #define OV9740_AEC_MAXEXPO_50_H 0x3a14
  93. #define OV9740_AEC_MAXEXPO_50_L 0x3a15
  94. /* AEC/AGC Control */
  95. #define OV9740_AEC_ENABLE 0x3503
  96. #define OV9740_GAIN_CEILING_01 0x3a18
  97. #define OV9740_GAIN_CEILING_02 0x3a19
  98. #define OV9740_AEC_HI_THRESHOLD 0x3a11
  99. #define OV9740_AEC_3A1A 0x3a1a
  100. #define OV9740_AEC_CTRL1B_WPT2 0x3a1b
  101. #define OV9740_AEC_CTRL0F_WPT 0x3a0f
  102. #define OV9740_AEC_CTRL10_BPT 0x3a10
  103. #define OV9740_AEC_CTRL1E_BPT2 0x3a1e
  104. #define OV9740_AEC_LO_THRESHOLD 0x3a1f
  105. /* BLC Control */
  106. #define OV9740_BLC_AUTO_ENABLE 0x4002
  107. #define OV9740_BLC_MODE 0x4005
  108. /* VFIFO */
  109. #define OV9740_VFIFO_READ_START_HI 0x4608
  110. #define OV9740_VFIFO_READ_START_LO 0x4609
  111. /* DVP Control */
  112. #define OV9740_DVP_VSYNC_CTRL02 0x4702
  113. #define OV9740_DVP_VSYNC_MODE 0x4704
  114. #define OV9740_DVP_VSYNC_CTRL06 0x4706
  115. /* PLL Setting */
  116. #define OV9740_PLL_MODE_CTRL01 0x3104
  117. #define OV9740_PRE_PLL_CLK_DIV 0x0305
  118. #define OV9740_PLL_MULTIPLIER 0x0307
  119. #define OV9740_VT_SYS_CLK_DIV 0x0303
  120. #define OV9740_VT_PIX_CLK_DIV 0x0301
  121. #define OV9740_PLL_CTRL3010 0x3010
  122. #define OV9740_VFIFO_CTRL00 0x460e
  123. /* ISP Control */
  124. #define OV9740_ISP_CTRL00 0x5000
  125. #define OV9740_ISP_CTRL01 0x5001
  126. #define OV9740_ISP_CTRL03 0x5003
  127. #define OV9740_ISP_CTRL05 0x5005
  128. #define OV9740_ISP_CTRL12 0x5012
  129. #define OV9740_ISP_CTRL19 0x5019
  130. #define OV9740_ISP_CTRL1A 0x501a
  131. #define OV9740_ISP_CTRL1E 0x501e
  132. #define OV9740_ISP_CTRL1F 0x501f
  133. #define OV9740_ISP_CTRL20 0x5020
  134. #define OV9740_ISP_CTRL21 0x5021
  135. /* AWB */
  136. #define OV9740_AWB_CTRL00 0x5180
  137. #define OV9740_AWB_CTRL01 0x5181
  138. #define OV9740_AWB_CTRL02 0x5182
  139. #define OV9740_AWB_CTRL03 0x5183
  140. #define OV9740_AWB_ADV_CTRL01 0x5184
  141. #define OV9740_AWB_ADV_CTRL02 0x5185
  142. #define OV9740_AWB_ADV_CTRL03 0x5186
  143. #define OV9740_AWB_ADV_CTRL04 0x5187
  144. #define OV9740_AWB_ADV_CTRL05 0x5188
  145. #define OV9740_AWB_ADV_CTRL06 0x5189
  146. #define OV9740_AWB_ADV_CTRL07 0x518a
  147. #define OV9740_AWB_ADV_CTRL08 0x518b
  148. #define OV9740_AWB_ADV_CTRL09 0x518c
  149. #define OV9740_AWB_ADV_CTRL10 0x518d
  150. #define OV9740_AWB_ADV_CTRL11 0x518e
  151. #define OV9740_AWB_CTRL0F 0x518f
  152. #define OV9740_AWB_CTRL10 0x5190
  153. #define OV9740_AWB_CTRL11 0x5191
  154. #define OV9740_AWB_CTRL12 0x5192
  155. #define OV9740_AWB_CTRL13 0x5193
  156. #define OV9740_AWB_CTRL14 0x5194
  157. /* MIPI Control */
  158. #define OV9740_MIPI_CTRL00 0x4800
  159. #define OV9740_MIPI_3837 0x3837
  160. #define OV9740_MIPI_CTRL01 0x4801
  161. #define OV9740_MIPI_CTRL03 0x4803
  162. #define OV9740_MIPI_CTRL05 0x4805
  163. #define OV9740_VFIFO_RD_CTRL 0x4601
  164. #define OV9740_MIPI_CTRL_3012 0x3012
  165. #define OV9740_SC_CMMM_MIPI_CTR 0x3014
  166. #define OV9740_MAX_WIDTH 1280
  167. #define OV9740_MAX_HEIGHT 720
  168. /* Misc. structures */
  169. struct ov9740_reg {
  170. u16 reg;
  171. u8 val;
  172. };
  173. struct ov9740_priv {
  174. struct v4l2_subdev subdev;
  175. struct v4l2_ctrl_handler hdl;
  176. struct v4l2_clk *clk;
  177. u16 model;
  178. u8 revision;
  179. u8 manid;
  180. u8 smiaver;
  181. bool flag_vflip;
  182. bool flag_hflip;
  183. /* For suspend/resume. */
  184. struct v4l2_mbus_framefmt current_mf;
  185. bool current_enable;
  186. };
  187. static const struct ov9740_reg ov9740_defaults[] = {
  188. /* Software Reset */
  189. { OV9740_SOFTWARE_RESET, 0x01 },
  190. /* Banding Filter */
  191. { OV9740_AEC_B50_STEP_HI, 0x00 },
  192. { OV9740_AEC_B50_STEP_LO, 0xe8 },
  193. { OV9740_AEC_CTRL0E, 0x03 },
  194. { OV9740_AEC_MAXEXPO_50_H, 0x15 },
  195. { OV9740_AEC_MAXEXPO_50_L, 0xc6 },
  196. { OV9740_AEC_B60_STEP_HI, 0x00 },
  197. { OV9740_AEC_B60_STEP_LO, 0xc0 },
  198. { OV9740_AEC_CTRL0D, 0x04 },
  199. { OV9740_AEC_MAXEXPO_60_H, 0x18 },
  200. { OV9740_AEC_MAXEXPO_60_L, 0x20 },
  201. /* LC */
  202. { 0x5842, 0x02 }, { 0x5843, 0x5e }, { 0x5844, 0x04 }, { 0x5845, 0x32 },
  203. { 0x5846, 0x03 }, { 0x5847, 0x29 }, { 0x5848, 0x02 }, { 0x5849, 0xcc },
  204. /* Un-documented OV9740 registers */
  205. { 0x5800, 0x29 }, { 0x5801, 0x25 }, { 0x5802, 0x20 }, { 0x5803, 0x21 },
  206. { 0x5804, 0x26 }, { 0x5805, 0x2e }, { 0x5806, 0x11 }, { 0x5807, 0x0c },
  207. { 0x5808, 0x09 }, { 0x5809, 0x0a }, { 0x580a, 0x0e }, { 0x580b, 0x16 },
  208. { 0x580c, 0x06 }, { 0x580d, 0x02 }, { 0x580e, 0x00 }, { 0x580f, 0x00 },
  209. { 0x5810, 0x04 }, { 0x5811, 0x0a }, { 0x5812, 0x05 }, { 0x5813, 0x02 },
  210. { 0x5814, 0x00 }, { 0x5815, 0x00 }, { 0x5816, 0x03 }, { 0x5817, 0x09 },
  211. { 0x5818, 0x0f }, { 0x5819, 0x0a }, { 0x581a, 0x07 }, { 0x581b, 0x08 },
  212. { 0x581c, 0x0b }, { 0x581d, 0x14 }, { 0x581e, 0x28 }, { 0x581f, 0x23 },
  213. { 0x5820, 0x1d }, { 0x5821, 0x1e }, { 0x5822, 0x24 }, { 0x5823, 0x2a },
  214. { 0x5824, 0x4f }, { 0x5825, 0x6f }, { 0x5826, 0x5f }, { 0x5827, 0x7f },
  215. { 0x5828, 0x9f }, { 0x5829, 0x5f }, { 0x582a, 0x8f }, { 0x582b, 0x9e },
  216. { 0x582c, 0x8f }, { 0x582d, 0x9f }, { 0x582e, 0x4f }, { 0x582f, 0x87 },
  217. { 0x5830, 0x86 }, { 0x5831, 0x97 }, { 0x5832, 0xae }, { 0x5833, 0x3f },
  218. { 0x5834, 0x8e }, { 0x5835, 0x7c }, { 0x5836, 0x7e }, { 0x5837, 0xaf },
  219. { 0x5838, 0x8f }, { 0x5839, 0x8f }, { 0x583a, 0x9f }, { 0x583b, 0x7f },
  220. { 0x583c, 0x5f },
  221. /* Y Gamma */
  222. { 0x5480, 0x07 }, { 0x5481, 0x18 }, { 0x5482, 0x2c }, { 0x5483, 0x4e },
  223. { 0x5484, 0x5e }, { 0x5485, 0x6b }, { 0x5486, 0x77 }, { 0x5487, 0x82 },
  224. { 0x5488, 0x8c }, { 0x5489, 0x95 }, { 0x548a, 0xa4 }, { 0x548b, 0xb1 },
  225. { 0x548c, 0xc6 }, { 0x548d, 0xd8 }, { 0x548e, 0xe9 },
  226. /* UV Gamma */
  227. { 0x5490, 0x0f }, { 0x5491, 0xff }, { 0x5492, 0x0d }, { 0x5493, 0x05 },
  228. { 0x5494, 0x07 }, { 0x5495, 0x1a }, { 0x5496, 0x04 }, { 0x5497, 0x01 },
  229. { 0x5498, 0x03 }, { 0x5499, 0x53 }, { 0x549a, 0x02 }, { 0x549b, 0xeb },
  230. { 0x549c, 0x02 }, { 0x549d, 0xa0 }, { 0x549e, 0x02 }, { 0x549f, 0x67 },
  231. { 0x54a0, 0x02 }, { 0x54a1, 0x3b }, { 0x54a2, 0x02 }, { 0x54a3, 0x18 },
  232. { 0x54a4, 0x01 }, { 0x54a5, 0xe7 }, { 0x54a6, 0x01 }, { 0x54a7, 0xc3 },
  233. { 0x54a8, 0x01 }, { 0x54a9, 0x94 }, { 0x54aa, 0x01 }, { 0x54ab, 0x72 },
  234. { 0x54ac, 0x01 }, { 0x54ad, 0x57 },
  235. /* AWB */
  236. { OV9740_AWB_CTRL00, 0xf0 },
  237. { OV9740_AWB_CTRL01, 0x00 },
  238. { OV9740_AWB_CTRL02, 0x41 },
  239. { OV9740_AWB_CTRL03, 0x42 },
  240. { OV9740_AWB_ADV_CTRL01, 0x8a },
  241. { OV9740_AWB_ADV_CTRL02, 0x61 },
  242. { OV9740_AWB_ADV_CTRL03, 0xce },
  243. { OV9740_AWB_ADV_CTRL04, 0xa8 },
  244. { OV9740_AWB_ADV_CTRL05, 0x17 },
  245. { OV9740_AWB_ADV_CTRL06, 0x1f },
  246. { OV9740_AWB_ADV_CTRL07, 0x27 },
  247. { OV9740_AWB_ADV_CTRL08, 0x41 },
  248. { OV9740_AWB_ADV_CTRL09, 0x34 },
  249. { OV9740_AWB_ADV_CTRL10, 0xf0 },
  250. { OV9740_AWB_ADV_CTRL11, 0x10 },
  251. { OV9740_AWB_CTRL0F, 0xff },
  252. { OV9740_AWB_CTRL10, 0x00 },
  253. { OV9740_AWB_CTRL11, 0xff },
  254. { OV9740_AWB_CTRL12, 0x00 },
  255. { OV9740_AWB_CTRL13, 0xff },
  256. { OV9740_AWB_CTRL14, 0x00 },
  257. /* CIP */
  258. { 0x530d, 0x12 },
  259. /* CMX */
  260. { 0x5380, 0x01 }, { 0x5381, 0x00 }, { 0x5382, 0x00 }, { 0x5383, 0x17 },
  261. { 0x5384, 0x00 }, { 0x5385, 0x01 }, { 0x5386, 0x00 }, { 0x5387, 0x00 },
  262. { 0x5388, 0x00 }, { 0x5389, 0xe0 }, { 0x538a, 0x00 }, { 0x538b, 0x20 },
  263. { 0x538c, 0x00 }, { 0x538d, 0x00 }, { 0x538e, 0x00 }, { 0x538f, 0x16 },
  264. { 0x5390, 0x00 }, { 0x5391, 0x9c }, { 0x5392, 0x00 }, { 0x5393, 0xa0 },
  265. { 0x5394, 0x18 },
  266. /* 50/60 Detection */
  267. { 0x3c0a, 0x9c }, { 0x3c0b, 0x3f },
  268. /* Output Select */
  269. { OV9740_IO_OUTPUT_SEL01, 0x00 },
  270. { OV9740_IO_OUTPUT_SEL02, 0x00 },
  271. { OV9740_IO_CREL00, 0x00 },
  272. { OV9740_IO_CREL01, 0x00 },
  273. { OV9740_IO_CREL02, 0x00 },
  274. /* AWB Control */
  275. { OV9740_AWB_MANUAL_CTRL, 0x00 },
  276. /* Analog Control */
  277. { OV9740_ANALOG_CTRL03, 0xaa },
  278. { OV9740_ANALOG_CTRL32, 0x2f },
  279. { OV9740_ANALOG_CTRL20, 0x66 },
  280. { OV9740_ANALOG_CTRL21, 0xc0 },
  281. { OV9740_ANALOG_CTRL31, 0x52 },
  282. { OV9740_ANALOG_CTRL33, 0x50 },
  283. { OV9740_ANALOG_CTRL30, 0xca },
  284. { OV9740_ANALOG_CTRL04, 0x0c },
  285. { OV9740_ANALOG_CTRL01, 0x40 },
  286. { OV9740_ANALOG_CTRL02, 0x16 },
  287. { OV9740_ANALOG_CTRL10, 0xa1 },
  288. { OV9740_ANALOG_CTRL12, 0x24 },
  289. { OV9740_ANALOG_CTRL22, 0x9f },
  290. { OV9740_ANALOG_CTRL15, 0xf0 },
  291. /* Sensor Control */
  292. { OV9740_SENSOR_CTRL03, 0x42 },
  293. { OV9740_SENSOR_CTRL04, 0x10 },
  294. { OV9740_SENSOR_CTRL05, 0x45 },
  295. { OV9740_SENSOR_CTRL07, 0x14 },
  296. /* Timing Control */
  297. { OV9740_TIMING_CTRL33, 0x04 },
  298. { OV9740_TIMING_CTRL35, 0x02 },
  299. { OV9740_TIMING_CTRL19, 0x6e },
  300. { OV9740_TIMING_CTRL17, 0x94 },
  301. /* AEC/AGC Control */
  302. { OV9740_AEC_ENABLE, 0x10 },
  303. { OV9740_GAIN_CEILING_01, 0x00 },
  304. { OV9740_GAIN_CEILING_02, 0x7f },
  305. { OV9740_AEC_HI_THRESHOLD, 0xa0 },
  306. { OV9740_AEC_3A1A, 0x05 },
  307. { OV9740_AEC_CTRL1B_WPT2, 0x50 },
  308. { OV9740_AEC_CTRL0F_WPT, 0x50 },
  309. { OV9740_AEC_CTRL10_BPT, 0x4c },
  310. { OV9740_AEC_CTRL1E_BPT2, 0x4c },
  311. { OV9740_AEC_LO_THRESHOLD, 0x26 },
  312. /* BLC Control */
  313. { OV9740_BLC_AUTO_ENABLE, 0x45 },
  314. { OV9740_BLC_MODE, 0x18 },
  315. /* DVP Control */
  316. { OV9740_DVP_VSYNC_CTRL02, 0x04 },
  317. { OV9740_DVP_VSYNC_MODE, 0x00 },
  318. { OV9740_DVP_VSYNC_CTRL06, 0x08 },
  319. /* PLL Setting */
  320. { OV9740_PLL_MODE_CTRL01, 0x20 },
  321. { OV9740_PRE_PLL_CLK_DIV, 0x03 },
  322. { OV9740_PLL_MULTIPLIER, 0x4c },
  323. { OV9740_VT_SYS_CLK_DIV, 0x01 },
  324. { OV9740_VT_PIX_CLK_DIV, 0x08 },
  325. { OV9740_PLL_CTRL3010, 0x01 },
  326. { OV9740_VFIFO_CTRL00, 0x82 },
  327. /* Timing Setting */
  328. /* VTS */
  329. { OV9740_FRM_LENGTH_LN_HI, 0x03 },
  330. { OV9740_FRM_LENGTH_LN_LO, 0x07 },
  331. /* HTS */
  332. { OV9740_LN_LENGTH_PCK_HI, 0x06 },
  333. { OV9740_LN_LENGTH_PCK_LO, 0x62 },
  334. /* MIPI Control */
  335. { OV9740_MIPI_CTRL00, 0x44 }, /* 0x64 for discontinuous clk */
  336. { OV9740_MIPI_3837, 0x01 },
  337. { OV9740_MIPI_CTRL01, 0x0f },
  338. { OV9740_MIPI_CTRL03, 0x05 },
  339. { OV9740_MIPI_CTRL05, 0x10 },
  340. { OV9740_VFIFO_RD_CTRL, 0x16 },
  341. { OV9740_MIPI_CTRL_3012, 0x70 },
  342. { OV9740_SC_CMMM_MIPI_CTR, 0x01 },
  343. /* YUYV order */
  344. { OV9740_ISP_CTRL19, 0x02 },
  345. };
  346. static u32 ov9740_codes[] = {
  347. MEDIA_BUS_FMT_YUYV8_2X8,
  348. };
  349. /* read a register */
  350. static int ov9740_reg_read(struct i2c_client *client, u16 reg, u8 *val)
  351. {
  352. int ret;
  353. struct i2c_msg msg[] = {
  354. {
  355. .addr = client->addr,
  356. .flags = 0,
  357. .len = 2,
  358. .buf = (u8 *)&reg,
  359. },
  360. {
  361. .addr = client->addr,
  362. .flags = I2C_M_RD,
  363. .len = 1,
  364. .buf = val,
  365. },
  366. };
  367. reg = swab16(reg);
  368. ret = i2c_transfer(client->adapter, msg, 2);
  369. if (ret < 0) {
  370. dev_err(&client->dev, "Failed reading register 0x%04x!\n", reg);
  371. return ret;
  372. }
  373. return 0;
  374. }
  375. /* write a register */
  376. static int ov9740_reg_write(struct i2c_client *client, u16 reg, u8 val)
  377. {
  378. struct i2c_msg msg;
  379. struct {
  380. u16 reg;
  381. u8 val;
  382. } __packed buf;
  383. int ret;
  384. reg = swab16(reg);
  385. buf.reg = reg;
  386. buf.val = val;
  387. msg.addr = client->addr;
  388. msg.flags = 0;
  389. msg.len = 3;
  390. msg.buf = (u8 *)&buf;
  391. ret = i2c_transfer(client->adapter, &msg, 1);
  392. if (ret < 0) {
  393. dev_err(&client->dev, "Failed writing register 0x%04x!\n", reg);
  394. return ret;
  395. }
  396. return 0;
  397. }
  398. /* Read a register, alter its bits, write it back */
  399. static int ov9740_reg_rmw(struct i2c_client *client, u16 reg, u8 set, u8 unset)
  400. {
  401. u8 val;
  402. int ret;
  403. ret = ov9740_reg_read(client, reg, &val);
  404. if (ret < 0) {
  405. dev_err(&client->dev,
  406. "[Read]-Modify-Write of register 0x%04x failed!\n",
  407. reg);
  408. return ret;
  409. }
  410. val |= set;
  411. val &= ~unset;
  412. ret = ov9740_reg_write(client, reg, val);
  413. if (ret < 0) {
  414. dev_err(&client->dev,
  415. "Read-Modify-[Write] of register 0x%04x failed!\n",
  416. reg);
  417. return ret;
  418. }
  419. return 0;
  420. }
  421. static int ov9740_reg_write_array(struct i2c_client *client,
  422. const struct ov9740_reg *regarray,
  423. int regarraylen)
  424. {
  425. int i;
  426. int ret;
  427. for (i = 0; i < regarraylen; i++) {
  428. ret = ov9740_reg_write(client,
  429. regarray[i].reg, regarray[i].val);
  430. if (ret < 0)
  431. return ret;
  432. }
  433. return 0;
  434. }
  435. /* Start/Stop streaming from the device */
  436. static int ov9740_s_stream(struct v4l2_subdev *sd, int enable)
  437. {
  438. struct i2c_client *client = v4l2_get_subdevdata(sd);
  439. struct ov9740_priv *priv = to_ov9740(sd);
  440. int ret;
  441. /* Program orientation register. */
  442. if (priv->flag_vflip)
  443. ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0x2, 0);
  444. else
  445. ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0, 0x2);
  446. if (ret < 0)
  447. return ret;
  448. if (priv->flag_hflip)
  449. ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0x1, 0);
  450. else
  451. ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0, 0x1);
  452. if (ret < 0)
  453. return ret;
  454. if (enable) {
  455. dev_dbg(&client->dev, "Enabling Streaming\n");
  456. /* Start Streaming */
  457. ret = ov9740_reg_write(client, OV9740_MODE_SELECT, 0x01);
  458. } else {
  459. dev_dbg(&client->dev, "Disabling Streaming\n");
  460. /* Software Reset */
  461. ret = ov9740_reg_write(client, OV9740_SOFTWARE_RESET, 0x01);
  462. if (!ret)
  463. /* Setting Streaming to Standby */
  464. ret = ov9740_reg_write(client, OV9740_MODE_SELECT,
  465. 0x00);
  466. }
  467. priv->current_enable = enable;
  468. return ret;
  469. }
  470. /* select nearest higher resolution for capture */
  471. static void ov9740_res_roundup(u32 *width, u32 *height)
  472. {
  473. /* Width must be a multiple of 4 pixels. */
  474. *width = ALIGN(*width, 4);
  475. /* Max resolution is 1280x720 (720p). */
  476. if (*width > OV9740_MAX_WIDTH)
  477. *width = OV9740_MAX_WIDTH;
  478. if (*height > OV9740_MAX_HEIGHT)
  479. *height = OV9740_MAX_HEIGHT;
  480. }
  481. /* Setup registers according to resolution and color encoding */
  482. static int ov9740_set_res(struct i2c_client *client, u32 width, u32 height)
  483. {
  484. u32 x_start;
  485. u32 y_start;
  486. u32 x_end;
  487. u32 y_end;
  488. bool scaling = false;
  489. u32 scale_input_x;
  490. u32 scale_input_y;
  491. int ret;
  492. if ((width != OV9740_MAX_WIDTH) || (height != OV9740_MAX_HEIGHT))
  493. scaling = true;
  494. /*
  495. * Try to use as much of the sensor area as possible when supporting
  496. * smaller resolutions. Depending on the aspect ratio of the
  497. * chosen resolution, we can either use the full width of the sensor,
  498. * or the full height of the sensor (or both if the aspect ratio is
  499. * the same as 1280x720.
  500. */
  501. if ((OV9740_MAX_WIDTH * height) > (OV9740_MAX_HEIGHT * width)) {
  502. scale_input_x = (OV9740_MAX_HEIGHT * width) / height;
  503. scale_input_y = OV9740_MAX_HEIGHT;
  504. } else {
  505. scale_input_x = OV9740_MAX_WIDTH;
  506. scale_input_y = (OV9740_MAX_WIDTH * height) / width;
  507. }
  508. /* These describe the area of the sensor to use. */
  509. x_start = (OV9740_MAX_WIDTH - scale_input_x) / 2;
  510. y_start = (OV9740_MAX_HEIGHT - scale_input_y) / 2;
  511. x_end = x_start + scale_input_x - 1;
  512. y_end = y_start + scale_input_y - 1;
  513. ret = ov9740_reg_write(client, OV9740_X_ADDR_START_HI, x_start >> 8);
  514. if (ret)
  515. goto done;
  516. ret = ov9740_reg_write(client, OV9740_X_ADDR_START_LO, x_start & 0xff);
  517. if (ret)
  518. goto done;
  519. ret = ov9740_reg_write(client, OV9740_Y_ADDR_START_HI, y_start >> 8);
  520. if (ret)
  521. goto done;
  522. ret = ov9740_reg_write(client, OV9740_Y_ADDR_START_LO, y_start & 0xff);
  523. if (ret)
  524. goto done;
  525. ret = ov9740_reg_write(client, OV9740_X_ADDR_END_HI, x_end >> 8);
  526. if (ret)
  527. goto done;
  528. ret = ov9740_reg_write(client, OV9740_X_ADDR_END_LO, x_end & 0xff);
  529. if (ret)
  530. goto done;
  531. ret = ov9740_reg_write(client, OV9740_Y_ADDR_END_HI, y_end >> 8);
  532. if (ret)
  533. goto done;
  534. ret = ov9740_reg_write(client, OV9740_Y_ADDR_END_LO, y_end & 0xff);
  535. if (ret)
  536. goto done;
  537. ret = ov9740_reg_write(client, OV9740_X_OUTPUT_SIZE_HI, width >> 8);
  538. if (ret)
  539. goto done;
  540. ret = ov9740_reg_write(client, OV9740_X_OUTPUT_SIZE_LO, width & 0xff);
  541. if (ret)
  542. goto done;
  543. ret = ov9740_reg_write(client, OV9740_Y_OUTPUT_SIZE_HI, height >> 8);
  544. if (ret)
  545. goto done;
  546. ret = ov9740_reg_write(client, OV9740_Y_OUTPUT_SIZE_LO, height & 0xff);
  547. if (ret)
  548. goto done;
  549. ret = ov9740_reg_write(client, OV9740_ISP_CTRL1E, scale_input_x >> 8);
  550. if (ret)
  551. goto done;
  552. ret = ov9740_reg_write(client, OV9740_ISP_CTRL1F, scale_input_x & 0xff);
  553. if (ret)
  554. goto done;
  555. ret = ov9740_reg_write(client, OV9740_ISP_CTRL20, scale_input_y >> 8);
  556. if (ret)
  557. goto done;
  558. ret = ov9740_reg_write(client, OV9740_ISP_CTRL21, scale_input_y & 0xff);
  559. if (ret)
  560. goto done;
  561. ret = ov9740_reg_write(client, OV9740_VFIFO_READ_START_HI,
  562. (scale_input_x - width) >> 8);
  563. if (ret)
  564. goto done;
  565. ret = ov9740_reg_write(client, OV9740_VFIFO_READ_START_LO,
  566. (scale_input_x - width) & 0xff);
  567. if (ret)
  568. goto done;
  569. ret = ov9740_reg_write(client, OV9740_ISP_CTRL00, 0xff);
  570. if (ret)
  571. goto done;
  572. ret = ov9740_reg_write(client, OV9740_ISP_CTRL01, 0xef |
  573. (scaling << 4));
  574. if (ret)
  575. goto done;
  576. ret = ov9740_reg_write(client, OV9740_ISP_CTRL03, 0xff);
  577. done:
  578. return ret;
  579. }
  580. /* set the format we will capture in */
  581. static int ov9740_s_fmt(struct v4l2_subdev *sd,
  582. struct v4l2_mbus_framefmt *mf)
  583. {
  584. struct i2c_client *client = v4l2_get_subdevdata(sd);
  585. struct ov9740_priv *priv = to_ov9740(sd);
  586. enum v4l2_colorspace cspace;
  587. u32 code = mf->code;
  588. int ret;
  589. ov9740_res_roundup(&mf->width, &mf->height);
  590. switch (code) {
  591. case MEDIA_BUS_FMT_YUYV8_2X8:
  592. cspace = V4L2_COLORSPACE_SRGB;
  593. break;
  594. default:
  595. return -EINVAL;
  596. }
  597. ret = ov9740_reg_write_array(client, ov9740_defaults,
  598. ARRAY_SIZE(ov9740_defaults));
  599. if (ret < 0)
  600. return ret;
  601. ret = ov9740_set_res(client, mf->width, mf->height);
  602. if (ret < 0)
  603. return ret;
  604. mf->code = code;
  605. mf->colorspace = cspace;
  606. memcpy(&priv->current_mf, mf, sizeof(struct v4l2_mbus_framefmt));
  607. return ret;
  608. }
  609. static int ov9740_set_fmt(struct v4l2_subdev *sd,
  610. struct v4l2_subdev_pad_config *cfg,
  611. struct v4l2_subdev_format *format)
  612. {
  613. struct v4l2_mbus_framefmt *mf = &format->format;
  614. if (format->pad)
  615. return -EINVAL;
  616. ov9740_res_roundup(&mf->width, &mf->height);
  617. mf->field = V4L2_FIELD_NONE;
  618. mf->code = MEDIA_BUS_FMT_YUYV8_2X8;
  619. mf->colorspace = V4L2_COLORSPACE_SRGB;
  620. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
  621. return ov9740_s_fmt(sd, mf);
  622. cfg->try_fmt = *mf;
  623. return 0;
  624. }
  625. static int ov9740_enum_mbus_code(struct v4l2_subdev *sd,
  626. struct v4l2_subdev_pad_config *cfg,
  627. struct v4l2_subdev_mbus_code_enum *code)
  628. {
  629. if (code->pad || code->index >= ARRAY_SIZE(ov9740_codes))
  630. return -EINVAL;
  631. code->code = ov9740_codes[code->index];
  632. return 0;
  633. }
  634. static int ov9740_get_selection(struct v4l2_subdev *sd,
  635. struct v4l2_subdev_pad_config *cfg,
  636. struct v4l2_subdev_selection *sel)
  637. {
  638. if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
  639. return -EINVAL;
  640. switch (sel->target) {
  641. case V4L2_SEL_TGT_CROP_BOUNDS:
  642. case V4L2_SEL_TGT_CROP_DEFAULT:
  643. case V4L2_SEL_TGT_CROP:
  644. sel->r.left = 0;
  645. sel->r.top = 0;
  646. sel->r.width = OV9740_MAX_WIDTH;
  647. sel->r.height = OV9740_MAX_HEIGHT;
  648. return 0;
  649. default:
  650. return -EINVAL;
  651. }
  652. }
  653. /* Set status of additional camera capabilities */
  654. static int ov9740_s_ctrl(struct v4l2_ctrl *ctrl)
  655. {
  656. struct ov9740_priv *priv =
  657. container_of(ctrl->handler, struct ov9740_priv, hdl);
  658. switch (ctrl->id) {
  659. case V4L2_CID_VFLIP:
  660. priv->flag_vflip = ctrl->val;
  661. break;
  662. case V4L2_CID_HFLIP:
  663. priv->flag_hflip = ctrl->val;
  664. break;
  665. default:
  666. return -EINVAL;
  667. }
  668. return 0;
  669. }
  670. static int ov9740_s_power(struct v4l2_subdev *sd, int on)
  671. {
  672. struct i2c_client *client = v4l2_get_subdevdata(sd);
  673. struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
  674. struct ov9740_priv *priv = to_ov9740(sd);
  675. int ret;
  676. if (on) {
  677. ret = soc_camera_power_on(&client->dev, ssdd, priv->clk);
  678. if (ret < 0)
  679. return ret;
  680. if (priv->current_enable) {
  681. ov9740_s_fmt(sd, &priv->current_mf);
  682. ov9740_s_stream(sd, 1);
  683. }
  684. } else {
  685. if (priv->current_enable) {
  686. ov9740_s_stream(sd, 0);
  687. priv->current_enable = true;
  688. }
  689. soc_camera_power_off(&client->dev, ssdd, priv->clk);
  690. }
  691. return 0;
  692. }
  693. #ifdef CONFIG_VIDEO_ADV_DEBUG
  694. static int ov9740_get_register(struct v4l2_subdev *sd,
  695. struct v4l2_dbg_register *reg)
  696. {
  697. struct i2c_client *client = v4l2_get_subdevdata(sd);
  698. int ret;
  699. u8 val;
  700. if (reg->reg & ~0xffff)
  701. return -EINVAL;
  702. reg->size = 2;
  703. ret = ov9740_reg_read(client, reg->reg, &val);
  704. if (ret)
  705. return ret;
  706. reg->val = (__u64)val;
  707. return ret;
  708. }
  709. static int ov9740_set_register(struct v4l2_subdev *sd,
  710. const struct v4l2_dbg_register *reg)
  711. {
  712. struct i2c_client *client = v4l2_get_subdevdata(sd);
  713. if (reg->reg & ~0xffff || reg->val & ~0xff)
  714. return -EINVAL;
  715. return ov9740_reg_write(client, reg->reg, reg->val);
  716. }
  717. #endif
  718. static int ov9740_video_probe(struct i2c_client *client)
  719. {
  720. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  721. struct ov9740_priv *priv = to_ov9740(sd);
  722. u8 modelhi, modello;
  723. int ret;
  724. ret = ov9740_s_power(&priv->subdev, 1);
  725. if (ret < 0)
  726. return ret;
  727. /*
  728. * check and show product ID and manufacturer ID
  729. */
  730. ret = ov9740_reg_read(client, OV9740_MODEL_ID_HI, &modelhi);
  731. if (ret < 0)
  732. goto done;
  733. ret = ov9740_reg_read(client, OV9740_MODEL_ID_LO, &modello);
  734. if (ret < 0)
  735. goto done;
  736. priv->model = (modelhi << 8) | modello;
  737. ret = ov9740_reg_read(client, OV9740_REVISION_NUMBER, &priv->revision);
  738. if (ret < 0)
  739. goto done;
  740. ret = ov9740_reg_read(client, OV9740_MANUFACTURER_ID, &priv->manid);
  741. if (ret < 0)
  742. goto done;
  743. ret = ov9740_reg_read(client, OV9740_SMIA_VERSION, &priv->smiaver);
  744. if (ret < 0)
  745. goto done;
  746. if (priv->model != 0x9740) {
  747. ret = -ENODEV;
  748. goto done;
  749. }
  750. dev_info(&client->dev, "ov9740 Model ID 0x%04x, Revision 0x%02x, "
  751. "Manufacturer 0x%02x, SMIA Version 0x%02x\n",
  752. priv->model, priv->revision, priv->manid, priv->smiaver);
  753. ret = v4l2_ctrl_handler_setup(&priv->hdl);
  754. done:
  755. ov9740_s_power(&priv->subdev, 0);
  756. return ret;
  757. }
  758. /* Request bus settings on camera side */
  759. static int ov9740_g_mbus_config(struct v4l2_subdev *sd,
  760. struct v4l2_mbus_config *cfg)
  761. {
  762. struct i2c_client *client = v4l2_get_subdevdata(sd);
  763. struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
  764. cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
  765. V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
  766. V4L2_MBUS_DATA_ACTIVE_HIGH;
  767. cfg->type = V4L2_MBUS_PARALLEL;
  768. cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
  769. return 0;
  770. }
  771. static struct v4l2_subdev_video_ops ov9740_video_ops = {
  772. .s_stream = ov9740_s_stream,
  773. .g_mbus_config = ov9740_g_mbus_config,
  774. };
  775. static struct v4l2_subdev_core_ops ov9740_core_ops = {
  776. .s_power = ov9740_s_power,
  777. #ifdef CONFIG_VIDEO_ADV_DEBUG
  778. .g_register = ov9740_get_register,
  779. .s_register = ov9740_set_register,
  780. #endif
  781. };
  782. static const struct v4l2_subdev_pad_ops ov9740_pad_ops = {
  783. .enum_mbus_code = ov9740_enum_mbus_code,
  784. .get_selection = ov9740_get_selection,
  785. .set_fmt = ov9740_set_fmt,
  786. };
  787. static struct v4l2_subdev_ops ov9740_subdev_ops = {
  788. .core = &ov9740_core_ops,
  789. .video = &ov9740_video_ops,
  790. .pad = &ov9740_pad_ops,
  791. };
  792. static const struct v4l2_ctrl_ops ov9740_ctrl_ops = {
  793. .s_ctrl = ov9740_s_ctrl,
  794. };
  795. /*
  796. * i2c_driver function
  797. */
  798. static int ov9740_probe(struct i2c_client *client,
  799. const struct i2c_device_id *did)
  800. {
  801. struct ov9740_priv *priv;
  802. struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
  803. int ret;
  804. if (!ssdd) {
  805. dev_err(&client->dev, "Missing platform_data for driver\n");
  806. return -EINVAL;
  807. }
  808. priv = devm_kzalloc(&client->dev, sizeof(struct ov9740_priv), GFP_KERNEL);
  809. if (!priv) {
  810. dev_err(&client->dev, "Failed to allocate private data!\n");
  811. return -ENOMEM;
  812. }
  813. v4l2_i2c_subdev_init(&priv->subdev, client, &ov9740_subdev_ops);
  814. v4l2_ctrl_handler_init(&priv->hdl, 13);
  815. v4l2_ctrl_new_std(&priv->hdl, &ov9740_ctrl_ops,
  816. V4L2_CID_VFLIP, 0, 1, 1, 0);
  817. v4l2_ctrl_new_std(&priv->hdl, &ov9740_ctrl_ops,
  818. V4L2_CID_HFLIP, 0, 1, 1, 0);
  819. priv->subdev.ctrl_handler = &priv->hdl;
  820. if (priv->hdl.error)
  821. return priv->hdl.error;
  822. priv->clk = v4l2_clk_get(&client->dev, "mclk");
  823. if (IS_ERR(priv->clk)) {
  824. ret = PTR_ERR(priv->clk);
  825. goto eclkget;
  826. }
  827. ret = ov9740_video_probe(client);
  828. if (ret < 0) {
  829. v4l2_clk_put(priv->clk);
  830. eclkget:
  831. v4l2_ctrl_handler_free(&priv->hdl);
  832. }
  833. return ret;
  834. }
  835. static int ov9740_remove(struct i2c_client *client)
  836. {
  837. struct ov9740_priv *priv = i2c_get_clientdata(client);
  838. v4l2_clk_put(priv->clk);
  839. v4l2_device_unregister_subdev(&priv->subdev);
  840. v4l2_ctrl_handler_free(&priv->hdl);
  841. return 0;
  842. }
  843. static const struct i2c_device_id ov9740_id[] = {
  844. { "ov9740", 0 },
  845. { }
  846. };
  847. MODULE_DEVICE_TABLE(i2c, ov9740_id);
  848. static struct i2c_driver ov9740_i2c_driver = {
  849. .driver = {
  850. .name = "ov9740",
  851. },
  852. .probe = ov9740_probe,
  853. .remove = ov9740_remove,
  854. .id_table = ov9740_id,
  855. };
  856. module_i2c_driver(ov9740_i2c_driver);
  857. MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV9740");
  858. MODULE_AUTHOR("Andrew Chew <[email protected]>");
  859. MODULE_LICENSE("GPL v2");