cx23885-cards.c 67 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/module.h>
  19. #include <linux/pci.h>
  20. #include <linux/delay.h>
  21. #include <media/drv-intf/cx25840.h>
  22. #include <linux/firmware.h>
  23. #include <misc/altera.h>
  24. #include "cx23885.h"
  25. #include "tuner-xc2028.h"
  26. #include "netup-eeprom.h"
  27. #include "netup-init.h"
  28. #include "altera-ci.h"
  29. #include "xc4000.h"
  30. #include "xc5000.h"
  31. #include "cx23888-ir.h"
  32. static unsigned int netup_card_rev = 4;
  33. module_param(netup_card_rev, int, 0644);
  34. MODULE_PARM_DESC(netup_card_rev,
  35. "NetUP Dual DVB-T/C CI card revision");
  36. static unsigned int enable_885_ir;
  37. module_param(enable_885_ir, int, 0644);
  38. MODULE_PARM_DESC(enable_885_ir,
  39. "Enable integrated IR controller for supported\n"
  40. "\t\t CX2388[57] boards that are wired for it:\n"
  41. "\t\t\tHVR-1250 (reported safe)\n"
  42. "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
  43. "\t\t\tTeVii S470 (reported unsafe)\n"
  44. "\t\t This can cause an interrupt storm with some cards.\n"
  45. "\t\t Default: 0 [Disabled]");
  46. /* ------------------------------------------------------------------ */
  47. /* board config info */
  48. struct cx23885_board cx23885_boards[] = {
  49. [CX23885_BOARD_UNKNOWN] = {
  50. .name = "UNKNOWN/GENERIC",
  51. /* Ensure safe default for unknown boards */
  52. .clk_freq = 0,
  53. .input = {{
  54. .type = CX23885_VMUX_COMPOSITE1,
  55. .vmux = 0,
  56. }, {
  57. .type = CX23885_VMUX_COMPOSITE2,
  58. .vmux = 1,
  59. }, {
  60. .type = CX23885_VMUX_COMPOSITE3,
  61. .vmux = 2,
  62. }, {
  63. .type = CX23885_VMUX_COMPOSITE4,
  64. .vmux = 3,
  65. } },
  66. },
  67. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  68. .name = "Hauppauge WinTV-HVR1800lp",
  69. .portc = CX23885_MPEG_DVB,
  70. .input = {{
  71. .type = CX23885_VMUX_TELEVISION,
  72. .vmux = 0,
  73. .gpio0 = 0xff00,
  74. }, {
  75. .type = CX23885_VMUX_DEBUG,
  76. .vmux = 0,
  77. .gpio0 = 0xff01,
  78. }, {
  79. .type = CX23885_VMUX_COMPOSITE1,
  80. .vmux = 1,
  81. .gpio0 = 0xff02,
  82. }, {
  83. .type = CX23885_VMUX_SVIDEO,
  84. .vmux = 2,
  85. .gpio0 = 0xff02,
  86. } },
  87. },
  88. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  89. .name = "Hauppauge WinTV-HVR1800",
  90. .porta = CX23885_ANALOG_VIDEO,
  91. .portb = CX23885_MPEG_ENCODER,
  92. .portc = CX23885_MPEG_DVB,
  93. .tuner_type = TUNER_PHILIPS_TDA8290,
  94. .tuner_addr = 0x42, /* 0x84 >> 1 */
  95. .tuner_bus = 1,
  96. .input = {{
  97. .type = CX23885_VMUX_TELEVISION,
  98. .vmux = CX25840_VIN7_CH3 |
  99. CX25840_VIN5_CH2 |
  100. CX25840_VIN2_CH1,
  101. .amux = CX25840_AUDIO8,
  102. .gpio0 = 0,
  103. }, {
  104. .type = CX23885_VMUX_COMPOSITE1,
  105. .vmux = CX25840_VIN7_CH3 |
  106. CX25840_VIN4_CH2 |
  107. CX25840_VIN6_CH1,
  108. .amux = CX25840_AUDIO7,
  109. .gpio0 = 0,
  110. }, {
  111. .type = CX23885_VMUX_SVIDEO,
  112. .vmux = CX25840_VIN7_CH3 |
  113. CX25840_VIN4_CH2 |
  114. CX25840_VIN8_CH1 |
  115. CX25840_SVIDEO_ON,
  116. .amux = CX25840_AUDIO7,
  117. .gpio0 = 0,
  118. } },
  119. },
  120. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  121. .name = "Hauppauge WinTV-HVR1250",
  122. .porta = CX23885_ANALOG_VIDEO,
  123. .portc = CX23885_MPEG_DVB,
  124. #ifdef MT2131_NO_ANALOG_SUPPORT_YET
  125. .tuner_type = TUNER_PHILIPS_TDA8290,
  126. .tuner_addr = 0x42, /* 0x84 >> 1 */
  127. .tuner_bus = 1,
  128. #endif
  129. .force_bff = 1,
  130. .input = {{
  131. #ifdef MT2131_NO_ANALOG_SUPPORT_YET
  132. .type = CX23885_VMUX_TELEVISION,
  133. .vmux = CX25840_VIN7_CH3 |
  134. CX25840_VIN5_CH2 |
  135. CX25840_VIN2_CH1,
  136. .amux = CX25840_AUDIO8,
  137. .gpio0 = 0xff00,
  138. }, {
  139. #endif
  140. .type = CX23885_VMUX_COMPOSITE1,
  141. .vmux = CX25840_VIN7_CH3 |
  142. CX25840_VIN4_CH2 |
  143. CX25840_VIN6_CH1,
  144. .amux = CX25840_AUDIO7,
  145. .gpio0 = 0xff02,
  146. }, {
  147. .type = CX23885_VMUX_SVIDEO,
  148. .vmux = CX25840_VIN7_CH3 |
  149. CX25840_VIN4_CH2 |
  150. CX25840_VIN8_CH1 |
  151. CX25840_SVIDEO_ON,
  152. .amux = CX25840_AUDIO7,
  153. .gpio0 = 0xff02,
  154. } },
  155. },
  156. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  157. .name = "DViCO FusionHDTV5 Express",
  158. .portb = CX23885_MPEG_DVB,
  159. },
  160. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  161. .name = "Hauppauge WinTV-HVR1500Q",
  162. .portc = CX23885_MPEG_DVB,
  163. },
  164. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  165. .name = "Hauppauge WinTV-HVR1500",
  166. .porta = CX23885_ANALOG_VIDEO,
  167. .portc = CX23885_MPEG_DVB,
  168. .tuner_type = TUNER_XC2028,
  169. .tuner_addr = 0x61, /* 0xc2 >> 1 */
  170. .input = {{
  171. .type = CX23885_VMUX_TELEVISION,
  172. .vmux = CX25840_VIN7_CH3 |
  173. CX25840_VIN5_CH2 |
  174. CX25840_VIN2_CH1,
  175. .gpio0 = 0,
  176. }, {
  177. .type = CX23885_VMUX_COMPOSITE1,
  178. .vmux = CX25840_VIN7_CH3 |
  179. CX25840_VIN4_CH2 |
  180. CX25840_VIN6_CH1,
  181. .gpio0 = 0,
  182. }, {
  183. .type = CX23885_VMUX_SVIDEO,
  184. .vmux = CX25840_VIN7_CH3 |
  185. CX25840_VIN4_CH2 |
  186. CX25840_VIN8_CH1 |
  187. CX25840_SVIDEO_ON,
  188. .gpio0 = 0,
  189. } },
  190. },
  191. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  192. .name = "Hauppauge WinTV-HVR1200",
  193. .portc = CX23885_MPEG_DVB,
  194. },
  195. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  196. .name = "Hauppauge WinTV-HVR1700",
  197. .portc = CX23885_MPEG_DVB,
  198. },
  199. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  200. .name = "Hauppauge WinTV-HVR1400",
  201. .portc = CX23885_MPEG_DVB,
  202. },
  203. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  204. .name = "DViCO FusionHDTV7 Dual Express",
  205. .portb = CX23885_MPEG_DVB,
  206. .portc = CX23885_MPEG_DVB,
  207. },
  208. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  209. .name = "DViCO FusionHDTV DVB-T Dual Express",
  210. .portb = CX23885_MPEG_DVB,
  211. .portc = CX23885_MPEG_DVB,
  212. },
  213. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  214. .name = "Leadtek Winfast PxDVR3200 H",
  215. .portc = CX23885_MPEG_DVB,
  216. },
  217. [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = {
  218. .name = "Leadtek Winfast PxPVR2200",
  219. .porta = CX23885_ANALOG_VIDEO,
  220. .tuner_type = TUNER_XC2028,
  221. .tuner_addr = 0x61,
  222. .tuner_bus = 1,
  223. .input = {{
  224. .type = CX23885_VMUX_TELEVISION,
  225. .vmux = CX25840_VIN2_CH1 |
  226. CX25840_VIN5_CH2,
  227. .amux = CX25840_AUDIO8,
  228. .gpio0 = 0x704040,
  229. }, {
  230. .type = CX23885_VMUX_COMPOSITE1,
  231. .vmux = CX25840_COMPOSITE1,
  232. .amux = CX25840_AUDIO7,
  233. .gpio0 = 0x704040,
  234. }, {
  235. .type = CX23885_VMUX_SVIDEO,
  236. .vmux = CX25840_SVIDEO_LUMA3 |
  237. CX25840_SVIDEO_CHROMA4,
  238. .amux = CX25840_AUDIO7,
  239. .gpio0 = 0x704040,
  240. }, {
  241. .type = CX23885_VMUX_COMPONENT,
  242. .vmux = CX25840_VIN7_CH1 |
  243. CX25840_VIN6_CH2 |
  244. CX25840_VIN8_CH3 |
  245. CX25840_COMPONENT_ON,
  246. .amux = CX25840_AUDIO7,
  247. .gpio0 = 0x704040,
  248. } },
  249. },
  250. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
  251. .name = "Leadtek Winfast PxDVR3200 H XC4000",
  252. .porta = CX23885_ANALOG_VIDEO,
  253. .portc = CX23885_MPEG_DVB,
  254. .tuner_type = TUNER_XC4000,
  255. .tuner_addr = 0x61,
  256. .radio_type = UNSET,
  257. .radio_addr = ADDR_UNSET,
  258. .input = {{
  259. .type = CX23885_VMUX_TELEVISION,
  260. .vmux = CX25840_VIN2_CH1 |
  261. CX25840_VIN5_CH2 |
  262. CX25840_NONE0_CH3,
  263. }, {
  264. .type = CX23885_VMUX_COMPOSITE1,
  265. .vmux = CX25840_COMPOSITE1,
  266. }, {
  267. .type = CX23885_VMUX_SVIDEO,
  268. .vmux = CX25840_SVIDEO_LUMA3 |
  269. CX25840_SVIDEO_CHROMA4,
  270. }, {
  271. .type = CX23885_VMUX_COMPONENT,
  272. .vmux = CX25840_VIN7_CH1 |
  273. CX25840_VIN6_CH2 |
  274. CX25840_VIN8_CH3 |
  275. CX25840_COMPONENT_ON,
  276. } },
  277. },
  278. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  279. .name = "Compro VideoMate E650F",
  280. .portc = CX23885_MPEG_DVB,
  281. },
  282. [CX23885_BOARD_TBS_6920] = {
  283. .name = "TurboSight TBS 6920",
  284. .portb = CX23885_MPEG_DVB,
  285. },
  286. [CX23885_BOARD_TBS_6980] = {
  287. .name = "TurboSight TBS 6980",
  288. .portb = CX23885_MPEG_DVB,
  289. .portc = CX23885_MPEG_DVB,
  290. },
  291. [CX23885_BOARD_TBS_6981] = {
  292. .name = "TurboSight TBS 6981",
  293. .portb = CX23885_MPEG_DVB,
  294. .portc = CX23885_MPEG_DVB,
  295. },
  296. [CX23885_BOARD_TEVII_S470] = {
  297. .name = "TeVii S470",
  298. .portb = CX23885_MPEG_DVB,
  299. },
  300. [CX23885_BOARD_DVBWORLD_2005] = {
  301. .name = "DVBWorld DVB-S2 2005",
  302. .portb = CX23885_MPEG_DVB,
  303. },
  304. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  305. .ci_type = 1,
  306. .name = "NetUP Dual DVB-S2 CI",
  307. .portb = CX23885_MPEG_DVB,
  308. .portc = CX23885_MPEG_DVB,
  309. },
  310. [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
  311. .name = "Hauppauge WinTV-HVR1270",
  312. .portc = CX23885_MPEG_DVB,
  313. },
  314. [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
  315. .name = "Hauppauge WinTV-HVR1275",
  316. .portc = CX23885_MPEG_DVB,
  317. },
  318. [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
  319. .name = "Hauppauge WinTV-HVR1255",
  320. .porta = CX23885_ANALOG_VIDEO,
  321. .portc = CX23885_MPEG_DVB,
  322. .tuner_type = TUNER_ABSENT,
  323. .tuner_addr = 0x42, /* 0x84 >> 1 */
  324. .force_bff = 1,
  325. .input = {{
  326. .type = CX23885_VMUX_TELEVISION,
  327. .vmux = CX25840_VIN7_CH3 |
  328. CX25840_VIN5_CH2 |
  329. CX25840_VIN2_CH1 |
  330. CX25840_DIF_ON,
  331. .amux = CX25840_AUDIO8,
  332. }, {
  333. .type = CX23885_VMUX_COMPOSITE1,
  334. .vmux = CX25840_VIN7_CH3 |
  335. CX25840_VIN4_CH2 |
  336. CX25840_VIN6_CH1,
  337. .amux = CX25840_AUDIO7,
  338. }, {
  339. .type = CX23885_VMUX_SVIDEO,
  340. .vmux = CX25840_VIN7_CH3 |
  341. CX25840_VIN4_CH2 |
  342. CX25840_VIN8_CH1 |
  343. CX25840_SVIDEO_ON,
  344. .amux = CX25840_AUDIO7,
  345. } },
  346. },
  347. [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
  348. .name = "Hauppauge WinTV-HVR1255",
  349. .porta = CX23885_ANALOG_VIDEO,
  350. .portc = CX23885_MPEG_DVB,
  351. .tuner_type = TUNER_ABSENT,
  352. .tuner_addr = 0x42, /* 0x84 >> 1 */
  353. .force_bff = 1,
  354. .input = {{
  355. .type = CX23885_VMUX_TELEVISION,
  356. .vmux = CX25840_VIN7_CH3 |
  357. CX25840_VIN5_CH2 |
  358. CX25840_VIN2_CH1 |
  359. CX25840_DIF_ON,
  360. .amux = CX25840_AUDIO8,
  361. }, {
  362. .type = CX23885_VMUX_SVIDEO,
  363. .vmux = CX25840_VIN7_CH3 |
  364. CX25840_VIN4_CH2 |
  365. CX25840_VIN8_CH1 |
  366. CX25840_SVIDEO_ON,
  367. .amux = CX25840_AUDIO7,
  368. } },
  369. },
  370. [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
  371. .name = "Hauppauge WinTV-HVR1210",
  372. .portc = CX23885_MPEG_DVB,
  373. },
  374. [CX23885_BOARD_MYGICA_X8506] = {
  375. .name = "Mygica X8506 DMB-TH",
  376. .tuner_type = TUNER_XC5000,
  377. .tuner_addr = 0x61,
  378. .tuner_bus = 1,
  379. .porta = CX23885_ANALOG_VIDEO,
  380. .portb = CX23885_MPEG_DVB,
  381. .input = {
  382. {
  383. .type = CX23885_VMUX_TELEVISION,
  384. .vmux = CX25840_COMPOSITE2,
  385. },
  386. {
  387. .type = CX23885_VMUX_COMPOSITE1,
  388. .vmux = CX25840_COMPOSITE8,
  389. },
  390. {
  391. .type = CX23885_VMUX_SVIDEO,
  392. .vmux = CX25840_SVIDEO_LUMA3 |
  393. CX25840_SVIDEO_CHROMA4,
  394. },
  395. {
  396. .type = CX23885_VMUX_COMPONENT,
  397. .vmux = CX25840_COMPONENT_ON |
  398. CX25840_VIN1_CH1 |
  399. CX25840_VIN6_CH2 |
  400. CX25840_VIN7_CH3,
  401. },
  402. },
  403. },
  404. [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
  405. .name = "Magic-Pro ProHDTV Extreme 2",
  406. .tuner_type = TUNER_XC5000,
  407. .tuner_addr = 0x61,
  408. .tuner_bus = 1,
  409. .porta = CX23885_ANALOG_VIDEO,
  410. .portb = CX23885_MPEG_DVB,
  411. .input = {
  412. {
  413. .type = CX23885_VMUX_TELEVISION,
  414. .vmux = CX25840_COMPOSITE2,
  415. },
  416. {
  417. .type = CX23885_VMUX_COMPOSITE1,
  418. .vmux = CX25840_COMPOSITE8,
  419. },
  420. {
  421. .type = CX23885_VMUX_SVIDEO,
  422. .vmux = CX25840_SVIDEO_LUMA3 |
  423. CX25840_SVIDEO_CHROMA4,
  424. },
  425. {
  426. .type = CX23885_VMUX_COMPONENT,
  427. .vmux = CX25840_COMPONENT_ON |
  428. CX25840_VIN1_CH1 |
  429. CX25840_VIN6_CH2 |
  430. CX25840_VIN7_CH3,
  431. },
  432. },
  433. },
  434. [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
  435. .name = "Hauppauge WinTV-HVR1850",
  436. .porta = CX23885_ANALOG_VIDEO,
  437. .portb = CX23885_MPEG_ENCODER,
  438. .portc = CX23885_MPEG_DVB,
  439. .tuner_type = TUNER_ABSENT,
  440. .tuner_addr = 0x42, /* 0x84 >> 1 */
  441. .force_bff = 1,
  442. .input = {{
  443. .type = CX23885_VMUX_TELEVISION,
  444. .vmux = CX25840_VIN7_CH3 |
  445. CX25840_VIN5_CH2 |
  446. CX25840_VIN2_CH1 |
  447. CX25840_DIF_ON,
  448. .amux = CX25840_AUDIO8,
  449. }, {
  450. .type = CX23885_VMUX_COMPOSITE1,
  451. .vmux = CX25840_VIN7_CH3 |
  452. CX25840_VIN4_CH2 |
  453. CX25840_VIN6_CH1,
  454. .amux = CX25840_AUDIO7,
  455. }, {
  456. .type = CX23885_VMUX_SVIDEO,
  457. .vmux = CX25840_VIN7_CH3 |
  458. CX25840_VIN4_CH2 |
  459. CX25840_VIN8_CH1 |
  460. CX25840_SVIDEO_ON,
  461. .amux = CX25840_AUDIO7,
  462. } },
  463. },
  464. [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
  465. .name = "Compro VideoMate E800",
  466. .portc = CX23885_MPEG_DVB,
  467. },
  468. [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
  469. .name = "Hauppauge WinTV-HVR1290",
  470. .portc = CX23885_MPEG_DVB,
  471. },
  472. [CX23885_BOARD_MYGICA_X8558PRO] = {
  473. .name = "Mygica X8558 PRO DMB-TH",
  474. .portb = CX23885_MPEG_DVB,
  475. .portc = CX23885_MPEG_DVB,
  476. },
  477. [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
  478. .name = "LEADTEK WinFast PxTV1200",
  479. .porta = CX23885_ANALOG_VIDEO,
  480. .tuner_type = TUNER_XC2028,
  481. .tuner_addr = 0x61,
  482. .tuner_bus = 1,
  483. .input = {{
  484. .type = CX23885_VMUX_TELEVISION,
  485. .vmux = CX25840_VIN2_CH1 |
  486. CX25840_VIN5_CH2 |
  487. CX25840_NONE0_CH3,
  488. }, {
  489. .type = CX23885_VMUX_COMPOSITE1,
  490. .vmux = CX25840_COMPOSITE1,
  491. }, {
  492. .type = CX23885_VMUX_SVIDEO,
  493. .vmux = CX25840_SVIDEO_LUMA3 |
  494. CX25840_SVIDEO_CHROMA4,
  495. }, {
  496. .type = CX23885_VMUX_COMPONENT,
  497. .vmux = CX25840_VIN7_CH1 |
  498. CX25840_VIN6_CH2 |
  499. CX25840_VIN8_CH3 |
  500. CX25840_COMPONENT_ON,
  501. } },
  502. },
  503. [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
  504. .name = "GoTView X5 3D Hybrid",
  505. .tuner_type = TUNER_XC5000,
  506. .tuner_addr = 0x64,
  507. .tuner_bus = 1,
  508. .porta = CX23885_ANALOG_VIDEO,
  509. .portb = CX23885_MPEG_DVB,
  510. .input = {{
  511. .type = CX23885_VMUX_TELEVISION,
  512. .vmux = CX25840_VIN2_CH1 |
  513. CX25840_VIN5_CH2,
  514. .gpio0 = 0x02,
  515. }, {
  516. .type = CX23885_VMUX_COMPOSITE1,
  517. .vmux = CX23885_VMUX_COMPOSITE1,
  518. }, {
  519. .type = CX23885_VMUX_SVIDEO,
  520. .vmux = CX25840_SVIDEO_LUMA3 |
  521. CX25840_SVIDEO_CHROMA4,
  522. } },
  523. },
  524. [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
  525. .ci_type = 2,
  526. .name = "NetUP Dual DVB-T/C-CI RF",
  527. .porta = CX23885_ANALOG_VIDEO,
  528. .portb = CX23885_MPEG_DVB,
  529. .portc = CX23885_MPEG_DVB,
  530. .num_fds_portb = 2,
  531. .num_fds_portc = 2,
  532. .tuner_type = TUNER_XC5000,
  533. .tuner_addr = 0x64,
  534. .input = { {
  535. .type = CX23885_VMUX_TELEVISION,
  536. .vmux = CX25840_COMPOSITE1,
  537. } },
  538. },
  539. [CX23885_BOARD_MPX885] = {
  540. .name = "MPX-885",
  541. .porta = CX23885_ANALOG_VIDEO,
  542. .input = {{
  543. .type = CX23885_VMUX_COMPOSITE1,
  544. .vmux = CX25840_COMPOSITE1,
  545. .amux = CX25840_AUDIO6,
  546. .gpio0 = 0,
  547. }, {
  548. .type = CX23885_VMUX_COMPOSITE2,
  549. .vmux = CX25840_COMPOSITE2,
  550. .amux = CX25840_AUDIO6,
  551. .gpio0 = 0,
  552. }, {
  553. .type = CX23885_VMUX_COMPOSITE3,
  554. .vmux = CX25840_COMPOSITE3,
  555. .amux = CX25840_AUDIO7,
  556. .gpio0 = 0,
  557. }, {
  558. .type = CX23885_VMUX_COMPOSITE4,
  559. .vmux = CX25840_COMPOSITE4,
  560. .amux = CX25840_AUDIO7,
  561. .gpio0 = 0,
  562. } },
  563. },
  564. [CX23885_BOARD_MYGICA_X8507] = {
  565. .name = "Mygica X8502/X8507 ISDB-T",
  566. .tuner_type = TUNER_XC5000,
  567. .tuner_addr = 0x61,
  568. .tuner_bus = 1,
  569. .porta = CX23885_ANALOG_VIDEO,
  570. .portb = CX23885_MPEG_DVB,
  571. .input = {
  572. {
  573. .type = CX23885_VMUX_TELEVISION,
  574. .vmux = CX25840_COMPOSITE2,
  575. .amux = CX25840_AUDIO8,
  576. },
  577. {
  578. .type = CX23885_VMUX_COMPOSITE1,
  579. .vmux = CX25840_COMPOSITE8,
  580. .amux = CX25840_AUDIO7,
  581. },
  582. {
  583. .type = CX23885_VMUX_SVIDEO,
  584. .vmux = CX25840_SVIDEO_LUMA3 |
  585. CX25840_SVIDEO_CHROMA4,
  586. .amux = CX25840_AUDIO7,
  587. },
  588. {
  589. .type = CX23885_VMUX_COMPONENT,
  590. .vmux = CX25840_COMPONENT_ON |
  591. CX25840_VIN1_CH1 |
  592. CX25840_VIN6_CH2 |
  593. CX25840_VIN7_CH3,
  594. .amux = CX25840_AUDIO7,
  595. },
  596. },
  597. },
  598. [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
  599. .name = "TerraTec Cinergy T PCIe Dual",
  600. .portb = CX23885_MPEG_DVB,
  601. .portc = CX23885_MPEG_DVB,
  602. },
  603. [CX23885_BOARD_TEVII_S471] = {
  604. .name = "TeVii S471",
  605. .portb = CX23885_MPEG_DVB,
  606. },
  607. [CX23885_BOARD_PROF_8000] = {
  608. .name = "Prof Revolution DVB-S2 8000",
  609. .portb = CX23885_MPEG_DVB,
  610. },
  611. [CX23885_BOARD_HAUPPAUGE_HVR4400] = {
  612. .name = "Hauppauge WinTV-HVR4400/HVR5500",
  613. .porta = CX23885_ANALOG_VIDEO,
  614. .portb = CX23885_MPEG_DVB,
  615. .portc = CX23885_MPEG_DVB,
  616. .tuner_type = TUNER_NXP_TDA18271,
  617. .tuner_addr = 0x60, /* 0xc0 >> 1 */
  618. .tuner_bus = 1,
  619. },
  620. [CX23885_BOARD_HAUPPAUGE_STARBURST] = {
  621. .name = "Hauppauge WinTV Starburst",
  622. .portb = CX23885_MPEG_DVB,
  623. },
  624. [CX23885_BOARD_AVERMEDIA_HC81R] = {
  625. .name = "AVerTV Hybrid Express Slim HC81R",
  626. .tuner_type = TUNER_XC2028,
  627. .tuner_addr = 0x61, /* 0xc2 >> 1 */
  628. .tuner_bus = 1,
  629. .porta = CX23885_ANALOG_VIDEO,
  630. .input = {{
  631. .type = CX23885_VMUX_TELEVISION,
  632. .vmux = CX25840_VIN2_CH1 |
  633. CX25840_VIN5_CH2 |
  634. CX25840_NONE0_CH3 |
  635. CX25840_NONE1_CH3,
  636. .amux = CX25840_AUDIO8,
  637. }, {
  638. .type = CX23885_VMUX_SVIDEO,
  639. .vmux = CX25840_VIN8_CH1 |
  640. CX25840_NONE_CH2 |
  641. CX25840_VIN7_CH3 |
  642. CX25840_SVIDEO_ON,
  643. .amux = CX25840_AUDIO6,
  644. }, {
  645. .type = CX23885_VMUX_COMPONENT,
  646. .vmux = CX25840_VIN1_CH1 |
  647. CX25840_NONE_CH2 |
  648. CX25840_NONE0_CH3 |
  649. CX25840_NONE1_CH3,
  650. .amux = CX25840_AUDIO6,
  651. } },
  652. },
  653. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = {
  654. .name = "DViCO FusionHDTV DVB-T Dual Express2",
  655. .portb = CX23885_MPEG_DVB,
  656. .portc = CX23885_MPEG_DVB,
  657. },
  658. [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = {
  659. .name = "Hauppauge ImpactVCB-e",
  660. .tuner_type = TUNER_ABSENT,
  661. .porta = CX23885_ANALOG_VIDEO,
  662. .input = {{
  663. .type = CX23885_VMUX_COMPOSITE1,
  664. .vmux = CX25840_VIN7_CH3 |
  665. CX25840_VIN4_CH2 |
  666. CX25840_VIN6_CH1,
  667. .amux = CX25840_AUDIO7,
  668. }, {
  669. .type = CX23885_VMUX_SVIDEO,
  670. .vmux = CX25840_VIN7_CH3 |
  671. CX25840_VIN4_CH2 |
  672. CX25840_VIN8_CH1 |
  673. CX25840_SVIDEO_ON,
  674. .amux = CX25840_AUDIO7,
  675. } },
  676. },
  677. [CX23885_BOARD_DVBSKY_T9580] = {
  678. .name = "DVBSky T9580",
  679. .portb = CX23885_MPEG_DVB,
  680. .portc = CX23885_MPEG_DVB,
  681. },
  682. [CX23885_BOARD_DVBSKY_T980C] = {
  683. .name = "DVBSky T980C",
  684. .portb = CX23885_MPEG_DVB,
  685. },
  686. [CX23885_BOARD_DVBSKY_S950C] = {
  687. .name = "DVBSky S950C",
  688. .portb = CX23885_MPEG_DVB,
  689. },
  690. [CX23885_BOARD_TT_CT2_4500_CI] = {
  691. .name = "Technotrend TT-budget CT2-4500 CI",
  692. .portb = CX23885_MPEG_DVB,
  693. },
  694. [CX23885_BOARD_DVBSKY_S950] = {
  695. .name = "DVBSky S950",
  696. .portb = CX23885_MPEG_DVB,
  697. },
  698. [CX23885_BOARD_DVBSKY_S952] = {
  699. .name = "DVBSky S952",
  700. .portb = CX23885_MPEG_DVB,
  701. .portc = CX23885_MPEG_DVB,
  702. },
  703. [CX23885_BOARD_DVBSKY_T982] = {
  704. .name = "DVBSky T982",
  705. .portb = CX23885_MPEG_DVB,
  706. .portc = CX23885_MPEG_DVB,
  707. },
  708. [CX23885_BOARD_HAUPPAUGE_HVR5525] = {
  709. .name = "Hauppauge WinTV-HVR5525",
  710. .portb = CX23885_MPEG_DVB,
  711. .portc = CX23885_MPEG_DVB,
  712. },
  713. [CX23885_BOARD_VIEWCAST_260E] = {
  714. .name = "ViewCast 260e",
  715. .porta = CX23885_ANALOG_VIDEO,
  716. .force_bff = 1,
  717. .input = {{
  718. .type = CX23885_VMUX_COMPOSITE1,
  719. .vmux = CX25840_VIN6_CH1,
  720. .amux = CX25840_AUDIO7,
  721. }, {
  722. .type = CX23885_VMUX_SVIDEO,
  723. .vmux = CX25840_VIN7_CH3 |
  724. CX25840_VIN5_CH1 |
  725. CX25840_SVIDEO_ON,
  726. .amux = CX25840_AUDIO7,
  727. }, {
  728. .type = CX23885_VMUX_COMPONENT,
  729. .vmux = CX25840_VIN7_CH3 |
  730. CX25840_VIN6_CH2 |
  731. CX25840_VIN5_CH1 |
  732. CX25840_COMPONENT_ON,
  733. .amux = CX25840_AUDIO7,
  734. } },
  735. },
  736. [CX23885_BOARD_VIEWCAST_460E] = {
  737. .name = "ViewCast 460e",
  738. .porta = CX23885_ANALOG_VIDEO,
  739. .force_bff = 1,
  740. .input = {{
  741. .type = CX23885_VMUX_COMPOSITE1,
  742. .vmux = CX25840_VIN4_CH1,
  743. .amux = CX25840_AUDIO7,
  744. }, {
  745. .type = CX23885_VMUX_SVIDEO,
  746. .vmux = CX25840_VIN7_CH3 |
  747. CX25840_VIN6_CH1 |
  748. CX25840_SVIDEO_ON,
  749. .amux = CX25840_AUDIO7,
  750. }, {
  751. .type = CX23885_VMUX_COMPONENT,
  752. .vmux = CX25840_VIN7_CH3 |
  753. CX25840_VIN6_CH1 |
  754. CX25840_VIN5_CH2 |
  755. CX25840_COMPONENT_ON,
  756. .amux = CX25840_AUDIO7,
  757. }, {
  758. .type = CX23885_VMUX_COMPOSITE2,
  759. .vmux = CX25840_VIN6_CH1,
  760. .amux = CX25840_AUDIO7,
  761. } },
  762. },
  763. [CX23885_BOARD_HAUPPAUGE_QUADHD_DVB] = {
  764. .name = "Hauppauge WinTV-QuadHD-DVB",
  765. .portb = CX23885_MPEG_DVB,
  766. .portc = CX23885_MPEG_DVB,
  767. },
  768. [CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC] = {
  769. .name = "Hauppauge WinTV-QuadHD-ATSC",
  770. .portb = CX23885_MPEG_DVB,
  771. .portc = CX23885_MPEG_DVB,
  772. },
  773. };
  774. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  775. /* ------------------------------------------------------------------ */
  776. /* PCI subsystem IDs */
  777. struct cx23885_subid cx23885_subids[] = {
  778. {
  779. .subvendor = 0x0070,
  780. .subdevice = 0x3400,
  781. .card = CX23885_BOARD_UNKNOWN,
  782. }, {
  783. .subvendor = 0x0070,
  784. .subdevice = 0x7600,
  785. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  786. }, {
  787. .subvendor = 0x0070,
  788. .subdevice = 0x7800,
  789. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  790. }, {
  791. .subvendor = 0x0070,
  792. .subdevice = 0x7801,
  793. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  794. }, {
  795. .subvendor = 0x0070,
  796. .subdevice = 0x7809,
  797. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  798. }, {
  799. .subvendor = 0x0070,
  800. .subdevice = 0x7911,
  801. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  802. }, {
  803. .subvendor = 0x18ac,
  804. .subdevice = 0xd500,
  805. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  806. }, {
  807. .subvendor = 0x0070,
  808. .subdevice = 0x7790,
  809. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  810. }, {
  811. .subvendor = 0x0070,
  812. .subdevice = 0x7797,
  813. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  814. }, {
  815. .subvendor = 0x0070,
  816. .subdevice = 0x7710,
  817. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  818. }, {
  819. .subvendor = 0x0070,
  820. .subdevice = 0x7717,
  821. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  822. }, {
  823. .subvendor = 0x0070,
  824. .subdevice = 0x71d1,
  825. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  826. }, {
  827. .subvendor = 0x0070,
  828. .subdevice = 0x71d3,
  829. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  830. }, {
  831. .subvendor = 0x0070,
  832. .subdevice = 0x8101,
  833. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  834. }, {
  835. .subvendor = 0x0070,
  836. .subdevice = 0x8010,
  837. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  838. }, {
  839. .subvendor = 0x18ac,
  840. .subdevice = 0xd618,
  841. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  842. }, {
  843. .subvendor = 0x18ac,
  844. .subdevice = 0xdb78,
  845. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  846. }, {
  847. .subvendor = 0x107d,
  848. .subdevice = 0x6681,
  849. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  850. }, {
  851. .subvendor = 0x107d,
  852. .subdevice = 0x6f21,
  853. .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200,
  854. }, {
  855. .subvendor = 0x107d,
  856. .subdevice = 0x6f39,
  857. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
  858. }, {
  859. .subvendor = 0x185b,
  860. .subdevice = 0xe800,
  861. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  862. }, {
  863. .subvendor = 0x6920,
  864. .subdevice = 0x8888,
  865. .card = CX23885_BOARD_TBS_6920,
  866. }, {
  867. .subvendor = 0x6980,
  868. .subdevice = 0x8888,
  869. .card = CX23885_BOARD_TBS_6980,
  870. }, {
  871. .subvendor = 0x6981,
  872. .subdevice = 0x8888,
  873. .card = CX23885_BOARD_TBS_6981,
  874. }, {
  875. .subvendor = 0xd470,
  876. .subdevice = 0x9022,
  877. .card = CX23885_BOARD_TEVII_S470,
  878. }, {
  879. .subvendor = 0x0001,
  880. .subdevice = 0x2005,
  881. .card = CX23885_BOARD_DVBWORLD_2005,
  882. }, {
  883. .subvendor = 0x1b55,
  884. .subdevice = 0x2a2c,
  885. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  886. }, {
  887. .subvendor = 0x0070,
  888. .subdevice = 0x2211,
  889. .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
  890. }, {
  891. .subvendor = 0x0070,
  892. .subdevice = 0x2215,
  893. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  894. }, {
  895. .subvendor = 0x0070,
  896. .subdevice = 0x221d,
  897. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  898. }, {
  899. .subvendor = 0x0070,
  900. .subdevice = 0x2251,
  901. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  902. }, {
  903. .subvendor = 0x0070,
  904. .subdevice = 0x2259,
  905. .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
  906. }, {
  907. .subvendor = 0x0070,
  908. .subdevice = 0x2291,
  909. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  910. }, {
  911. .subvendor = 0x0070,
  912. .subdevice = 0x2295,
  913. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  914. }, {
  915. .subvendor = 0x0070,
  916. .subdevice = 0x2299,
  917. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  918. }, {
  919. .subvendor = 0x0070,
  920. .subdevice = 0x229d,
  921. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  922. }, {
  923. .subvendor = 0x0070,
  924. .subdevice = 0x22f0,
  925. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  926. }, {
  927. .subvendor = 0x0070,
  928. .subdevice = 0x22f1,
  929. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  930. }, {
  931. .subvendor = 0x0070,
  932. .subdevice = 0x22f2,
  933. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  934. }, {
  935. .subvendor = 0x0070,
  936. .subdevice = 0x22f3,
  937. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  938. }, {
  939. .subvendor = 0x0070,
  940. .subdevice = 0x22f4,
  941. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  942. }, {
  943. .subvendor = 0x0070,
  944. .subdevice = 0x22f5,
  945. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  946. }, {
  947. .subvendor = 0x14f1,
  948. .subdevice = 0x8651,
  949. .card = CX23885_BOARD_MYGICA_X8506,
  950. }, {
  951. .subvendor = 0x14f1,
  952. .subdevice = 0x8657,
  953. .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
  954. }, {
  955. .subvendor = 0x0070,
  956. .subdevice = 0x8541,
  957. .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
  958. }, {
  959. .subvendor = 0x1858,
  960. .subdevice = 0xe800,
  961. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
  962. }, {
  963. .subvendor = 0x0070,
  964. .subdevice = 0x8551,
  965. .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
  966. }, {
  967. .subvendor = 0x14f1,
  968. .subdevice = 0x8578,
  969. .card = CX23885_BOARD_MYGICA_X8558PRO,
  970. }, {
  971. .subvendor = 0x107d,
  972. .subdevice = 0x6f22,
  973. .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
  974. }, {
  975. .subvendor = 0x5654,
  976. .subdevice = 0x2390,
  977. .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
  978. }, {
  979. .subvendor = 0x1b55,
  980. .subdevice = 0xe2e4,
  981. .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
  982. }, {
  983. .subvendor = 0x14f1,
  984. .subdevice = 0x8502,
  985. .card = CX23885_BOARD_MYGICA_X8507,
  986. }, {
  987. .subvendor = 0x153b,
  988. .subdevice = 0x117e,
  989. .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
  990. }, {
  991. .subvendor = 0xd471,
  992. .subdevice = 0x9022,
  993. .card = CX23885_BOARD_TEVII_S471,
  994. }, {
  995. .subvendor = 0x8000,
  996. .subdevice = 0x3034,
  997. .card = CX23885_BOARD_PROF_8000,
  998. }, {
  999. .subvendor = 0x0070,
  1000. .subdevice = 0xc108,
  1001. .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-4400 (Model 121xxx, Hybrid DVB-T/S2, IR) */
  1002. }, {
  1003. .subvendor = 0x0070,
  1004. .subdevice = 0xc138,
  1005. .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
  1006. }, {
  1007. .subvendor = 0x0070,
  1008. .subdevice = 0xc12a,
  1009. .card = CX23885_BOARD_HAUPPAUGE_STARBURST, /* Hauppauge WinTV Starburst (Model 121x00, DVB-S2, IR) */
  1010. }, {
  1011. .subvendor = 0x0070,
  1012. .subdevice = 0xc1f8,
  1013. .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
  1014. }, {
  1015. .subvendor = 0x1461,
  1016. .subdevice = 0xd939,
  1017. .card = CX23885_BOARD_AVERMEDIA_HC81R,
  1018. }, {
  1019. .subvendor = 0x0070,
  1020. .subdevice = 0x7133,
  1021. .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE,
  1022. }, {
  1023. .subvendor = 0x18ac,
  1024. .subdevice = 0xdb98,
  1025. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2,
  1026. }, {
  1027. .subvendor = 0x4254,
  1028. .subdevice = 0x9580,
  1029. .card = CX23885_BOARD_DVBSKY_T9580,
  1030. }, {
  1031. .subvendor = 0x4254,
  1032. .subdevice = 0x980c,
  1033. .card = CX23885_BOARD_DVBSKY_T980C,
  1034. }, {
  1035. .subvendor = 0x4254,
  1036. .subdevice = 0x950c,
  1037. .card = CX23885_BOARD_DVBSKY_S950C,
  1038. }, {
  1039. .subvendor = 0x13c2,
  1040. .subdevice = 0x3013,
  1041. .card = CX23885_BOARD_TT_CT2_4500_CI,
  1042. }, {
  1043. .subvendor = 0x4254,
  1044. .subdevice = 0x0950,
  1045. .card = CX23885_BOARD_DVBSKY_S950,
  1046. }, {
  1047. .subvendor = 0x4254,
  1048. .subdevice = 0x0952,
  1049. .card = CX23885_BOARD_DVBSKY_S952,
  1050. }, {
  1051. .subvendor = 0x4254,
  1052. .subdevice = 0x0982,
  1053. .card = CX23885_BOARD_DVBSKY_T982,
  1054. }, {
  1055. .subvendor = 0x0070,
  1056. .subdevice = 0xf038,
  1057. .card = CX23885_BOARD_HAUPPAUGE_HVR5525,
  1058. }, {
  1059. .subvendor = 0x1576,
  1060. .subdevice = 0x0260,
  1061. .card = CX23885_BOARD_VIEWCAST_260E,
  1062. }, {
  1063. .subvendor = 0x1576,
  1064. .subdevice = 0x0460,
  1065. .card = CX23885_BOARD_VIEWCAST_460E,
  1066. }, {
  1067. .subvendor = 0x0070,
  1068. .subdevice = 0x6a28,
  1069. .card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 1 */
  1070. }, {
  1071. .subvendor = 0x0070,
  1072. .subdevice = 0x6b28,
  1073. .card = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB, /* Tuner Pair 2 */
  1074. }, {
  1075. .subvendor = 0x0070,
  1076. .subdevice = 0x6a18,
  1077. .card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 1 */
  1078. }, {
  1079. .subvendor = 0x0070,
  1080. .subdevice = 0x6b18,
  1081. .card = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC, /* Tuner Pair 2 */
  1082. },
  1083. };
  1084. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  1085. void cx23885_card_list(struct cx23885_dev *dev)
  1086. {
  1087. int i;
  1088. if (0 == dev->pci->subsystem_vendor &&
  1089. 0 == dev->pci->subsystem_device) {
  1090. printk(KERN_INFO
  1091. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  1092. "%s: be autodetected. Pass card=<n> insmod option\n"
  1093. "%s: to workaround that. Redirect complaints to the\n"
  1094. "%s: vendor of the TV card. Best regards,\n"
  1095. "%s: -- tux\n",
  1096. dev->name, dev->name, dev->name, dev->name, dev->name);
  1097. } else {
  1098. printk(KERN_INFO
  1099. "%s: Your board isn't known (yet) to the driver.\n"
  1100. "%s: Try to pick one of the existing card configs via\n"
  1101. "%s: card=<n> insmod option. Updating to the latest\n"
  1102. "%s: version might help as well.\n",
  1103. dev->name, dev->name, dev->name, dev->name);
  1104. }
  1105. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  1106. dev->name);
  1107. for (i = 0; i < cx23885_bcount; i++)
  1108. printk(KERN_INFO "%s: card=%d -> %s\n",
  1109. dev->name, i, cx23885_boards[i].name);
  1110. }
  1111. static void viewcast_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  1112. {
  1113. u32 sn;
  1114. /* The serial number record begins with tag 0x59 */
  1115. if (*(eeprom_data + 0x00) != 0x59) {
  1116. pr_info("%s() eeprom records are undefined, no serial number\n",
  1117. __func__);
  1118. return;
  1119. }
  1120. sn = (*(eeprom_data + 0x06) << 24) |
  1121. (*(eeprom_data + 0x05) << 16) |
  1122. (*(eeprom_data + 0x04) << 8) |
  1123. (*(eeprom_data + 0x03));
  1124. pr_info("%s: card '%s' sn# MM%d\n",
  1125. dev->name,
  1126. cx23885_boards[dev->board].name,
  1127. sn);
  1128. }
  1129. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  1130. {
  1131. struct tveeprom tv;
  1132. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  1133. eeprom_data);
  1134. /* Make sure we support the board model */
  1135. switch (tv.model) {
  1136. case 22001:
  1137. /* WinTV-HVR1270 (PCIe, Retail, half height)
  1138. * ATSC/QAM and basic analog, IR Blast */
  1139. case 22009:
  1140. /* WinTV-HVR1210 (PCIe, Retail, half height)
  1141. * DVB-T and basic analog, IR Blast */
  1142. case 22011:
  1143. /* WinTV-HVR1270 (PCIe, Retail, half height)
  1144. * ATSC/QAM and basic analog, IR Recv */
  1145. case 22019:
  1146. /* WinTV-HVR1210 (PCIe, Retail, half height)
  1147. * DVB-T and basic analog, IR Recv */
  1148. case 22021:
  1149. /* WinTV-HVR1275 (PCIe, Retail, half height)
  1150. * ATSC/QAM and basic analog, IR Recv */
  1151. case 22029:
  1152. /* WinTV-HVR1210 (PCIe, Retail, half height)
  1153. * DVB-T and basic analog, IR Recv */
  1154. case 22101:
  1155. /* WinTV-HVR1270 (PCIe, Retail, full height)
  1156. * ATSC/QAM and basic analog, IR Blast */
  1157. case 22109:
  1158. /* WinTV-HVR1210 (PCIe, Retail, full height)
  1159. * DVB-T and basic analog, IR Blast */
  1160. case 22111:
  1161. /* WinTV-HVR1270 (PCIe, Retail, full height)
  1162. * ATSC/QAM and basic analog, IR Recv */
  1163. case 22119:
  1164. /* WinTV-HVR1210 (PCIe, Retail, full height)
  1165. * DVB-T and basic analog, IR Recv */
  1166. case 22121:
  1167. /* WinTV-HVR1275 (PCIe, Retail, full height)
  1168. * ATSC/QAM and basic analog, IR Recv */
  1169. case 22129:
  1170. /* WinTV-HVR1210 (PCIe, Retail, full height)
  1171. * DVB-T and basic analog, IR Recv */
  1172. case 71009:
  1173. /* WinTV-HVR1200 (PCIe, Retail, full height)
  1174. * DVB-T and basic analog */
  1175. case 71100:
  1176. /* WinTV-ImpactVCB-e (PCIe, Retail, half height)
  1177. * Basic analog */
  1178. case 71359:
  1179. /* WinTV-HVR1200 (PCIe, OEM, half height)
  1180. * DVB-T and basic analog */
  1181. case 71439:
  1182. /* WinTV-HVR1200 (PCIe, OEM, half height)
  1183. * DVB-T and basic analog */
  1184. case 71449:
  1185. /* WinTV-HVR1200 (PCIe, OEM, full height)
  1186. * DVB-T and basic analog */
  1187. case 71939:
  1188. /* WinTV-HVR1200 (PCIe, OEM, half height)
  1189. * DVB-T and basic analog */
  1190. case 71949:
  1191. /* WinTV-HVR1200 (PCIe, OEM, full height)
  1192. * DVB-T and basic analog */
  1193. case 71959:
  1194. /* WinTV-HVR1200 (PCIe, OEM, full height)
  1195. * DVB-T and basic analog */
  1196. case 71979:
  1197. /* WinTV-HVR1200 (PCIe, OEM, half height)
  1198. * DVB-T and basic analog */
  1199. case 71999:
  1200. /* WinTV-HVR1200 (PCIe, OEM, full height)
  1201. * DVB-T and basic analog */
  1202. case 76601:
  1203. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  1204. channel ATSC and MPEG2 HW Encoder */
  1205. case 77001:
  1206. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  1207. and Basic analog */
  1208. case 77011:
  1209. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  1210. and Basic analog */
  1211. case 77041:
  1212. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  1213. and Basic analog */
  1214. case 77051:
  1215. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  1216. and Basic analog */
  1217. case 78011:
  1218. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  1219. Dual channel ATSC and MPEG2 HW Encoder */
  1220. case 78501:
  1221. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  1222. Dual channel ATSC and MPEG2 HW Encoder */
  1223. case 78521:
  1224. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  1225. Dual channel ATSC and MPEG2 HW Encoder */
  1226. case 78531:
  1227. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  1228. Dual channel ATSC and MPEG2 HW Encoder */
  1229. case 78631:
  1230. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  1231. Dual channel ATSC and MPEG2 HW Encoder */
  1232. case 79001:
  1233. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  1234. ATSC and Basic analog */
  1235. case 79101:
  1236. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  1237. ATSC and Basic analog */
  1238. case 79501:
  1239. /* WinTV-HVR1250 (PCIe, No IR, half height,
  1240. ATSC [at least] and Basic analog) */
  1241. case 79561:
  1242. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  1243. ATSC and Basic analog */
  1244. case 79571:
  1245. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  1246. ATSC and Basic analog */
  1247. case 79671:
  1248. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  1249. ATSC and Basic analog */
  1250. case 80019:
  1251. /* WinTV-HVR1400 (Express Card, Retail, IR,
  1252. * DVB-T and Basic analog */
  1253. case 81509:
  1254. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  1255. * DVB-T and MPEG2 HW Encoder */
  1256. case 81519:
  1257. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  1258. * DVB-T and MPEG2 HW Encoder */
  1259. break;
  1260. case 85021:
  1261. /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
  1262. Dual channel ATSC and MPEG2 HW Encoder */
  1263. break;
  1264. case 85721:
  1265. /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
  1266. Dual channel ATSC and Basic analog */
  1267. case 150329:
  1268. /* WinTV-HVR5525 (PCIe, DVB-S/S2, DVB-T/T2/C) */
  1269. break;
  1270. case 166100:
  1271. /* WinTV-QuadHD (DVB) Tuner Pair 1 (PCIe, IR, half height,
  1272. DVB-T/T2/C, DVB-T/T2/C */
  1273. break;
  1274. case 166101:
  1275. /* WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height,
  1276. DVB-T/T2/C, DVB-T/T2/C */
  1277. break;
  1278. case 165100:
  1279. /*
  1280. * WinTV-QuadHD (ATSC) Tuner Pair 1 (PCIe, IR, half height,
  1281. * ATSC, ATSC
  1282. */
  1283. break;
  1284. case 165101:
  1285. /*
  1286. * WinTV-QuadHD (DVB) Tuner Pair 2 (PCIe, IR, half height,
  1287. * ATSC, ATSC
  1288. */
  1289. break;
  1290. default:
  1291. printk(KERN_WARNING "%s: warning: "
  1292. "unknown hauppauge model #%d\n",
  1293. dev->name, tv.model);
  1294. break;
  1295. }
  1296. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  1297. dev->name, tv.model);
  1298. }
  1299. /* Some TBS cards require initing a chip using a bitbanged SPI attached
  1300. to the cx23885 gpio's. If this chip doesn't get init'ed the demod
  1301. doesn't respond to any command. */
  1302. static void tbs_card_init(struct cx23885_dev *dev)
  1303. {
  1304. int i;
  1305. const u8 buf[] = {
  1306. 0xe0, 0x06, 0x66, 0x33, 0x65,
  1307. 0x01, 0x17, 0x06, 0xde};
  1308. switch (dev->board) {
  1309. case CX23885_BOARD_TBS_6980:
  1310. case CX23885_BOARD_TBS_6981:
  1311. cx_set(GP0_IO, 0x00070007);
  1312. usleep_range(1000, 10000);
  1313. cx_clear(GP0_IO, 2);
  1314. usleep_range(1000, 10000);
  1315. for (i = 0; i < 9 * 8; i++) {
  1316. cx_clear(GP0_IO, 7);
  1317. usleep_range(1000, 10000);
  1318. cx_set(GP0_IO,
  1319. ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4);
  1320. usleep_range(1000, 10000);
  1321. }
  1322. cx_set(GP0_IO, 7);
  1323. break;
  1324. }
  1325. }
  1326. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  1327. {
  1328. struct cx23885_tsport *port = priv;
  1329. struct cx23885_dev *dev = port->dev;
  1330. u32 bitmask = 0;
  1331. if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
  1332. return 0;
  1333. if (command != 0) {
  1334. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  1335. __func__, command);
  1336. return -EINVAL;
  1337. }
  1338. switch (dev->board) {
  1339. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1340. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1341. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1342. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1343. case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
  1344. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1345. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1346. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1347. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1348. /* Tuner Reset Command */
  1349. bitmask = 0x04;
  1350. break;
  1351. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1352. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1353. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
  1354. /* Two identical tuners on two different i2c buses,
  1355. * we need to reset the correct gpio. */
  1356. if (port->nr == 1)
  1357. bitmask = 0x01;
  1358. else if (port->nr == 2)
  1359. bitmask = 0x04;
  1360. break;
  1361. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1362. /* Tuner Reset Command */
  1363. bitmask = 0x02;
  1364. break;
  1365. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1366. altera_ci_tuner_reset(dev, port->nr);
  1367. break;
  1368. case CX23885_BOARD_AVERMEDIA_HC81R:
  1369. /* XC3028L Reset Command */
  1370. bitmask = 1 << 2;
  1371. break;
  1372. }
  1373. if (bitmask) {
  1374. /* Drive the tuner into reset and back out */
  1375. cx_clear(GP0_IO, bitmask);
  1376. mdelay(200);
  1377. cx_set(GP0_IO, bitmask);
  1378. }
  1379. return 0;
  1380. }
  1381. void cx23885_gpio_setup(struct cx23885_dev *dev)
  1382. {
  1383. switch (dev->board) {
  1384. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1385. /* GPIO-0 cx24227 demodulator reset */
  1386. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  1387. break;
  1388. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1389. /* GPIO-0 cx24227 demodulator */
  1390. /* GPIO-2 xc3028 tuner */
  1391. /* Put the parts into reset */
  1392. cx_set(GP0_IO, 0x00050000);
  1393. cx_clear(GP0_IO, 0x00000005);
  1394. msleep(5);
  1395. /* Bring the parts out of reset */
  1396. cx_set(GP0_IO, 0x00050005);
  1397. break;
  1398. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1399. /* GPIO-0 cx24227 demodulator reset */
  1400. /* GPIO-2 xc5000 tuner reset */
  1401. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  1402. break;
  1403. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1404. /* GPIO-0 656_CLK */
  1405. /* GPIO-1 656_D0 */
  1406. /* GPIO-2 8295A Reset */
  1407. /* GPIO-3-10 cx23417 data0-7 */
  1408. /* GPIO-11-14 cx23417 addr0-3 */
  1409. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1410. /* GPIO-19 IR_RX */
  1411. /* CX23417 GPIO's */
  1412. /* EIO15 Zilog Reset */
  1413. /* EIO14 S5H1409/CX24227 Reset */
  1414. mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
  1415. /* Put the demod into reset and protect the eeprom */
  1416. mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
  1417. mdelay(100);
  1418. /* Bring the demod and blaster out of reset */
  1419. mc417_gpio_set(dev, GPIO_15 | GPIO_14);
  1420. mdelay(100);
  1421. /* Force the TDA8295A into reset and back */
  1422. cx23885_gpio_enable(dev, GPIO_2, 1);
  1423. cx23885_gpio_set(dev, GPIO_2);
  1424. mdelay(20);
  1425. cx23885_gpio_clear(dev, GPIO_2);
  1426. mdelay(20);
  1427. cx23885_gpio_set(dev, GPIO_2);
  1428. mdelay(20);
  1429. break;
  1430. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1431. /* GPIO-0 tda10048 demodulator reset */
  1432. /* GPIO-2 tda18271 tuner reset */
  1433. /* Put the parts into reset and back */
  1434. cx_set(GP0_IO, 0x00050000);
  1435. mdelay(20);
  1436. cx_clear(GP0_IO, 0x00000005);
  1437. mdelay(20);
  1438. cx_set(GP0_IO, 0x00050005);
  1439. break;
  1440. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1441. /* GPIO-0 TDA10048 demodulator reset */
  1442. /* GPIO-2 TDA8295A Reset */
  1443. /* GPIO-3-10 cx23417 data0-7 */
  1444. /* GPIO-11-14 cx23417 addr0-3 */
  1445. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1446. /* The following GPIO's are on the interna AVCore (cx25840) */
  1447. /* GPIO-19 IR_RX */
  1448. /* GPIO-20 IR_TX 416/DVBT Select */
  1449. /* GPIO-21 IIS DAT */
  1450. /* GPIO-22 IIS WCLK */
  1451. /* GPIO-23 IIS BCLK */
  1452. /* Put the parts into reset and back */
  1453. cx_set(GP0_IO, 0x00050000);
  1454. mdelay(20);
  1455. cx_clear(GP0_IO, 0x00000005);
  1456. mdelay(20);
  1457. cx_set(GP0_IO, 0x00050005);
  1458. break;
  1459. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1460. /* GPIO-0 Dibcom7000p demodulator reset */
  1461. /* GPIO-2 xc3028L tuner reset */
  1462. /* GPIO-13 LED */
  1463. /* Put the parts into reset and back */
  1464. cx_set(GP0_IO, 0x00050000);
  1465. mdelay(20);
  1466. cx_clear(GP0_IO, 0x00000005);
  1467. mdelay(20);
  1468. cx_set(GP0_IO, 0x00050005);
  1469. break;
  1470. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1471. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  1472. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  1473. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  1474. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  1475. /* Put the parts into reset and back */
  1476. cx_set(GP0_IO, 0x000f0000);
  1477. mdelay(20);
  1478. cx_clear(GP0_IO, 0x0000000f);
  1479. mdelay(20);
  1480. cx_set(GP0_IO, 0x000f000f);
  1481. break;
  1482. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1483. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
  1484. /* GPIO-0 portb xc3028 reset */
  1485. /* GPIO-1 portb zl10353 reset */
  1486. /* GPIO-2 portc xc3028 reset */
  1487. /* GPIO-3 portc zl10353 reset */
  1488. /* Put the parts into reset and back */
  1489. cx_set(GP0_IO, 0x000f0000);
  1490. mdelay(20);
  1491. cx_clear(GP0_IO, 0x0000000f);
  1492. mdelay(20);
  1493. cx_set(GP0_IO, 0x000f000f);
  1494. break;
  1495. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1496. case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
  1497. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1498. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1499. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1500. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1501. /* GPIO-2 xc3028 tuner reset */
  1502. /* The following GPIO's are on the internal AVCore (cx25840) */
  1503. /* GPIO-? zl10353 demod reset */
  1504. /* Put the parts into reset and back */
  1505. cx_set(GP0_IO, 0x00040000);
  1506. mdelay(20);
  1507. cx_clear(GP0_IO, 0x00000004);
  1508. mdelay(20);
  1509. cx_set(GP0_IO, 0x00040004);
  1510. break;
  1511. case CX23885_BOARD_TBS_6920:
  1512. case CX23885_BOARD_TBS_6980:
  1513. case CX23885_BOARD_TBS_6981:
  1514. case CX23885_BOARD_PROF_8000:
  1515. cx_write(MC417_CTL, 0x00000036);
  1516. cx_write(MC417_OEN, 0x00001000);
  1517. cx_set(MC417_RWD, 0x00000002);
  1518. mdelay(200);
  1519. cx_clear(MC417_RWD, 0x00000800);
  1520. mdelay(200);
  1521. cx_set(MC417_RWD, 0x00000800);
  1522. mdelay(200);
  1523. break;
  1524. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1525. /* GPIO-0 INTA from CiMax1
  1526. GPIO-1 INTB from CiMax2
  1527. GPIO-2 reset chips
  1528. GPIO-3 to GPIO-10 data/addr for CA
  1529. GPIO-11 ~CS0 to CiMax1
  1530. GPIO-12 ~CS1 to CiMax2
  1531. GPIO-13 ADL0 load LSB addr
  1532. GPIO-14 ADL1 load MSB addr
  1533. GPIO-15 ~RDY from CiMax
  1534. GPIO-17 ~RD to CiMax
  1535. GPIO-18 ~WR to CiMax
  1536. */
  1537. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  1538. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  1539. cx_clear(GP0_IO, 0x00030004);
  1540. mdelay(100);/* reset delay */
  1541. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  1542. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  1543. /* GPIO-15 IN as ~ACK, rest as OUT */
  1544. cx_write(MC417_OEN, 0x00001000);
  1545. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  1546. cx_write(MC417_RWD, 0x0000c300);
  1547. /* enable irq */
  1548. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1549. break;
  1550. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1551. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1552. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1553. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1554. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1555. /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
  1556. /* GPIO-6 I2C Gate which can isolate the demod from the bus */
  1557. /* GPIO-9 Demod reset */
  1558. /* Put the parts into reset and back */
  1559. cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
  1560. cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
  1561. cx23885_gpio_clear(dev, GPIO_9);
  1562. mdelay(20);
  1563. cx23885_gpio_set(dev, GPIO_9);
  1564. break;
  1565. case CX23885_BOARD_MYGICA_X8506:
  1566. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1567. case CX23885_BOARD_MYGICA_X8507:
  1568. /* GPIO-0 (0)Analog / (1)Digital TV */
  1569. /* GPIO-1 reset XC5000 */
  1570. /* GPIO-2 demod reset */
  1571. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
  1572. cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
  1573. mdelay(100);
  1574. cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
  1575. mdelay(100);
  1576. break;
  1577. case CX23885_BOARD_MYGICA_X8558PRO:
  1578. /* GPIO-0 reset first ATBM8830 */
  1579. /* GPIO-1 reset second ATBM8830 */
  1580. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
  1581. cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
  1582. mdelay(100);
  1583. cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
  1584. mdelay(100);
  1585. break;
  1586. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1587. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1588. /* GPIO-0 656_CLK */
  1589. /* GPIO-1 656_D0 */
  1590. /* GPIO-2 Wake# */
  1591. /* GPIO-3-10 cx23417 data0-7 */
  1592. /* GPIO-11-14 cx23417 addr0-3 */
  1593. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1594. /* GPIO-19 IR_RX */
  1595. /* GPIO-20 C_IR_TX */
  1596. /* GPIO-21 I2S DAT */
  1597. /* GPIO-22 I2S WCLK */
  1598. /* GPIO-23 I2S BCLK */
  1599. /* ALT GPIO: EXP GPIO LATCH */
  1600. /* CX23417 GPIO's */
  1601. /* GPIO-14 S5H1411/CX24228 Reset */
  1602. /* GPIO-13 EEPROM write protect */
  1603. mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
  1604. /* Put the demod into reset and protect the eeprom */
  1605. mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
  1606. mdelay(100);
  1607. /* Bring the demod out of reset */
  1608. mc417_gpio_set(dev, GPIO_14);
  1609. mdelay(100);
  1610. /* CX24228 GPIO */
  1611. /* Connected to IF / Mux */
  1612. break;
  1613. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1614. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  1615. break;
  1616. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1617. /* GPIO-0 ~INT in
  1618. GPIO-1 TMS out
  1619. GPIO-2 ~reset chips out
  1620. GPIO-3 to GPIO-10 data/addr for CA in/out
  1621. GPIO-11 ~CS out
  1622. GPIO-12 ADDR out
  1623. GPIO-13 ~WR out
  1624. GPIO-14 ~RD out
  1625. GPIO-15 ~RDY in
  1626. GPIO-16 TCK out
  1627. GPIO-17 TDO in
  1628. GPIO-18 TDI out
  1629. */
  1630. cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
  1631. /* GPIO-0 as INT, reset & TMS low */
  1632. cx_clear(GP0_IO, 0x00010006);
  1633. mdelay(100);/* reset delay */
  1634. cx_set(GP0_IO, 0x00000004); /* reset high */
  1635. cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
  1636. /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
  1637. cx_write(MC417_OEN, 0x00005000);
  1638. /* ~RD, ~WR high; ADDR low; ~CS high */
  1639. cx_write(MC417_RWD, 0x00000d00);
  1640. /* enable irq */
  1641. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1642. break;
  1643. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1644. case CX23885_BOARD_HAUPPAUGE_STARBURST:
  1645. /* GPIO-8 tda10071 demod reset */
  1646. /* GPIO-9 si2165 demod reset (only HVR4400/HVR5500)*/
  1647. /* Put the parts into reset and back */
  1648. cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
  1649. cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
  1650. mdelay(100);
  1651. cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
  1652. mdelay(100);
  1653. break;
  1654. case CX23885_BOARD_AVERMEDIA_HC81R:
  1655. cx_clear(MC417_CTL, 1);
  1656. /* GPIO-0,1,2 setup direction as output */
  1657. cx_set(GP0_IO, 0x00070000);
  1658. mdelay(10);
  1659. /* AF9013 demod reset */
  1660. cx_set(GP0_IO, 0x00010001);
  1661. mdelay(10);
  1662. cx_clear(GP0_IO, 0x00010001);
  1663. mdelay(10);
  1664. cx_set(GP0_IO, 0x00010001);
  1665. mdelay(10);
  1666. /* demod tune? */
  1667. cx_clear(GP0_IO, 0x00030003);
  1668. mdelay(10);
  1669. cx_set(GP0_IO, 0x00020002);
  1670. mdelay(10);
  1671. cx_set(GP0_IO, 0x00010001);
  1672. mdelay(10);
  1673. cx_clear(GP0_IO, 0x00020002);
  1674. /* XC3028L tuner reset */
  1675. cx_set(GP0_IO, 0x00040004);
  1676. cx_clear(GP0_IO, 0x00040004);
  1677. cx_set(GP0_IO, 0x00040004);
  1678. mdelay(60);
  1679. break;
  1680. case CX23885_BOARD_DVBSKY_T9580:
  1681. case CX23885_BOARD_DVBSKY_S952:
  1682. case CX23885_BOARD_DVBSKY_T982:
  1683. /* enable GPIO3-18 pins */
  1684. cx_write(MC417_CTL, 0x00000037);
  1685. cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1);
  1686. cx23885_gpio_clear(dev, GPIO_2 | GPIO_11);
  1687. mdelay(100);
  1688. cx23885_gpio_set(dev, GPIO_2 | GPIO_11);
  1689. break;
  1690. case CX23885_BOARD_DVBSKY_T980C:
  1691. case CX23885_BOARD_DVBSKY_S950C:
  1692. case CX23885_BOARD_TT_CT2_4500_CI:
  1693. /*
  1694. * GPIO-0 INTA from CiMax, input
  1695. * GPIO-1 reset CiMax, output, high active
  1696. * GPIO-2 reset demod, output, low active
  1697. * GPIO-3 to GPIO-10 data/addr for CAM
  1698. * GPIO-11 ~CS0 to CiMax1
  1699. * GPIO-12 ~CS1 to CiMax2
  1700. * GPIO-13 ADL0 load LSB addr
  1701. * GPIO-14 ADL1 load MSB addr
  1702. * GPIO-15 ~RDY from CiMax
  1703. * GPIO-17 ~RD to CiMax
  1704. * GPIO-18 ~WR to CiMax
  1705. */
  1706. cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */
  1707. cx_clear(GP0_IO, 0x00010004); /* GPIO 0 as input */
  1708. mdelay(100); /* reset delay */
  1709. cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */
  1710. cx_clear(GP0_IO, 0x00010002);
  1711. cx_write(MC417_CTL, 0x00000037); /* enable GPIO3-18 pins */
  1712. /* GPIO-15 IN as ~ACK, rest as OUT */
  1713. cx_write(MC417_OEN, 0x00001000);
  1714. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  1715. cx_write(MC417_RWD, 0x0000c300);
  1716. /* enable irq */
  1717. cx_write(GPIO_ISM, 0x00000000); /* INTERRUPTS active low */
  1718. break;
  1719. case CX23885_BOARD_DVBSKY_S950:
  1720. cx23885_gpio_enable(dev, GPIO_2, 1);
  1721. cx23885_gpio_clear(dev, GPIO_2);
  1722. msleep(100);
  1723. cx23885_gpio_set(dev, GPIO_2);
  1724. break;
  1725. case CX23885_BOARD_HAUPPAUGE_HVR5525:
  1726. case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
  1727. case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
  1728. /*
  1729. * HVR5525 GPIO Details:
  1730. * GPIO-00 IR_WIDE
  1731. * GPIO-02 wake#
  1732. * GPIO-03 VAUX Pres.
  1733. * GPIO-07 PROG#
  1734. * GPIO-08 SAT_RESN
  1735. * GPIO-09 TER_RESN
  1736. * GPIO-10 B2_SENSE
  1737. * GPIO-11 B1_SENSE
  1738. * GPIO-15 IR_LED_STATUS
  1739. * GPIO-19 IR_NARROW
  1740. * GPIO-20 Blauster1
  1741. * ALTGPIO VAUX_SWITCH
  1742. * AUX_PLL_CLK : Blaster2
  1743. */
  1744. /* Put the parts into reset and back */
  1745. cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
  1746. cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
  1747. msleep(100);
  1748. cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
  1749. msleep(100);
  1750. break;
  1751. case CX23885_BOARD_VIEWCAST_260E:
  1752. case CX23885_BOARD_VIEWCAST_460E:
  1753. /* For documentation purposes, it's worth noting that this
  1754. * card does not have any GPIO's connected to subcomponents.
  1755. */
  1756. break;
  1757. }
  1758. }
  1759. int cx23885_ir_init(struct cx23885_dev *dev)
  1760. {
  1761. static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
  1762. {
  1763. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1764. .pin = CX23885_PIN_IR_RX_GPIO19,
  1765. .function = CX23885_PAD_IR_RX,
  1766. .value = 0,
  1767. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1768. }, {
  1769. .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
  1770. .pin = CX23885_PIN_IR_TX_GPIO20,
  1771. .function = CX23885_PAD_IR_TX,
  1772. .value = 0,
  1773. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1774. }
  1775. };
  1776. const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
  1777. static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
  1778. {
  1779. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1780. .pin = CX23885_PIN_IR_RX_GPIO19,
  1781. .function = CX23885_PAD_IR_RX,
  1782. .value = 0,
  1783. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1784. }
  1785. };
  1786. const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
  1787. struct v4l2_subdev_ir_parameters params;
  1788. int ret = 0;
  1789. switch (dev->board) {
  1790. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1791. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1792. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1793. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1794. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1795. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1796. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1797. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1798. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1799. case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
  1800. case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
  1801. /* FIXME: Implement me */
  1802. break;
  1803. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1804. ret = cx23888_ir_probe(dev);
  1805. if (ret)
  1806. break;
  1807. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1808. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1809. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1810. break;
  1811. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1812. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1813. ret = cx23888_ir_probe(dev);
  1814. if (ret)
  1815. break;
  1816. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1817. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1818. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1819. /*
  1820. * For these boards we need to invert the Tx output via the
  1821. * IR controller to have the LED off while idle
  1822. */
  1823. v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
  1824. params.enable = false;
  1825. params.shutdown = false;
  1826. params.invert_level = true;
  1827. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1828. params.shutdown = true;
  1829. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1830. break;
  1831. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1832. case CX23885_BOARD_TEVII_S470:
  1833. case CX23885_BOARD_MYGICA_X8507:
  1834. case CX23885_BOARD_TBS_6980:
  1835. case CX23885_BOARD_TBS_6981:
  1836. case CX23885_BOARD_DVBSKY_T9580:
  1837. case CX23885_BOARD_DVBSKY_T980C:
  1838. case CX23885_BOARD_DVBSKY_S950C:
  1839. case CX23885_BOARD_TT_CT2_4500_CI:
  1840. case CX23885_BOARD_DVBSKY_S950:
  1841. case CX23885_BOARD_DVBSKY_S952:
  1842. case CX23885_BOARD_DVBSKY_T982:
  1843. if (!enable_885_ir)
  1844. break;
  1845. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1846. if (dev->sd_ir == NULL) {
  1847. ret = -ENODEV;
  1848. break;
  1849. }
  1850. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1851. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1852. break;
  1853. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1854. if (!enable_885_ir)
  1855. break;
  1856. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1857. if (dev->sd_ir == NULL) {
  1858. ret = -ENODEV;
  1859. break;
  1860. }
  1861. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1862. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1863. break;
  1864. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1865. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
  1866. request_module("ir-kbd-i2c");
  1867. break;
  1868. }
  1869. return ret;
  1870. }
  1871. void cx23885_ir_fini(struct cx23885_dev *dev)
  1872. {
  1873. switch (dev->board) {
  1874. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1875. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1876. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1877. cx23885_irq_remove(dev, PCI_MSK_IR);
  1878. cx23888_ir_remove(dev);
  1879. dev->sd_ir = NULL;
  1880. break;
  1881. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1882. case CX23885_BOARD_TEVII_S470:
  1883. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1884. case CX23885_BOARD_MYGICA_X8507:
  1885. case CX23885_BOARD_TBS_6980:
  1886. case CX23885_BOARD_TBS_6981:
  1887. case CX23885_BOARD_DVBSKY_T9580:
  1888. case CX23885_BOARD_DVBSKY_T980C:
  1889. case CX23885_BOARD_DVBSKY_S950C:
  1890. case CX23885_BOARD_TT_CT2_4500_CI:
  1891. case CX23885_BOARD_DVBSKY_S950:
  1892. case CX23885_BOARD_DVBSKY_S952:
  1893. case CX23885_BOARD_DVBSKY_T982:
  1894. cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
  1895. /* sd_ir is a duplicate pointer to the AV Core, just clear it */
  1896. dev->sd_ir = NULL;
  1897. break;
  1898. }
  1899. }
  1900. static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
  1901. {
  1902. int data;
  1903. int tdo = 0;
  1904. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  1905. /*TMS*/
  1906. data = ((cx_read(GP0_IO)) & (~0x00000002));
  1907. data |= (tms ? 0x00020002 : 0x00020000);
  1908. cx_write(GP0_IO, data);
  1909. /*TDI*/
  1910. data = ((cx_read(MC417_RWD)) & (~0x0000a000));
  1911. data |= (tdi ? 0x00008000 : 0);
  1912. cx_write(MC417_RWD, data);
  1913. if (read_tdo)
  1914. tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
  1915. cx_write(MC417_RWD, data | 0x00002000);
  1916. udelay(1);
  1917. /*TCK*/
  1918. cx_write(MC417_RWD, data);
  1919. return tdo;
  1920. }
  1921. void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
  1922. {
  1923. switch (dev->board) {
  1924. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1925. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1926. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1927. if (dev->sd_ir)
  1928. cx23885_irq_add_enable(dev, PCI_MSK_IR);
  1929. break;
  1930. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1931. case CX23885_BOARD_TEVII_S470:
  1932. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1933. case CX23885_BOARD_MYGICA_X8507:
  1934. case CX23885_BOARD_TBS_6980:
  1935. case CX23885_BOARD_TBS_6981:
  1936. case CX23885_BOARD_DVBSKY_T9580:
  1937. case CX23885_BOARD_DVBSKY_T980C:
  1938. case CX23885_BOARD_DVBSKY_S950C:
  1939. case CX23885_BOARD_TT_CT2_4500_CI:
  1940. case CX23885_BOARD_DVBSKY_S950:
  1941. case CX23885_BOARD_DVBSKY_S952:
  1942. case CX23885_BOARD_DVBSKY_T982:
  1943. if (dev->sd_ir)
  1944. cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
  1945. break;
  1946. }
  1947. }
  1948. void cx23885_card_setup(struct cx23885_dev *dev)
  1949. {
  1950. struct cx23885_tsport *ts1 = &dev->ts1;
  1951. struct cx23885_tsport *ts2 = &dev->ts2;
  1952. static u8 eeprom[256];
  1953. if (dev->i2c_bus[0].i2c_rc == 0) {
  1954. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1955. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  1956. eeprom, sizeof(eeprom));
  1957. }
  1958. switch (dev->board) {
  1959. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1960. if (dev->i2c_bus[0].i2c_rc == 0) {
  1961. if (eeprom[0x80] != 0x84)
  1962. hauppauge_eeprom(dev, eeprom+0xc0);
  1963. else
  1964. hauppauge_eeprom(dev, eeprom+0x80);
  1965. }
  1966. break;
  1967. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1968. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1969. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1970. if (dev->i2c_bus[0].i2c_rc == 0)
  1971. hauppauge_eeprom(dev, eeprom+0x80);
  1972. break;
  1973. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1974. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1975. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1976. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1977. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1978. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1979. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1980. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1981. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1982. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1983. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1984. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1985. case CX23885_BOARD_HAUPPAUGE_STARBURST:
  1986. case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
  1987. case CX23885_BOARD_HAUPPAUGE_HVR5525:
  1988. case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
  1989. case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
  1990. if (dev->i2c_bus[0].i2c_rc == 0)
  1991. hauppauge_eeprom(dev, eeprom+0xc0);
  1992. break;
  1993. case CX23885_BOARD_VIEWCAST_260E:
  1994. case CX23885_BOARD_VIEWCAST_460E:
  1995. dev->i2c_bus[1].i2c_client.addr = 0xa0 >> 1;
  1996. tveeprom_read(&dev->i2c_bus[1].i2c_client,
  1997. eeprom, sizeof(eeprom));
  1998. if (dev->i2c_bus[0].i2c_rc == 0)
  1999. viewcast_eeprom(dev, eeprom);
  2000. break;
  2001. }
  2002. switch (dev->board) {
  2003. case CX23885_BOARD_AVERMEDIA_HC81R:
  2004. /* Defaults for VID B */
  2005. ts1->gen_ctrl_val = 0x4; /* Parallel */
  2006. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2007. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2008. /* Defaults for VID C */
  2009. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  2010. ts2->gen_ctrl_val = 0x10e;
  2011. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2012. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2013. break;
  2014. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  2015. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  2016. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
  2017. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2018. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2019. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2020. /* break omitted intentionally */
  2021. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  2022. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2023. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2024. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2025. break;
  2026. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  2027. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  2028. /* Defaults for VID B - Analog encoder */
  2029. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  2030. ts1->gen_ctrl_val = 0x10e;
  2031. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2032. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2033. /* APB_TSVALERR_POL (active low)*/
  2034. ts1->vld_misc_val = 0x2000;
  2035. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  2036. cx_write(0x130184, 0xc);
  2037. /* Defaults for VID C */
  2038. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2039. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2040. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2041. break;
  2042. case CX23885_BOARD_TBS_6920:
  2043. ts1->gen_ctrl_val = 0x4; /* Parallel */
  2044. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2045. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2046. break;
  2047. case CX23885_BOARD_TEVII_S470:
  2048. case CX23885_BOARD_TEVII_S471:
  2049. case CX23885_BOARD_DVBWORLD_2005:
  2050. case CX23885_BOARD_PROF_8000:
  2051. case CX23885_BOARD_DVBSKY_T980C:
  2052. case CX23885_BOARD_DVBSKY_S950C:
  2053. case CX23885_BOARD_TT_CT2_4500_CI:
  2054. case CX23885_BOARD_DVBSKY_S950:
  2055. ts1->gen_ctrl_val = 0x5; /* Parallel */
  2056. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2057. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2058. break;
  2059. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  2060. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  2061. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  2062. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2063. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2064. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2065. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2066. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2067. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2068. break;
  2069. case CX23885_BOARD_TBS_6980:
  2070. case CX23885_BOARD_TBS_6981:
  2071. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2072. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2073. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2074. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2075. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2076. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2077. tbs_card_init(dev);
  2078. break;
  2079. case CX23885_BOARD_MYGICA_X8506:
  2080. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  2081. case CX23885_BOARD_MYGICA_X8507:
  2082. ts1->gen_ctrl_val = 0x5; /* Parallel */
  2083. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2084. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2085. break;
  2086. case CX23885_BOARD_MYGICA_X8558PRO:
  2087. ts1->gen_ctrl_val = 0x5; /* Parallel */
  2088. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2089. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2090. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2091. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2092. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2093. break;
  2094. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  2095. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2096. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2097. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2098. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2099. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2100. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2101. break;
  2102. case CX23885_BOARD_HAUPPAUGE_STARBURST:
  2103. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2104. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2105. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2106. break;
  2107. case CX23885_BOARD_DVBSKY_T9580:
  2108. case CX23885_BOARD_DVBSKY_T982:
  2109. ts1->gen_ctrl_val = 0x5; /* Parallel */
  2110. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2111. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2112. ts2->gen_ctrl_val = 0x8; /* Serial bus */
  2113. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2114. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2115. break;
  2116. case CX23885_BOARD_DVBSKY_S952:
  2117. ts1->gen_ctrl_val = 0x5; /* Parallel */
  2118. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2119. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2120. ts2->gen_ctrl_val = 0xe; /* Serial bus */
  2121. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2122. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2123. break;
  2124. case CX23885_BOARD_HAUPPAUGE_HVR5525:
  2125. ts1->gen_ctrl_val = 0x5; /* Parallel */
  2126. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2127. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2128. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2129. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2130. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2131. break;
  2132. case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
  2133. case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
  2134. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2135. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2136. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2137. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2138. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2139. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2140. break;
  2141. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  2142. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  2143. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  2144. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  2145. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  2146. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  2147. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  2148. case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
  2149. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  2150. case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
  2151. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  2152. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  2153. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  2154. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  2155. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  2156. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  2157. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  2158. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  2159. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  2160. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  2161. default:
  2162. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  2163. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  2164. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  2165. }
  2166. /* Certain boards support analog, or require the avcore to be
  2167. * loaded, ensure this happens.
  2168. */
  2169. switch (dev->board) {
  2170. case CX23885_BOARD_TEVII_S470:
  2171. /* Currently only enabled for the integrated IR controller */
  2172. if (!enable_885_ir)
  2173. break;
  2174. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  2175. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  2176. case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
  2177. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  2178. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  2179. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  2180. case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
  2181. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  2182. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  2183. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  2184. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  2185. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  2186. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  2187. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  2188. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  2189. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  2190. case CX23885_BOARD_MYGICA_X8506:
  2191. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  2192. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  2193. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  2194. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  2195. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  2196. case CX23885_BOARD_MPX885:
  2197. case CX23885_BOARD_MYGICA_X8507:
  2198. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  2199. case CX23885_BOARD_AVERMEDIA_HC81R:
  2200. case CX23885_BOARD_TBS_6980:
  2201. case CX23885_BOARD_TBS_6981:
  2202. case CX23885_BOARD_DVBSKY_T9580:
  2203. case CX23885_BOARD_DVBSKY_T980C:
  2204. case CX23885_BOARD_DVBSKY_S950C:
  2205. case CX23885_BOARD_TT_CT2_4500_CI:
  2206. case CX23885_BOARD_DVBSKY_S950:
  2207. case CX23885_BOARD_DVBSKY_S952:
  2208. case CX23885_BOARD_DVBSKY_T982:
  2209. case CX23885_BOARD_VIEWCAST_260E:
  2210. case CX23885_BOARD_VIEWCAST_460E:
  2211. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
  2212. &dev->i2c_bus[2].i2c_adap,
  2213. "cx25840", 0x88 >> 1, NULL);
  2214. if (dev->sd_cx25840) {
  2215. /* set host data for clk_freq configuration */
  2216. v4l2_set_subdev_hostdata(dev->sd_cx25840,
  2217. &dev->clk_freq);
  2218. dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
  2219. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  2220. }
  2221. break;
  2222. }
  2223. switch (dev->board) {
  2224. case CX23885_BOARD_VIEWCAST_260E:
  2225. v4l2_i2c_new_subdev(&dev->v4l2_dev,
  2226. &dev->i2c_bus[0].i2c_adap,
  2227. "cs3308", 0x82 >> 1, NULL);
  2228. break;
  2229. case CX23885_BOARD_VIEWCAST_460E:
  2230. /* This cs3308 controls the audio from the breakout cable */
  2231. v4l2_i2c_new_subdev(&dev->v4l2_dev,
  2232. &dev->i2c_bus[0].i2c_adap,
  2233. "cs3308", 0x80 >> 1, NULL);
  2234. /* This cs3308 controls the audio from the onboard header */
  2235. v4l2_i2c_new_subdev(&dev->v4l2_dev,
  2236. &dev->i2c_bus[0].i2c_adap,
  2237. "cs3308", 0x82 >> 1, NULL);
  2238. break;
  2239. }
  2240. /* AUX-PLL 27MHz CLK */
  2241. switch (dev->board) {
  2242. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  2243. netup_initialize(dev);
  2244. break;
  2245. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  2246. int ret;
  2247. const struct firmware *fw;
  2248. const char *filename = "dvb-netup-altera-01.fw";
  2249. char *action = "configure";
  2250. static struct netup_card_info cinfo;
  2251. struct altera_config netup_config = {
  2252. .dev = dev,
  2253. .action = action,
  2254. .jtag_io = netup_jtag_io,
  2255. };
  2256. netup_initialize(dev);
  2257. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  2258. if (netup_card_rev)
  2259. cinfo.rev = netup_card_rev;
  2260. switch (cinfo.rev) {
  2261. case 0x4:
  2262. filename = "dvb-netup-altera-04.fw";
  2263. break;
  2264. default:
  2265. filename = "dvb-netup-altera-01.fw";
  2266. break;
  2267. }
  2268. printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
  2269. cinfo.rev, filename);
  2270. ret = request_firmware(&fw, filename, &dev->pci->dev);
  2271. if (ret != 0)
  2272. printk(KERN_ERR "did not find the firmware file. (%s) "
  2273. "Please see linux/Documentation/dvb/ for more details "
  2274. "on firmware-problems.", filename);
  2275. else
  2276. altera_init(&netup_config, fw);
  2277. release_firmware(fw);
  2278. break;
  2279. }
  2280. }
  2281. }