arizona-core.c 37 KB

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  1. /*
  2. * Arizona core driver
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <[email protected]>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. #include <linux/gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/mfd/core.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <linux/of_gpio.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/regmap.h>
  24. #include <linux/regulator/consumer.h>
  25. #include <linux/regulator/machine.h>
  26. #include <linux/slab.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/mfd/arizona/core.h>
  29. #include <linux/mfd/arizona/registers.h>
  30. #include "arizona.h"
  31. static const char * const wm5102_core_supplies[] = {
  32. "AVDD",
  33. "DBVDD1",
  34. };
  35. int arizona_clk32k_enable(struct arizona *arizona)
  36. {
  37. int ret = 0;
  38. mutex_lock(&arizona->clk_lock);
  39. arizona->clk32k_ref++;
  40. if (arizona->clk32k_ref == 1) {
  41. switch (arizona->pdata.clk32k_src) {
  42. case ARIZONA_32KZ_MCLK1:
  43. ret = pm_runtime_get_sync(arizona->dev);
  44. if (ret != 0)
  45. goto err_ref;
  46. ret = clk_prepare_enable(arizona->mclk[ARIZONA_MCLK1]);
  47. if (ret != 0)
  48. goto err_pm;
  49. break;
  50. case ARIZONA_32KZ_MCLK2:
  51. ret = clk_prepare_enable(arizona->mclk[ARIZONA_MCLK2]);
  52. if (ret != 0)
  53. goto err_ref;
  54. break;
  55. }
  56. ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  57. ARIZONA_CLK_32K_ENA,
  58. ARIZONA_CLK_32K_ENA);
  59. }
  60. err_pm:
  61. pm_runtime_put_sync(arizona->dev);
  62. err_ref:
  63. if (ret != 0)
  64. arizona->clk32k_ref--;
  65. mutex_unlock(&arizona->clk_lock);
  66. return ret;
  67. }
  68. EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
  69. int arizona_clk32k_disable(struct arizona *arizona)
  70. {
  71. mutex_lock(&arizona->clk_lock);
  72. BUG_ON(arizona->clk32k_ref <= 0);
  73. arizona->clk32k_ref--;
  74. if (arizona->clk32k_ref == 0) {
  75. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  76. ARIZONA_CLK_32K_ENA, 0);
  77. switch (arizona->pdata.clk32k_src) {
  78. case ARIZONA_32KZ_MCLK1:
  79. pm_runtime_put_sync(arizona->dev);
  80. clk_disable_unprepare(arizona->mclk[ARIZONA_MCLK1]);
  81. break;
  82. case ARIZONA_32KZ_MCLK2:
  83. clk_disable_unprepare(arizona->mclk[ARIZONA_MCLK2]);
  84. break;
  85. }
  86. }
  87. mutex_unlock(&arizona->clk_lock);
  88. return 0;
  89. }
  90. EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
  91. static irqreturn_t arizona_clkgen_err(int irq, void *data)
  92. {
  93. struct arizona *arizona = data;
  94. dev_err(arizona->dev, "CLKGEN error\n");
  95. return IRQ_HANDLED;
  96. }
  97. static irqreturn_t arizona_underclocked(int irq, void *data)
  98. {
  99. struct arizona *arizona = data;
  100. unsigned int val;
  101. int ret;
  102. ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
  103. &val);
  104. if (ret != 0) {
  105. dev_err(arizona->dev, "Failed to read underclock status: %d\n",
  106. ret);
  107. return IRQ_NONE;
  108. }
  109. if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
  110. dev_err(arizona->dev, "AIF3 underclocked\n");
  111. if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
  112. dev_err(arizona->dev, "AIF2 underclocked\n");
  113. if (val & ARIZONA_AIF1_UNDERCLOCKED_STS)
  114. dev_err(arizona->dev, "AIF1 underclocked\n");
  115. if (val & ARIZONA_ISRC3_UNDERCLOCKED_STS)
  116. dev_err(arizona->dev, "ISRC3 underclocked\n");
  117. if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
  118. dev_err(arizona->dev, "ISRC2 underclocked\n");
  119. if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
  120. dev_err(arizona->dev, "ISRC1 underclocked\n");
  121. if (val & ARIZONA_FX_UNDERCLOCKED_STS)
  122. dev_err(arizona->dev, "FX underclocked\n");
  123. if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
  124. dev_err(arizona->dev, "ASRC underclocked\n");
  125. if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
  126. dev_err(arizona->dev, "DAC underclocked\n");
  127. if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
  128. dev_err(arizona->dev, "ADC underclocked\n");
  129. if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
  130. dev_err(arizona->dev, "Mixer dropped sample\n");
  131. return IRQ_HANDLED;
  132. }
  133. static irqreturn_t arizona_overclocked(int irq, void *data)
  134. {
  135. struct arizona *arizona = data;
  136. unsigned int val[3];
  137. int ret;
  138. ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
  139. &val[0], 3);
  140. if (ret != 0) {
  141. dev_err(arizona->dev, "Failed to read overclock status: %d\n",
  142. ret);
  143. return IRQ_NONE;
  144. }
  145. switch (arizona->type) {
  146. case WM8998:
  147. case WM1814:
  148. /* Some bits are shifted on WM8998,
  149. * rearrange to match the standard bit layout
  150. */
  151. val[0] = ((val[0] & 0x60e0) >> 1) |
  152. ((val[0] & 0x1e00) >> 2) |
  153. (val[0] & 0x000f);
  154. break;
  155. default:
  156. break;
  157. }
  158. if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
  159. dev_err(arizona->dev, "PWM overclocked\n");
  160. if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
  161. dev_err(arizona->dev, "FX core overclocked\n");
  162. if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
  163. dev_err(arizona->dev, "DAC SYS overclocked\n");
  164. if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
  165. dev_err(arizona->dev, "DAC WARP overclocked\n");
  166. if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
  167. dev_err(arizona->dev, "ADC overclocked\n");
  168. if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
  169. dev_err(arizona->dev, "Mixer overclocked\n");
  170. if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
  171. dev_err(arizona->dev, "AIF3 overclocked\n");
  172. if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
  173. dev_err(arizona->dev, "AIF2 overclocked\n");
  174. if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
  175. dev_err(arizona->dev, "AIF1 overclocked\n");
  176. if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
  177. dev_err(arizona->dev, "Pad control overclocked\n");
  178. if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
  179. dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
  180. if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
  181. dev_err(arizona->dev, "Slimbus async overclocked\n");
  182. if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
  183. dev_err(arizona->dev, "Slimbus sync overclocked\n");
  184. if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
  185. dev_err(arizona->dev, "ASRC async system overclocked\n");
  186. if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
  187. dev_err(arizona->dev, "ASRC async WARP overclocked\n");
  188. if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
  189. dev_err(arizona->dev, "ASRC sync system overclocked\n");
  190. if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
  191. dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
  192. if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
  193. dev_err(arizona->dev, "DSP1 overclocked\n");
  194. if (val[1] & ARIZONA_ISRC3_OVERCLOCKED_STS)
  195. dev_err(arizona->dev, "ISRC3 overclocked\n");
  196. if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
  197. dev_err(arizona->dev, "ISRC2 overclocked\n");
  198. if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
  199. dev_err(arizona->dev, "ISRC1 overclocked\n");
  200. if (val[2] & ARIZONA_SPDIF_OVERCLOCKED_STS)
  201. dev_err(arizona->dev, "SPDIF overclocked\n");
  202. return IRQ_HANDLED;
  203. }
  204. static int arizona_poll_reg(struct arizona *arizona,
  205. int timeout, unsigned int reg,
  206. unsigned int mask, unsigned int target)
  207. {
  208. unsigned int val = 0;
  209. int ret, i;
  210. for (i = 0; i < timeout; i++) {
  211. ret = regmap_read(arizona->regmap, reg, &val);
  212. if (ret != 0) {
  213. dev_err(arizona->dev, "Failed to read reg %u: %d\n",
  214. reg, ret);
  215. continue;
  216. }
  217. if ((val & mask) == target)
  218. return 0;
  219. usleep_range(1000, 5000);
  220. }
  221. dev_err(arizona->dev, "Polling reg %u timed out: %x\n", reg, val);
  222. return -ETIMEDOUT;
  223. }
  224. static int arizona_wait_for_boot(struct arizona *arizona)
  225. {
  226. int ret;
  227. /*
  228. * We can't use an interrupt as we need to runtime resume to do so,
  229. * we won't race with the interrupt handler as it'll be blocked on
  230. * runtime resume.
  231. */
  232. ret = arizona_poll_reg(arizona, 5, ARIZONA_INTERRUPT_RAW_STATUS_5,
  233. ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
  234. if (!ret)
  235. regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
  236. ARIZONA_BOOT_DONE_STS);
  237. pm_runtime_mark_last_busy(arizona->dev);
  238. return ret;
  239. }
  240. static inline void arizona_enable_reset(struct arizona *arizona)
  241. {
  242. if (arizona->pdata.reset)
  243. gpio_set_value_cansleep(arizona->pdata.reset, 0);
  244. }
  245. static void arizona_disable_reset(struct arizona *arizona)
  246. {
  247. if (arizona->pdata.reset) {
  248. switch (arizona->type) {
  249. case WM5110:
  250. case WM8280:
  251. /* Meet requirements for minimum reset duration */
  252. usleep_range(5000, 10000);
  253. break;
  254. default:
  255. break;
  256. }
  257. gpio_set_value_cansleep(arizona->pdata.reset, 1);
  258. usleep_range(1000, 5000);
  259. }
  260. }
  261. struct arizona_sysclk_state {
  262. unsigned int fll;
  263. unsigned int sysclk;
  264. };
  265. static int arizona_enable_freerun_sysclk(struct arizona *arizona,
  266. struct arizona_sysclk_state *state)
  267. {
  268. int ret, err;
  269. /* Cache existing FLL and SYSCLK settings */
  270. ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &state->fll);
  271. if (ret) {
  272. dev_err(arizona->dev, "Failed to cache FLL settings: %d\n",
  273. ret);
  274. return ret;
  275. }
  276. ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1,
  277. &state->sysclk);
  278. if (ret) {
  279. dev_err(arizona->dev, "Failed to cache SYSCLK settings: %d\n",
  280. ret);
  281. return ret;
  282. }
  283. /* Start up SYSCLK using the FLL in free running mode */
  284. ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1,
  285. ARIZONA_FLL1_ENA | ARIZONA_FLL1_FREERUN);
  286. if (ret) {
  287. dev_err(arizona->dev,
  288. "Failed to start FLL in freerunning mode: %d\n",
  289. ret);
  290. return ret;
  291. }
  292. ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5,
  293. ARIZONA_FLL1_CLOCK_OK_STS,
  294. ARIZONA_FLL1_CLOCK_OK_STS);
  295. if (ret) {
  296. ret = -ETIMEDOUT;
  297. goto err_fll;
  298. }
  299. ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144);
  300. if (ret) {
  301. dev_err(arizona->dev, "Failed to start SYSCLK: %d\n", ret);
  302. goto err_fll;
  303. }
  304. return 0;
  305. err_fll:
  306. err = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, state->fll);
  307. if (err)
  308. dev_err(arizona->dev,
  309. "Failed to re-apply old FLL settings: %d\n", err);
  310. return ret;
  311. }
  312. static int arizona_disable_freerun_sysclk(struct arizona *arizona,
  313. struct arizona_sysclk_state *state)
  314. {
  315. int ret;
  316. ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1,
  317. state->sysclk);
  318. if (ret) {
  319. dev_err(arizona->dev,
  320. "Failed to re-apply old SYSCLK settings: %d\n", ret);
  321. return ret;
  322. }
  323. ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, state->fll);
  324. if (ret) {
  325. dev_err(arizona->dev,
  326. "Failed to re-apply old FLL settings: %d\n", ret);
  327. return ret;
  328. }
  329. return 0;
  330. }
  331. static int wm5102_apply_hardware_patch(struct arizona *arizona)
  332. {
  333. struct arizona_sysclk_state state;
  334. int err, ret;
  335. ret = arizona_enable_freerun_sysclk(arizona, &state);
  336. if (ret)
  337. return ret;
  338. /* Start the write sequencer and wait for it to finish */
  339. ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  340. ARIZONA_WSEQ_ENA | ARIZONA_WSEQ_START | 160);
  341. if (ret) {
  342. dev_err(arizona->dev, "Failed to start write sequencer: %d\n",
  343. ret);
  344. goto err;
  345. }
  346. ret = arizona_poll_reg(arizona, 5, ARIZONA_WRITE_SEQUENCER_CTRL_1,
  347. ARIZONA_WSEQ_BUSY, 0);
  348. if (ret) {
  349. regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  350. ARIZONA_WSEQ_ABORT);
  351. ret = -ETIMEDOUT;
  352. }
  353. err:
  354. err = arizona_disable_freerun_sysclk(arizona, &state);
  355. return ret ?: err;
  356. }
  357. /*
  358. * Register patch to some of the CODECs internal write sequences
  359. * to ensure a clean exit from the low power sleep state.
  360. */
  361. static const struct reg_sequence wm5110_sleep_patch[] = {
  362. { 0x337A, 0xC100 },
  363. { 0x337B, 0x0041 },
  364. { 0x3300, 0xA210 },
  365. { 0x3301, 0x050C },
  366. };
  367. static int wm5110_apply_sleep_patch(struct arizona *arizona)
  368. {
  369. struct arizona_sysclk_state state;
  370. int err, ret;
  371. ret = arizona_enable_freerun_sysclk(arizona, &state);
  372. if (ret)
  373. return ret;
  374. ret = regmap_multi_reg_write_bypassed(arizona->regmap,
  375. wm5110_sleep_patch,
  376. ARRAY_SIZE(wm5110_sleep_patch));
  377. err = arizona_disable_freerun_sysclk(arizona, &state);
  378. return ret ?: err;
  379. }
  380. static int wm5102_clear_write_sequencer(struct arizona *arizona)
  381. {
  382. int ret;
  383. ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_3,
  384. 0x0);
  385. if (ret) {
  386. dev_err(arizona->dev,
  387. "Failed to clear write sequencer state: %d\n", ret);
  388. return ret;
  389. }
  390. arizona_enable_reset(arizona);
  391. regulator_disable(arizona->dcvdd);
  392. msleep(20);
  393. ret = regulator_enable(arizona->dcvdd);
  394. if (ret) {
  395. dev_err(arizona->dev, "Failed to re-enable DCVDD: %d\n", ret);
  396. return ret;
  397. }
  398. arizona_disable_reset(arizona);
  399. return 0;
  400. }
  401. #ifdef CONFIG_PM
  402. static int arizona_isolate_dcvdd(struct arizona *arizona)
  403. {
  404. int ret;
  405. ret = regmap_update_bits(arizona->regmap,
  406. ARIZONA_ISOLATION_CONTROL,
  407. ARIZONA_ISOLATE_DCVDD1,
  408. ARIZONA_ISOLATE_DCVDD1);
  409. if (ret != 0)
  410. dev_err(arizona->dev, "Failed to isolate DCVDD: %d\n", ret);
  411. return ret;
  412. }
  413. static int arizona_connect_dcvdd(struct arizona *arizona)
  414. {
  415. int ret;
  416. ret = regmap_update_bits(arizona->regmap,
  417. ARIZONA_ISOLATION_CONTROL,
  418. ARIZONA_ISOLATE_DCVDD1, 0);
  419. if (ret != 0)
  420. dev_err(arizona->dev, "Failed to connect DCVDD: %d\n", ret);
  421. return ret;
  422. }
  423. static int arizona_is_jack_det_active(struct arizona *arizona)
  424. {
  425. unsigned int val;
  426. int ret;
  427. ret = regmap_read(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, &val);
  428. if (ret) {
  429. dev_err(arizona->dev,
  430. "Failed to check jack det status: %d\n", ret);
  431. return ret;
  432. } else if (val & ARIZONA_JD1_ENA) {
  433. return 1;
  434. } else {
  435. return 0;
  436. }
  437. }
  438. static int arizona_runtime_resume(struct device *dev)
  439. {
  440. struct arizona *arizona = dev_get_drvdata(dev);
  441. int ret;
  442. dev_dbg(arizona->dev, "Leaving AoD mode\n");
  443. if (arizona->has_fully_powered_off) {
  444. dev_dbg(arizona->dev, "Re-enabling core supplies\n");
  445. ret = regulator_bulk_enable(arizona->num_core_supplies,
  446. arizona->core_supplies);
  447. if (ret) {
  448. dev_err(dev, "Failed to enable core supplies: %d\n",
  449. ret);
  450. return ret;
  451. }
  452. }
  453. ret = regulator_enable(arizona->dcvdd);
  454. if (ret != 0) {
  455. dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
  456. if (arizona->has_fully_powered_off)
  457. regulator_bulk_disable(arizona->num_core_supplies,
  458. arizona->core_supplies);
  459. return ret;
  460. }
  461. if (arizona->has_fully_powered_off) {
  462. arizona_disable_reset(arizona);
  463. enable_irq(arizona->irq);
  464. arizona->has_fully_powered_off = false;
  465. }
  466. regcache_cache_only(arizona->regmap, false);
  467. switch (arizona->type) {
  468. case WM5102:
  469. if (arizona->external_dcvdd) {
  470. ret = arizona_connect_dcvdd(arizona);
  471. if (ret != 0)
  472. goto err;
  473. }
  474. ret = wm5102_patch(arizona);
  475. if (ret != 0) {
  476. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  477. ret);
  478. goto err;
  479. }
  480. ret = wm5102_apply_hardware_patch(arizona);
  481. if (ret) {
  482. dev_err(arizona->dev,
  483. "Failed to apply hardware patch: %d\n",
  484. ret);
  485. goto err;
  486. }
  487. break;
  488. case WM5110:
  489. case WM8280:
  490. ret = arizona_wait_for_boot(arizona);
  491. if (ret)
  492. goto err;
  493. if (arizona->external_dcvdd) {
  494. ret = arizona_connect_dcvdd(arizona);
  495. if (ret != 0)
  496. goto err;
  497. } else {
  498. /*
  499. * As this is only called for the internal regulator
  500. * (where we know voltage ranges available) it is ok
  501. * to request an exact range.
  502. */
  503. ret = regulator_set_voltage(arizona->dcvdd,
  504. 1200000, 1200000);
  505. if (ret < 0) {
  506. dev_err(arizona->dev,
  507. "Failed to set resume voltage: %d\n",
  508. ret);
  509. goto err;
  510. }
  511. }
  512. ret = wm5110_apply_sleep_patch(arizona);
  513. if (ret) {
  514. dev_err(arizona->dev,
  515. "Failed to re-apply sleep patch: %d\n",
  516. ret);
  517. goto err;
  518. }
  519. break;
  520. case WM1831:
  521. case CS47L24:
  522. ret = arizona_wait_for_boot(arizona);
  523. if (ret != 0)
  524. goto err;
  525. break;
  526. default:
  527. ret = arizona_wait_for_boot(arizona);
  528. if (ret != 0)
  529. goto err;
  530. if (arizona->external_dcvdd) {
  531. ret = arizona_connect_dcvdd(arizona);
  532. if (ret != 0)
  533. goto err;
  534. }
  535. break;
  536. }
  537. ret = regcache_sync(arizona->regmap);
  538. if (ret != 0) {
  539. dev_err(arizona->dev, "Failed to restore register cache\n");
  540. goto err;
  541. }
  542. return 0;
  543. err:
  544. regcache_cache_only(arizona->regmap, true);
  545. regulator_disable(arizona->dcvdd);
  546. return ret;
  547. }
  548. static int arizona_runtime_suspend(struct device *dev)
  549. {
  550. struct arizona *arizona = dev_get_drvdata(dev);
  551. int jd_active = 0;
  552. int ret;
  553. dev_dbg(arizona->dev, "Entering AoD mode\n");
  554. switch (arizona->type) {
  555. case WM5110:
  556. case WM8280:
  557. jd_active = arizona_is_jack_det_active(arizona);
  558. if (jd_active < 0)
  559. return jd_active;
  560. if (arizona->external_dcvdd) {
  561. ret = arizona_isolate_dcvdd(arizona);
  562. if (ret != 0)
  563. return ret;
  564. } else {
  565. /*
  566. * As this is only called for the internal regulator
  567. * (where we know voltage ranges available) it is ok
  568. * to request an exact range.
  569. */
  570. ret = regulator_set_voltage(arizona->dcvdd,
  571. 1175000, 1175000);
  572. if (ret < 0) {
  573. dev_err(arizona->dev,
  574. "Failed to set suspend voltage: %d\n",
  575. ret);
  576. return ret;
  577. }
  578. }
  579. break;
  580. case WM5102:
  581. jd_active = arizona_is_jack_det_active(arizona);
  582. if (jd_active < 0)
  583. return jd_active;
  584. if (arizona->external_dcvdd) {
  585. ret = arizona_isolate_dcvdd(arizona);
  586. if (ret != 0)
  587. return ret;
  588. }
  589. if (!jd_active) {
  590. ret = regmap_write(arizona->regmap,
  591. ARIZONA_WRITE_SEQUENCER_CTRL_3, 0x0);
  592. if (ret) {
  593. dev_err(arizona->dev,
  594. "Failed to clear write sequencer: %d\n",
  595. ret);
  596. return ret;
  597. }
  598. }
  599. break;
  600. case WM1831:
  601. case CS47L24:
  602. break;
  603. default:
  604. jd_active = arizona_is_jack_det_active(arizona);
  605. if (jd_active < 0)
  606. return jd_active;
  607. if (arizona->external_dcvdd) {
  608. ret = arizona_isolate_dcvdd(arizona);
  609. if (ret != 0)
  610. return ret;
  611. }
  612. break;
  613. }
  614. regcache_cache_only(arizona->regmap, true);
  615. regcache_mark_dirty(arizona->regmap);
  616. regulator_disable(arizona->dcvdd);
  617. /* Allow us to completely power down if no jack detection */
  618. if (!jd_active) {
  619. dev_dbg(arizona->dev, "Fully powering off\n");
  620. arizona->has_fully_powered_off = true;
  621. disable_irq_nosync(arizona->irq);
  622. arizona_enable_reset(arizona);
  623. regulator_bulk_disable(arizona->num_core_supplies,
  624. arizona->core_supplies);
  625. }
  626. return 0;
  627. }
  628. #endif
  629. #ifdef CONFIG_PM_SLEEP
  630. static int arizona_suspend(struct device *dev)
  631. {
  632. struct arizona *arizona = dev_get_drvdata(dev);
  633. dev_dbg(arizona->dev, "Suspend, disabling IRQ\n");
  634. disable_irq(arizona->irq);
  635. return 0;
  636. }
  637. static int arizona_suspend_noirq(struct device *dev)
  638. {
  639. struct arizona *arizona = dev_get_drvdata(dev);
  640. dev_dbg(arizona->dev, "Late suspend, reenabling IRQ\n");
  641. enable_irq(arizona->irq);
  642. return 0;
  643. }
  644. static int arizona_resume_noirq(struct device *dev)
  645. {
  646. struct arizona *arizona = dev_get_drvdata(dev);
  647. dev_dbg(arizona->dev, "Early resume, disabling IRQ\n");
  648. disable_irq(arizona->irq);
  649. return 0;
  650. }
  651. static int arizona_resume(struct device *dev)
  652. {
  653. struct arizona *arizona = dev_get_drvdata(dev);
  654. dev_dbg(arizona->dev, "Resume, reenabling IRQ\n");
  655. enable_irq(arizona->irq);
  656. return 0;
  657. }
  658. #endif
  659. const struct dev_pm_ops arizona_pm_ops = {
  660. SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
  661. arizona_runtime_resume,
  662. NULL)
  663. SET_SYSTEM_SLEEP_PM_OPS(arizona_suspend, arizona_resume)
  664. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(arizona_suspend_noirq,
  665. arizona_resume_noirq)
  666. };
  667. EXPORT_SYMBOL_GPL(arizona_pm_ops);
  668. #ifdef CONFIG_OF
  669. unsigned long arizona_of_get_type(struct device *dev)
  670. {
  671. const struct of_device_id *id = of_match_device(arizona_of_match, dev);
  672. if (id)
  673. return (unsigned long)id->data;
  674. else
  675. return 0;
  676. }
  677. EXPORT_SYMBOL_GPL(arizona_of_get_type);
  678. static int arizona_of_get_core_pdata(struct arizona *arizona)
  679. {
  680. struct arizona_pdata *pdata = &arizona->pdata;
  681. struct property *prop;
  682. const __be32 *cur;
  683. u32 val;
  684. u32 pdm_val[ARIZONA_MAX_PDM_SPK];
  685. int ret, i;
  686. int count = 0;
  687. pdata->reset = of_get_named_gpio(arizona->dev->of_node, "wlf,reset", 0);
  688. if (pdata->reset == -EPROBE_DEFER) {
  689. return pdata->reset;
  690. } else if (pdata->reset < 0) {
  691. dev_err(arizona->dev, "Reset GPIO missing/malformed: %d\n",
  692. pdata->reset);
  693. pdata->reset = 0;
  694. }
  695. ret = of_property_read_u32_array(arizona->dev->of_node,
  696. "wlf,gpio-defaults",
  697. pdata->gpio_defaults,
  698. ARRAY_SIZE(pdata->gpio_defaults));
  699. if (ret >= 0) {
  700. /*
  701. * All values are literal except out of range values
  702. * which are chip default, translate into platform
  703. * data which uses 0 as chip default and out of range
  704. * as zero.
  705. */
  706. for (i = 0; i < ARRAY_SIZE(pdata->gpio_defaults); i++) {
  707. if (pdata->gpio_defaults[i] > 0xffff)
  708. pdata->gpio_defaults[i] = 0;
  709. else if (pdata->gpio_defaults[i] == 0)
  710. pdata->gpio_defaults[i] = 0x10000;
  711. }
  712. } else {
  713. dev_err(arizona->dev, "Failed to parse GPIO defaults: %d\n",
  714. ret);
  715. }
  716. of_property_for_each_u32(arizona->dev->of_node, "wlf,inmode", prop,
  717. cur, val) {
  718. if (count == ARRAY_SIZE(pdata->inmode))
  719. break;
  720. pdata->inmode[count] = val;
  721. count++;
  722. }
  723. count = 0;
  724. of_property_for_each_u32(arizona->dev->of_node, "wlf,dmic-ref", prop,
  725. cur, val) {
  726. if (count == ARRAY_SIZE(pdata->dmic_ref))
  727. break;
  728. pdata->dmic_ref[count] = val;
  729. count++;
  730. }
  731. count = 0;
  732. of_property_for_each_u32(arizona->dev->of_node, "wlf,out-mono", prop,
  733. cur, val) {
  734. if (count == ARRAY_SIZE(pdata->out_mono))
  735. break;
  736. pdata->out_mono[count] = !!val;
  737. count++;
  738. }
  739. count = 0;
  740. of_property_for_each_u32(arizona->dev->of_node,
  741. "wlf,max-channels-clocked",
  742. prop, cur, val) {
  743. if (count == ARRAY_SIZE(pdata->max_channels_clocked))
  744. break;
  745. pdata->max_channels_clocked[count] = val;
  746. count++;
  747. }
  748. ret = of_property_read_u32_array(arizona->dev->of_node,
  749. "wlf,spk-fmt",
  750. pdm_val,
  751. ARRAY_SIZE(pdm_val));
  752. if (ret >= 0)
  753. for (count = 0; count < ARRAY_SIZE(pdata->spk_fmt); ++count)
  754. pdata->spk_fmt[count] = pdm_val[count];
  755. ret = of_property_read_u32_array(arizona->dev->of_node,
  756. "wlf,spk-mute",
  757. pdm_val,
  758. ARRAY_SIZE(pdm_val));
  759. if (ret >= 0)
  760. for (count = 0; count < ARRAY_SIZE(pdata->spk_mute); ++count)
  761. pdata->spk_mute[count] = pdm_val[count];
  762. return 0;
  763. }
  764. const struct of_device_id arizona_of_match[] = {
  765. { .compatible = "wlf,wm5102", .data = (void *)WM5102 },
  766. { .compatible = "wlf,wm5110", .data = (void *)WM5110 },
  767. { .compatible = "wlf,wm8280", .data = (void *)WM8280 },
  768. { .compatible = "wlf,wm8997", .data = (void *)WM8997 },
  769. { .compatible = "wlf,wm8998", .data = (void *)WM8998 },
  770. { .compatible = "wlf,wm1814", .data = (void *)WM1814 },
  771. { .compatible = "wlf,wm1831", .data = (void *)WM1831 },
  772. { .compatible = "cirrus,cs47l24", .data = (void *)CS47L24 },
  773. {},
  774. };
  775. EXPORT_SYMBOL_GPL(arizona_of_match);
  776. #else
  777. static inline int arizona_of_get_core_pdata(struct arizona *arizona)
  778. {
  779. return 0;
  780. }
  781. #endif
  782. static const struct mfd_cell early_devs[] = {
  783. { .name = "arizona-ldo1" },
  784. };
  785. static const char * const wm5102_supplies[] = {
  786. "MICVDD",
  787. "DBVDD2",
  788. "DBVDD3",
  789. "CPVDD",
  790. "SPKVDDL",
  791. "SPKVDDR",
  792. };
  793. static const struct mfd_cell wm5102_devs[] = {
  794. { .name = "arizona-micsupp" },
  795. { .name = "arizona-gpio" },
  796. {
  797. .name = "arizona-extcon",
  798. .parent_supplies = wm5102_supplies,
  799. .num_parent_supplies = 1, /* We only need MICVDD */
  800. },
  801. { .name = "arizona-haptics" },
  802. { .name = "arizona-pwm" },
  803. {
  804. .name = "wm5102-codec",
  805. .parent_supplies = wm5102_supplies,
  806. .num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
  807. },
  808. };
  809. static const struct mfd_cell wm5110_devs[] = {
  810. { .name = "arizona-micsupp" },
  811. { .name = "arizona-gpio" },
  812. {
  813. .name = "arizona-extcon",
  814. .parent_supplies = wm5102_supplies,
  815. .num_parent_supplies = 1, /* We only need MICVDD */
  816. },
  817. { .name = "arizona-haptics" },
  818. { .name = "arizona-pwm" },
  819. {
  820. .name = "wm5110-codec",
  821. .parent_supplies = wm5102_supplies,
  822. .num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
  823. },
  824. };
  825. static const char * const cs47l24_supplies[] = {
  826. "MICVDD",
  827. "CPVDD",
  828. "SPKVDD",
  829. };
  830. static const struct mfd_cell cs47l24_devs[] = {
  831. { .name = "arizona-gpio" },
  832. { .name = "arizona-haptics" },
  833. { .name = "arizona-pwm" },
  834. {
  835. .name = "cs47l24-codec",
  836. .parent_supplies = cs47l24_supplies,
  837. .num_parent_supplies = ARRAY_SIZE(cs47l24_supplies),
  838. },
  839. };
  840. static const char * const wm8997_supplies[] = {
  841. "MICVDD",
  842. "DBVDD2",
  843. "CPVDD",
  844. "SPKVDD",
  845. };
  846. static const struct mfd_cell wm8997_devs[] = {
  847. { .name = "arizona-micsupp" },
  848. { .name = "arizona-gpio" },
  849. {
  850. .name = "arizona-extcon",
  851. .parent_supplies = wm8997_supplies,
  852. .num_parent_supplies = 1, /* We only need MICVDD */
  853. },
  854. { .name = "arizona-haptics" },
  855. { .name = "arizona-pwm" },
  856. {
  857. .name = "wm8997-codec",
  858. .parent_supplies = wm8997_supplies,
  859. .num_parent_supplies = ARRAY_SIZE(wm8997_supplies),
  860. },
  861. };
  862. static const struct mfd_cell wm8998_devs[] = {
  863. { .name = "arizona-micsupp" },
  864. { .name = "arizona-gpio" },
  865. {
  866. .name = "arizona-extcon",
  867. .parent_supplies = wm5102_supplies,
  868. .num_parent_supplies = 1, /* We only need MICVDD */
  869. },
  870. { .name = "arizona-haptics" },
  871. { .name = "arizona-pwm" },
  872. {
  873. .name = "wm8998-codec",
  874. .parent_supplies = wm5102_supplies,
  875. .num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
  876. },
  877. };
  878. int arizona_dev_init(struct arizona *arizona)
  879. {
  880. const char * const mclk_name[] = { "mclk1", "mclk2" };
  881. struct device *dev = arizona->dev;
  882. const char *type_name = NULL;
  883. unsigned int reg, val, mask;
  884. int (*apply_patch)(struct arizona *) = NULL;
  885. const struct mfd_cell *subdevs = NULL;
  886. int n_subdevs = 0, ret, i;
  887. dev_set_drvdata(arizona->dev, arizona);
  888. mutex_init(&arizona->clk_lock);
  889. if (dev_get_platdata(arizona->dev)) {
  890. memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
  891. sizeof(arizona->pdata));
  892. } else {
  893. ret = arizona_of_get_core_pdata(arizona);
  894. if (ret < 0)
  895. return ret;
  896. }
  897. BUILD_BUG_ON(ARRAY_SIZE(arizona->mclk) != ARRAY_SIZE(mclk_name));
  898. for (i = 0; i < ARRAY_SIZE(arizona->mclk); i++) {
  899. arizona->mclk[i] = devm_clk_get(arizona->dev, mclk_name[i]);
  900. if (IS_ERR(arizona->mclk[i])) {
  901. dev_info(arizona->dev, "Failed to get %s: %ld\n",
  902. mclk_name[i], PTR_ERR(arizona->mclk[i]));
  903. arizona->mclk[i] = NULL;
  904. }
  905. }
  906. regcache_cache_only(arizona->regmap, true);
  907. switch (arizona->type) {
  908. case WM5102:
  909. case WM5110:
  910. case WM8280:
  911. case WM8997:
  912. case WM8998:
  913. case WM1814:
  914. case WM1831:
  915. case CS47L24:
  916. for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
  917. arizona->core_supplies[i].supply
  918. = wm5102_core_supplies[i];
  919. arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
  920. break;
  921. default:
  922. dev_err(arizona->dev, "Unknown device type %d\n",
  923. arizona->type);
  924. return -ENODEV;
  925. }
  926. /* Mark DCVDD as external, LDO1 driver will clear if internal */
  927. arizona->external_dcvdd = true;
  928. switch (arizona->type) {
  929. case WM1831:
  930. case CS47L24:
  931. break; /* No LDO1 regulator */
  932. default:
  933. ret = mfd_add_devices(arizona->dev, -1, early_devs,
  934. ARRAY_SIZE(early_devs), NULL, 0, NULL);
  935. if (ret != 0) {
  936. dev_err(dev, "Failed to add early children: %d\n", ret);
  937. return ret;
  938. }
  939. break;
  940. }
  941. ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
  942. arizona->core_supplies);
  943. if (ret != 0) {
  944. dev_err(dev, "Failed to request core supplies: %d\n",
  945. ret);
  946. goto err_early;
  947. }
  948. /**
  949. * Don't use devres here because the only device we have to get
  950. * against is the MFD device and DCVDD will likely be supplied by
  951. * one of its children. Meaning that the regulator will be
  952. * destroyed by the time devres calls regulator put.
  953. */
  954. arizona->dcvdd = regulator_get(arizona->dev, "DCVDD");
  955. if (IS_ERR(arizona->dcvdd)) {
  956. ret = PTR_ERR(arizona->dcvdd);
  957. dev_err(dev, "Failed to request DCVDD: %d\n", ret);
  958. goto err_early;
  959. }
  960. if (arizona->pdata.reset) {
  961. /* Start out with /RESET low to put the chip into reset */
  962. ret = devm_gpio_request_one(arizona->dev, arizona->pdata.reset,
  963. GPIOF_DIR_OUT | GPIOF_INIT_LOW,
  964. "arizona /RESET");
  965. if (ret != 0) {
  966. dev_err(dev, "Failed to request /RESET: %d\n", ret);
  967. goto err_dcvdd;
  968. }
  969. }
  970. ret = regulator_bulk_enable(arizona->num_core_supplies,
  971. arizona->core_supplies);
  972. if (ret != 0) {
  973. dev_err(dev, "Failed to enable core supplies: %d\n",
  974. ret);
  975. goto err_dcvdd;
  976. }
  977. ret = regulator_enable(arizona->dcvdd);
  978. if (ret != 0) {
  979. dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
  980. goto err_enable;
  981. }
  982. arizona_disable_reset(arizona);
  983. regcache_cache_only(arizona->regmap, false);
  984. /* Verify that this is a chip we know about */
  985. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  986. if (ret != 0) {
  987. dev_err(dev, "Failed to read ID register: %d\n", ret);
  988. goto err_reset;
  989. }
  990. switch (reg) {
  991. case 0x5102:
  992. case 0x5110:
  993. case 0x6349:
  994. case 0x6363:
  995. case 0x8997:
  996. break;
  997. default:
  998. dev_err(arizona->dev, "Unknown device ID: %x\n", reg);
  999. ret = -ENODEV;
  1000. goto err_reset;
  1001. }
  1002. /* If we have a /RESET GPIO we'll already be reset */
  1003. if (!arizona->pdata.reset) {
  1004. ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
  1005. if (ret != 0) {
  1006. dev_err(dev, "Failed to reset device: %d\n", ret);
  1007. goto err_reset;
  1008. }
  1009. usleep_range(1000, 5000);
  1010. }
  1011. /* Ensure device startup is complete */
  1012. switch (arizona->type) {
  1013. case WM5102:
  1014. ret = regmap_read(arizona->regmap,
  1015. ARIZONA_WRITE_SEQUENCER_CTRL_3, &val);
  1016. if (ret) {
  1017. dev_err(dev,
  1018. "Failed to check write sequencer state: %d\n",
  1019. ret);
  1020. } else if (val & 0x01) {
  1021. ret = wm5102_clear_write_sequencer(arizona);
  1022. if (ret)
  1023. return ret;
  1024. }
  1025. break;
  1026. default:
  1027. break;
  1028. }
  1029. ret = arizona_wait_for_boot(arizona);
  1030. if (ret) {
  1031. dev_err(arizona->dev, "Device failed initial boot: %d\n", ret);
  1032. goto err_reset;
  1033. }
  1034. /* Read the device ID information & do device specific stuff */
  1035. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  1036. if (ret != 0) {
  1037. dev_err(dev, "Failed to read ID register: %d\n", ret);
  1038. goto err_reset;
  1039. }
  1040. ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
  1041. &arizona->rev);
  1042. if (ret != 0) {
  1043. dev_err(dev, "Failed to read revision register: %d\n", ret);
  1044. goto err_reset;
  1045. }
  1046. arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
  1047. switch (reg) {
  1048. case 0x5102:
  1049. if (IS_ENABLED(CONFIG_MFD_WM5102)) {
  1050. type_name = "WM5102";
  1051. if (arizona->type != WM5102) {
  1052. dev_warn(arizona->dev,
  1053. "WM5102 registered as %d\n",
  1054. arizona->type);
  1055. arizona->type = WM5102;
  1056. }
  1057. apply_patch = wm5102_patch;
  1058. arizona->rev &= 0x7;
  1059. subdevs = wm5102_devs;
  1060. n_subdevs = ARRAY_SIZE(wm5102_devs);
  1061. }
  1062. break;
  1063. case 0x5110:
  1064. if (IS_ENABLED(CONFIG_MFD_WM5110)) {
  1065. switch (arizona->type) {
  1066. case WM5110:
  1067. type_name = "WM5110";
  1068. break;
  1069. case WM8280:
  1070. type_name = "WM8280";
  1071. break;
  1072. default:
  1073. type_name = "WM5110";
  1074. dev_warn(arizona->dev,
  1075. "WM5110 registered as %d\n",
  1076. arizona->type);
  1077. arizona->type = WM5110;
  1078. break;
  1079. }
  1080. apply_patch = wm5110_patch;
  1081. subdevs = wm5110_devs;
  1082. n_subdevs = ARRAY_SIZE(wm5110_devs);
  1083. }
  1084. break;
  1085. case 0x6363:
  1086. if (IS_ENABLED(CONFIG_MFD_CS47L24)) {
  1087. switch (arizona->type) {
  1088. case CS47L24:
  1089. type_name = "CS47L24";
  1090. break;
  1091. case WM1831:
  1092. type_name = "WM1831";
  1093. break;
  1094. default:
  1095. dev_warn(arizona->dev,
  1096. "CS47L24 registered as %d\n",
  1097. arizona->type);
  1098. arizona->type = CS47L24;
  1099. break;
  1100. }
  1101. apply_patch = cs47l24_patch;
  1102. subdevs = cs47l24_devs;
  1103. n_subdevs = ARRAY_SIZE(cs47l24_devs);
  1104. }
  1105. break;
  1106. case 0x8997:
  1107. if (IS_ENABLED(CONFIG_MFD_WM8997)) {
  1108. type_name = "WM8997";
  1109. if (arizona->type != WM8997) {
  1110. dev_warn(arizona->dev,
  1111. "WM8997 registered as %d\n",
  1112. arizona->type);
  1113. arizona->type = WM8997;
  1114. }
  1115. apply_patch = wm8997_patch;
  1116. subdevs = wm8997_devs;
  1117. n_subdevs = ARRAY_SIZE(wm8997_devs);
  1118. }
  1119. break;
  1120. case 0x6349:
  1121. if (IS_ENABLED(CONFIG_MFD_WM8998)) {
  1122. switch (arizona->type) {
  1123. case WM8998:
  1124. type_name = "WM8998";
  1125. break;
  1126. case WM1814:
  1127. type_name = "WM1814";
  1128. break;
  1129. default:
  1130. type_name = "WM8998";
  1131. dev_warn(arizona->dev,
  1132. "WM8998 registered as %d\n",
  1133. arizona->type);
  1134. arizona->type = WM8998;
  1135. }
  1136. apply_patch = wm8998_patch;
  1137. subdevs = wm8998_devs;
  1138. n_subdevs = ARRAY_SIZE(wm8998_devs);
  1139. }
  1140. break;
  1141. default:
  1142. dev_err(arizona->dev, "Unknown device ID %x\n", reg);
  1143. ret = -ENODEV;
  1144. goto err_reset;
  1145. }
  1146. if (!subdevs) {
  1147. dev_err(arizona->dev,
  1148. "No kernel support for device ID %x\n", reg);
  1149. ret = -ENODEV;
  1150. goto err_reset;
  1151. }
  1152. dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
  1153. if (apply_patch) {
  1154. ret = apply_patch(arizona);
  1155. if (ret != 0) {
  1156. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  1157. ret);
  1158. goto err_reset;
  1159. }
  1160. switch (arizona->type) {
  1161. case WM5102:
  1162. ret = wm5102_apply_hardware_patch(arizona);
  1163. if (ret) {
  1164. dev_err(arizona->dev,
  1165. "Failed to apply hardware patch: %d\n",
  1166. ret);
  1167. goto err_reset;
  1168. }
  1169. break;
  1170. case WM5110:
  1171. case WM8280:
  1172. ret = wm5110_apply_sleep_patch(arizona);
  1173. if (ret) {
  1174. dev_err(arizona->dev,
  1175. "Failed to apply sleep patch: %d\n",
  1176. ret);
  1177. goto err_reset;
  1178. }
  1179. break;
  1180. default:
  1181. break;
  1182. }
  1183. }
  1184. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  1185. if (!arizona->pdata.gpio_defaults[i])
  1186. continue;
  1187. regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
  1188. arizona->pdata.gpio_defaults[i]);
  1189. }
  1190. /* Chip default */
  1191. if (!arizona->pdata.clk32k_src)
  1192. arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
  1193. switch (arizona->pdata.clk32k_src) {
  1194. case ARIZONA_32KZ_MCLK1:
  1195. case ARIZONA_32KZ_MCLK2:
  1196. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  1197. ARIZONA_CLK_32K_SRC_MASK,
  1198. arizona->pdata.clk32k_src - 1);
  1199. arizona_clk32k_enable(arizona);
  1200. break;
  1201. case ARIZONA_32KZ_NONE:
  1202. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  1203. ARIZONA_CLK_32K_SRC_MASK, 2);
  1204. break;
  1205. default:
  1206. dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
  1207. arizona->pdata.clk32k_src);
  1208. ret = -EINVAL;
  1209. goto err_reset;
  1210. }
  1211. for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
  1212. if (!arizona->pdata.micbias[i].mV &&
  1213. !arizona->pdata.micbias[i].bypass)
  1214. continue;
  1215. /* Apply default for bypass mode */
  1216. if (!arizona->pdata.micbias[i].mV)
  1217. arizona->pdata.micbias[i].mV = 2800;
  1218. val = (arizona->pdata.micbias[i].mV - 1500) / 100;
  1219. val <<= ARIZONA_MICB1_LVL_SHIFT;
  1220. if (arizona->pdata.micbias[i].ext_cap)
  1221. val |= ARIZONA_MICB1_EXT_CAP;
  1222. if (arizona->pdata.micbias[i].discharge)
  1223. val |= ARIZONA_MICB1_DISCH;
  1224. if (arizona->pdata.micbias[i].soft_start)
  1225. val |= ARIZONA_MICB1_RATE;
  1226. if (arizona->pdata.micbias[i].bypass)
  1227. val |= ARIZONA_MICB1_BYPASS;
  1228. regmap_update_bits(arizona->regmap,
  1229. ARIZONA_MIC_BIAS_CTRL_1 + i,
  1230. ARIZONA_MICB1_LVL_MASK |
  1231. ARIZONA_MICB1_EXT_CAP |
  1232. ARIZONA_MICB1_DISCH |
  1233. ARIZONA_MICB1_BYPASS |
  1234. ARIZONA_MICB1_RATE, val);
  1235. }
  1236. for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
  1237. /* Default for both is 0 so noop with defaults */
  1238. val = arizona->pdata.dmic_ref[i]
  1239. << ARIZONA_IN1_DMIC_SUP_SHIFT;
  1240. if (arizona->pdata.inmode[i] & ARIZONA_INMODE_DMIC)
  1241. val |= 1 << ARIZONA_IN1_MODE_SHIFT;
  1242. switch (arizona->type) {
  1243. case WM8998:
  1244. case WM1814:
  1245. regmap_update_bits(arizona->regmap,
  1246. ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 8),
  1247. ARIZONA_IN1L_SRC_SE_MASK,
  1248. (arizona->pdata.inmode[i] & ARIZONA_INMODE_SE)
  1249. << ARIZONA_IN1L_SRC_SE_SHIFT);
  1250. regmap_update_bits(arizona->regmap,
  1251. ARIZONA_ADC_DIGITAL_VOLUME_1R + (i * 8),
  1252. ARIZONA_IN1R_SRC_SE_MASK,
  1253. (arizona->pdata.inmode[i] & ARIZONA_INMODE_SE)
  1254. << ARIZONA_IN1R_SRC_SE_SHIFT);
  1255. mask = ARIZONA_IN1_DMIC_SUP_MASK |
  1256. ARIZONA_IN1_MODE_MASK;
  1257. break;
  1258. default:
  1259. if (arizona->pdata.inmode[i] & ARIZONA_INMODE_SE)
  1260. val |= 1 << ARIZONA_IN1_SINGLE_ENDED_SHIFT;
  1261. mask = ARIZONA_IN1_DMIC_SUP_MASK |
  1262. ARIZONA_IN1_MODE_MASK |
  1263. ARIZONA_IN1_SINGLE_ENDED_MASK;
  1264. break;
  1265. }
  1266. regmap_update_bits(arizona->regmap,
  1267. ARIZONA_IN1L_CONTROL + (i * 8),
  1268. mask, val);
  1269. }
  1270. for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
  1271. /* Default is 0 so noop with defaults */
  1272. if (arizona->pdata.out_mono[i])
  1273. val = ARIZONA_OUT1_MONO;
  1274. else
  1275. val = 0;
  1276. regmap_update_bits(arizona->regmap,
  1277. ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
  1278. ARIZONA_OUT1_MONO, val);
  1279. }
  1280. for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
  1281. if (arizona->pdata.spk_mute[i])
  1282. regmap_update_bits(arizona->regmap,
  1283. ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
  1284. ARIZONA_SPK1_MUTE_ENDIAN_MASK |
  1285. ARIZONA_SPK1_MUTE_SEQ1_MASK,
  1286. arizona->pdata.spk_mute[i]);
  1287. if (arizona->pdata.spk_fmt[i])
  1288. regmap_update_bits(arizona->regmap,
  1289. ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
  1290. ARIZONA_SPK1_FMT_MASK,
  1291. arizona->pdata.spk_fmt[i]);
  1292. }
  1293. pm_runtime_set_active(arizona->dev);
  1294. pm_runtime_enable(arizona->dev);
  1295. /* Set up for interrupts */
  1296. ret = arizona_irq_init(arizona);
  1297. if (ret != 0)
  1298. goto err_pm;
  1299. pm_runtime_set_autosuspend_delay(arizona->dev, 100);
  1300. pm_runtime_use_autosuspend(arizona->dev);
  1301. arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
  1302. arizona_clkgen_err, arizona);
  1303. arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
  1304. arizona_overclocked, arizona);
  1305. arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
  1306. arizona_underclocked, arizona);
  1307. ret = mfd_add_devices(arizona->dev, PLATFORM_DEVID_NONE,
  1308. subdevs, n_subdevs, NULL, 0, NULL);
  1309. if (ret) {
  1310. dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
  1311. goto err_irq;
  1312. }
  1313. return 0;
  1314. err_irq:
  1315. arizona_irq_exit(arizona);
  1316. err_pm:
  1317. pm_runtime_disable(arizona->dev);
  1318. err_reset:
  1319. arizona_enable_reset(arizona);
  1320. regulator_disable(arizona->dcvdd);
  1321. err_enable:
  1322. regulator_bulk_disable(arizona->num_core_supplies,
  1323. arizona->core_supplies);
  1324. err_dcvdd:
  1325. regulator_put(arizona->dcvdd);
  1326. err_early:
  1327. mfd_remove_devices(dev);
  1328. return ret;
  1329. }
  1330. EXPORT_SYMBOL_GPL(arizona_dev_init);
  1331. int arizona_dev_exit(struct arizona *arizona)
  1332. {
  1333. pm_runtime_disable(arizona->dev);
  1334. regulator_disable(arizona->dcvdd);
  1335. regulator_put(arizona->dcvdd);
  1336. mfd_remove_devices(arizona->dev);
  1337. arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
  1338. arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
  1339. arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
  1340. arizona_irq_exit(arizona);
  1341. arizona_enable_reset(arizona);
  1342. regulator_bulk_disable(arizona->num_core_supplies,
  1343. arizona->core_supplies);
  1344. return 0;
  1345. }
  1346. EXPORT_SYMBOL_GPL(arizona_dev_exit);