intel-lpss-pci.c 8.1 KB

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  1. /*
  2. * Intel LPSS PCI support.
  3. *
  4. * Copyright (C) 2015, Intel Corporation
  5. *
  6. * Authors: Andy Shevchenko <[email protected]>
  7. * Mika Westerberg <[email protected]>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/ioport.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/pci.h>
  17. #include <linux/pm.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/property.h>
  20. #include "intel-lpss.h"
  21. static int intel_lpss_pci_probe(struct pci_dev *pdev,
  22. const struct pci_device_id *id)
  23. {
  24. struct intel_lpss_platform_info *info;
  25. int ret;
  26. ret = pcim_enable_device(pdev);
  27. if (ret)
  28. return ret;
  29. info = devm_kmemdup(&pdev->dev, (void *)id->driver_data, sizeof(*info),
  30. GFP_KERNEL);
  31. if (!info)
  32. return -ENOMEM;
  33. info->mem = &pdev->resource[0];
  34. info->irq = pdev->irq;
  35. pdev->d3cold_delay = 0;
  36. /* Probably it is enough to set this for iDMA capable devices only */
  37. pci_set_master(pdev);
  38. ret = intel_lpss_probe(&pdev->dev, info);
  39. if (ret)
  40. return ret;
  41. pm_runtime_put(&pdev->dev);
  42. pm_runtime_allow(&pdev->dev);
  43. return 0;
  44. }
  45. static void intel_lpss_pci_remove(struct pci_dev *pdev)
  46. {
  47. pm_runtime_forbid(&pdev->dev);
  48. pm_runtime_get_sync(&pdev->dev);
  49. intel_lpss_remove(&pdev->dev);
  50. }
  51. static INTEL_LPSS_PM_OPS(intel_lpss_pci_pm_ops);
  52. static const struct intel_lpss_platform_info spt_info = {
  53. .clk_rate = 120000000,
  54. };
  55. static struct property_entry spt_i2c_properties[] = {
  56. PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 230),
  57. { },
  58. };
  59. static const struct intel_lpss_platform_info spt_i2c_info = {
  60. .clk_rate = 120000000,
  61. .properties = spt_i2c_properties,
  62. };
  63. static struct property_entry uart_properties[] = {
  64. PROPERTY_ENTRY_U32("reg-io-width", 4),
  65. PROPERTY_ENTRY_U32("reg-shift", 2),
  66. PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
  67. { },
  68. };
  69. static const struct intel_lpss_platform_info spt_uart_info = {
  70. .clk_rate = 120000000,
  71. .clk_con_id = "baudclk",
  72. .properties = uart_properties,
  73. };
  74. static const struct intel_lpss_platform_info bxt_info = {
  75. .clk_rate = 100000000,
  76. };
  77. static const struct intel_lpss_platform_info bxt_uart_info = {
  78. .clk_rate = 100000000,
  79. .clk_con_id = "baudclk",
  80. .properties = uart_properties,
  81. };
  82. static struct property_entry bxt_i2c_properties[] = {
  83. PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 42),
  84. PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
  85. PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 208),
  86. { },
  87. };
  88. static const struct intel_lpss_platform_info bxt_i2c_info = {
  89. .clk_rate = 133000000,
  90. .properties = bxt_i2c_properties,
  91. };
  92. static struct property_entry apl_i2c_properties[] = {
  93. PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 207),
  94. PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
  95. PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 208),
  96. { },
  97. };
  98. static const struct intel_lpss_platform_info apl_i2c_info = {
  99. .clk_rate = 133000000,
  100. .properties = apl_i2c_properties,
  101. };
  102. static const struct pci_device_id intel_lpss_pci_ids[] = {
  103. /* BXT A-Step */
  104. { PCI_VDEVICE(INTEL, 0x0aac), (kernel_ulong_t)&bxt_i2c_info },
  105. { PCI_VDEVICE(INTEL, 0x0aae), (kernel_ulong_t)&bxt_i2c_info },
  106. { PCI_VDEVICE(INTEL, 0x0ab0), (kernel_ulong_t)&bxt_i2c_info },
  107. { PCI_VDEVICE(INTEL, 0x0ab2), (kernel_ulong_t)&bxt_i2c_info },
  108. { PCI_VDEVICE(INTEL, 0x0ab4), (kernel_ulong_t)&bxt_i2c_info },
  109. { PCI_VDEVICE(INTEL, 0x0ab6), (kernel_ulong_t)&bxt_i2c_info },
  110. { PCI_VDEVICE(INTEL, 0x0ab8), (kernel_ulong_t)&bxt_i2c_info },
  111. { PCI_VDEVICE(INTEL, 0x0aba), (kernel_ulong_t)&bxt_i2c_info },
  112. { PCI_VDEVICE(INTEL, 0x0abc), (kernel_ulong_t)&bxt_uart_info },
  113. { PCI_VDEVICE(INTEL, 0x0abe), (kernel_ulong_t)&bxt_uart_info },
  114. { PCI_VDEVICE(INTEL, 0x0ac0), (kernel_ulong_t)&bxt_uart_info },
  115. { PCI_VDEVICE(INTEL, 0x0ac2), (kernel_ulong_t)&bxt_info },
  116. { PCI_VDEVICE(INTEL, 0x0ac4), (kernel_ulong_t)&bxt_info },
  117. { PCI_VDEVICE(INTEL, 0x0ac6), (kernel_ulong_t)&bxt_info },
  118. { PCI_VDEVICE(INTEL, 0x0aee), (kernel_ulong_t)&bxt_uart_info },
  119. /* BXT B-Step */
  120. { PCI_VDEVICE(INTEL, 0x1aac), (kernel_ulong_t)&bxt_i2c_info },
  121. { PCI_VDEVICE(INTEL, 0x1aae), (kernel_ulong_t)&bxt_i2c_info },
  122. { PCI_VDEVICE(INTEL, 0x1ab0), (kernel_ulong_t)&bxt_i2c_info },
  123. { PCI_VDEVICE(INTEL, 0x1ab2), (kernel_ulong_t)&bxt_i2c_info },
  124. { PCI_VDEVICE(INTEL, 0x1ab4), (kernel_ulong_t)&bxt_i2c_info },
  125. { PCI_VDEVICE(INTEL, 0x1ab6), (kernel_ulong_t)&bxt_i2c_info },
  126. { PCI_VDEVICE(INTEL, 0x1ab8), (kernel_ulong_t)&bxt_i2c_info },
  127. { PCI_VDEVICE(INTEL, 0x1aba), (kernel_ulong_t)&bxt_i2c_info },
  128. { PCI_VDEVICE(INTEL, 0x1abc), (kernel_ulong_t)&bxt_uart_info },
  129. { PCI_VDEVICE(INTEL, 0x1abe), (kernel_ulong_t)&bxt_uart_info },
  130. { PCI_VDEVICE(INTEL, 0x1ac0), (kernel_ulong_t)&bxt_uart_info },
  131. { PCI_VDEVICE(INTEL, 0x1ac2), (kernel_ulong_t)&bxt_info },
  132. { PCI_VDEVICE(INTEL, 0x1ac4), (kernel_ulong_t)&bxt_info },
  133. { PCI_VDEVICE(INTEL, 0x1ac6), (kernel_ulong_t)&bxt_info },
  134. { PCI_VDEVICE(INTEL, 0x1aee), (kernel_ulong_t)&bxt_uart_info },
  135. /* APL */
  136. { PCI_VDEVICE(INTEL, 0x5aac), (kernel_ulong_t)&apl_i2c_info },
  137. { PCI_VDEVICE(INTEL, 0x5aae), (kernel_ulong_t)&apl_i2c_info },
  138. { PCI_VDEVICE(INTEL, 0x5ab0), (kernel_ulong_t)&apl_i2c_info },
  139. { PCI_VDEVICE(INTEL, 0x5ab2), (kernel_ulong_t)&apl_i2c_info },
  140. { PCI_VDEVICE(INTEL, 0x5ab4), (kernel_ulong_t)&apl_i2c_info },
  141. { PCI_VDEVICE(INTEL, 0x5ab6), (kernel_ulong_t)&apl_i2c_info },
  142. { PCI_VDEVICE(INTEL, 0x5ab8), (kernel_ulong_t)&apl_i2c_info },
  143. { PCI_VDEVICE(INTEL, 0x5aba), (kernel_ulong_t)&apl_i2c_info },
  144. { PCI_VDEVICE(INTEL, 0x5abc), (kernel_ulong_t)&bxt_uart_info },
  145. { PCI_VDEVICE(INTEL, 0x5abe), (kernel_ulong_t)&bxt_uart_info },
  146. { PCI_VDEVICE(INTEL, 0x5ac0), (kernel_ulong_t)&bxt_uart_info },
  147. { PCI_VDEVICE(INTEL, 0x5ac2), (kernel_ulong_t)&bxt_info },
  148. { PCI_VDEVICE(INTEL, 0x5ac4), (kernel_ulong_t)&bxt_info },
  149. { PCI_VDEVICE(INTEL, 0x5ac6), (kernel_ulong_t)&bxt_info },
  150. { PCI_VDEVICE(INTEL, 0x5aee), (kernel_ulong_t)&bxt_uart_info },
  151. /* SPT-LP */
  152. { PCI_VDEVICE(INTEL, 0x9d27), (kernel_ulong_t)&spt_uart_info },
  153. { PCI_VDEVICE(INTEL, 0x9d28), (kernel_ulong_t)&spt_uart_info },
  154. { PCI_VDEVICE(INTEL, 0x9d29), (kernel_ulong_t)&spt_info },
  155. { PCI_VDEVICE(INTEL, 0x9d2a), (kernel_ulong_t)&spt_info },
  156. { PCI_VDEVICE(INTEL, 0x9d60), (kernel_ulong_t)&spt_i2c_info },
  157. { PCI_VDEVICE(INTEL, 0x9d61), (kernel_ulong_t)&spt_i2c_info },
  158. { PCI_VDEVICE(INTEL, 0x9d62), (kernel_ulong_t)&spt_i2c_info },
  159. { PCI_VDEVICE(INTEL, 0x9d63), (kernel_ulong_t)&spt_i2c_info },
  160. { PCI_VDEVICE(INTEL, 0x9d64), (kernel_ulong_t)&spt_i2c_info },
  161. { PCI_VDEVICE(INTEL, 0x9d65), (kernel_ulong_t)&spt_i2c_info },
  162. { PCI_VDEVICE(INTEL, 0x9d66), (kernel_ulong_t)&spt_uart_info },
  163. /* SPT-H */
  164. { PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info },
  165. { PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info },
  166. { PCI_VDEVICE(INTEL, 0xa129), (kernel_ulong_t)&spt_info },
  167. { PCI_VDEVICE(INTEL, 0xa12a), (kernel_ulong_t)&spt_info },
  168. { PCI_VDEVICE(INTEL, 0xa160), (kernel_ulong_t)&spt_i2c_info },
  169. { PCI_VDEVICE(INTEL, 0xa161), (kernel_ulong_t)&spt_i2c_info },
  170. { PCI_VDEVICE(INTEL, 0xa166), (kernel_ulong_t)&spt_uart_info },
  171. /* KBL-H */
  172. { PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&spt_uart_info },
  173. { PCI_VDEVICE(INTEL, 0xa2a8), (kernel_ulong_t)&spt_uart_info },
  174. { PCI_VDEVICE(INTEL, 0xa2a9), (kernel_ulong_t)&spt_info },
  175. { PCI_VDEVICE(INTEL, 0xa2aa), (kernel_ulong_t)&spt_info },
  176. { PCI_VDEVICE(INTEL, 0xa2e0), (kernel_ulong_t)&spt_i2c_info },
  177. { PCI_VDEVICE(INTEL, 0xa2e1), (kernel_ulong_t)&spt_i2c_info },
  178. { PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&spt_i2c_info },
  179. { PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&spt_i2c_info },
  180. { PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&spt_uart_info },
  181. { }
  182. };
  183. MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids);
  184. static struct pci_driver intel_lpss_pci_driver = {
  185. .name = "intel-lpss",
  186. .id_table = intel_lpss_pci_ids,
  187. .probe = intel_lpss_pci_probe,
  188. .remove = intel_lpss_pci_remove,
  189. .driver = {
  190. .pm = &intel_lpss_pci_pm_ops,
  191. },
  192. };
  193. module_pci_driver(intel_lpss_pci_driver);
  194. MODULE_AUTHOR("Andy Shevchenko <[email protected]>");
  195. MODULE_AUTHOR("Mika Westerberg <[email protected]>");
  196. MODULE_DESCRIPTION("Intel LPSS PCI driver");
  197. MODULE_LICENSE("GPL v2");