qpnp-adc-tm.c 90 KB

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  1. /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. */
  13. #define pr_fmt(fmt) "%s: " fmt, __func__
  14. #include <linux/kernel.h>
  15. #include <linux/regmap.h>
  16. #include <linux/of.h>
  17. #include <linux/err.h>
  18. #include <linux/init.h>
  19. #include <linux/slab.h>
  20. #include <linux/delay.h>
  21. #include <linux/mutex.h>
  22. #include <linux/types.h>
  23. #include <linux/hwmon.h>
  24. #include <linux/module.h>
  25. #include <linux/debugfs.h>
  26. #include <linux/spmi.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/of_irq.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/completion.h>
  31. #include <linux/hwmon-sysfs.h>
  32. #include <linux/qpnp/qpnp-adc.h>
  33. #include <linux/thermal.h>
  34. #include <linux/platform_device.h>
  35. #include "thermal_core.h"
  36. /* QPNP VADC TM register definition */
  37. #define QPNP_REVISION3 0x2
  38. #define QPNP_PERPH_SUBTYPE 0x5
  39. #define QPNP_PERPH_TYPE2 0x2
  40. #define QPNP_REVISION_EIGHT_CHANNEL_SUPPORT 2
  41. #define QPNP_PERPH_SUBTYPE_TWO_CHANNEL_SUPPORT 0x22
  42. #define QPNP_STATUS1 0x8
  43. #define QPNP_STATUS1_OP_MODE 4
  44. #define QPNP_STATUS1_MEAS_INTERVAL_EN_STS BIT(2)
  45. #define QPNP_STATUS1_REQ_STS BIT(1)
  46. #define QPNP_STATUS1_EOC BIT(0)
  47. #define QPNP_STATUS2 0x9
  48. #define QPNP_STATUS2_CONV_SEQ_STATE 6
  49. #define QPNP_STATUS2_FIFO_NOT_EMPTY_FLAG BIT(1)
  50. #define QPNP_STATUS2_CONV_SEQ_TIMEOUT_STS BIT(0)
  51. #define QPNP_CONV_TIMEOUT_ERR 2
  52. #define QPNP_MODE_CTL 0x40
  53. #define QPNP_OP_MODE_SHIFT 3
  54. #define QPNP_VREF_XO_THM_FORCE BIT(2)
  55. #define QPNP_AMUX_TRIM_EN BIT(1)
  56. #define QPNP_ADC_TRIM_EN BIT(0)
  57. #define QPNP_EN_CTL1 0x46
  58. #define QPNP_ADC_TM_EN BIT(7)
  59. #define QPNP_BTM_CONV_REQ 0x47
  60. #define QPNP_ADC_CONV_REQ_EN BIT(7)
  61. #define QPNP_ADC_DIG_PARAM 0x50
  62. #define QPNP_ADC_DIG_DEC_RATIO_SEL_SHIFT 3
  63. #define QPNP_HW_SETTLE_DELAY 0x51
  64. #define QPNP_CONV_SEQ_CTL 0x54
  65. #define QPNP_CONV_SEQ_HOLDOFF_SHIFT 4
  66. #define QPNP_CONV_SEQ_TRIG_CTL 0x55
  67. #define QPNP_ADC_TM_MEAS_INTERVAL_CTL 0x57
  68. #define QPNP_ADC_TM_MEAS_INTERVAL_TIME_SHIFT 0x3
  69. #define QPNP_ADC_TM_MEAS_INTERVAL_CTL2 0x58
  70. #define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_SHIFT 0x4
  71. #define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_MASK 0xf0
  72. #define QPNP_ADC_TM_MEAS_INTERVAL_CTL3_MASK 0xf
  73. #define QPNP_ADC_MEAS_INTERVAL_OP_CTL 0x59
  74. #define QPNP_ADC_MEAS_INTERVAL_OP BIT(7)
  75. #define QPNP_OP_MODE_SHIFT 3
  76. #define QPNP_CONV_REQ 0x52
  77. #define QPNP_CONV_REQ_SET BIT(7)
  78. #define QPNP_FAST_AVG_CTL 0x5a
  79. #define QPNP_FAST_AVG_EN 0x5b
  80. #define QPNP_FAST_AVG_ENABLED BIT(7)
  81. #define QPNP_M0_LOW_THR_LSB 0x5c
  82. #define QPNP_M0_LOW_THR_MSB 0x5d
  83. #define QPNP_M0_HIGH_THR_LSB 0x5e
  84. #define QPNP_M0_HIGH_THR_MSB 0x5f
  85. #define QPNP_M1_ADC_CH_SEL_CTL 0x68
  86. #define QPNP_M1_LOW_THR_LSB 0x69
  87. #define QPNP_M1_LOW_THR_MSB 0x6a
  88. #define QPNP_M1_HIGH_THR_LSB 0x6b
  89. #define QPNP_M1_HIGH_THR_MSB 0x6c
  90. #define QPNP_M2_ADC_CH_SEL_CTL 0x70
  91. #define QPNP_M2_LOW_THR_LSB 0x71
  92. #define QPNP_M2_LOW_THR_MSB 0x72
  93. #define QPNP_M2_HIGH_THR_LSB 0x73
  94. #define QPNP_M2_HIGH_THR_MSB 0x74
  95. #define QPNP_M3_ADC_CH_SEL_CTL 0x78
  96. #define QPNP_M3_LOW_THR_LSB 0x79
  97. #define QPNP_M3_LOW_THR_MSB 0x7a
  98. #define QPNP_M3_HIGH_THR_LSB 0x7b
  99. #define QPNP_M3_HIGH_THR_MSB 0x7c
  100. #define QPNP_M4_ADC_CH_SEL_CTL 0x80
  101. #define QPNP_M4_LOW_THR_LSB 0x81
  102. #define QPNP_M4_LOW_THR_MSB 0x82
  103. #define QPNP_M4_HIGH_THR_LSB 0x83
  104. #define QPNP_M4_HIGH_THR_MSB 0x84
  105. #define QPNP_M5_ADC_CH_SEL_CTL 0x88
  106. #define QPNP_M5_LOW_THR_LSB 0x89
  107. #define QPNP_M5_LOW_THR_MSB 0x8a
  108. #define QPNP_M5_HIGH_THR_LSB 0x8b
  109. #define QPNP_M5_HIGH_THR_MSB 0x8c
  110. #define QPNP_M6_ADC_CH_SEL_CTL 0x90
  111. #define QPNP_M6_LOW_THR_LSB 0x91
  112. #define QPNP_M6_LOW_THR_MSB 0x92
  113. #define QPNP_M6_HIGH_THR_LSB 0x93
  114. #define QPNP_M6_HIGH_THR_MSB 0x94
  115. #define QPNP_M7_ADC_CH_SEL_CTL 0x98
  116. #define QPNP_M7_LOW_THR_LSB 0x99
  117. #define QPNP_M7_LOW_THR_MSB 0x9a
  118. #define QPNP_M7_HIGH_THR_LSB 0x9b
  119. #define QPNP_M7_HIGH_THR_MSB 0x9c
  120. #define QPNP_ADC_TM_MULTI_MEAS_EN 0x41
  121. #define QPNP_ADC_TM_MULTI_MEAS_EN_M0 BIT(0)
  122. #define QPNP_ADC_TM_MULTI_MEAS_EN_M1 BIT(1)
  123. #define QPNP_ADC_TM_MULTI_MEAS_EN_M2 BIT(2)
  124. #define QPNP_ADC_TM_MULTI_MEAS_EN_M3 BIT(3)
  125. #define QPNP_ADC_TM_MULTI_MEAS_EN_M4 BIT(4)
  126. #define QPNP_ADC_TM_MULTI_MEAS_EN_M5 BIT(5)
  127. #define QPNP_ADC_TM_MULTI_MEAS_EN_M6 BIT(6)
  128. #define QPNP_ADC_TM_MULTI_MEAS_EN_M7 BIT(7)
  129. #define QPNP_ADC_TM_LOW_THR_INT_EN 0x42
  130. #define QPNP_ADC_TM_LOW_THR_INT_EN_M0 BIT(0)
  131. #define QPNP_ADC_TM_LOW_THR_INT_EN_M1 BIT(1)
  132. #define QPNP_ADC_TM_LOW_THR_INT_EN_M2 BIT(2)
  133. #define QPNP_ADC_TM_LOW_THR_INT_EN_M3 BIT(3)
  134. #define QPNP_ADC_TM_LOW_THR_INT_EN_M4 BIT(4)
  135. #define QPNP_ADC_TM_LOW_THR_INT_EN_M5 BIT(5)
  136. #define QPNP_ADC_TM_LOW_THR_INT_EN_M6 BIT(6)
  137. #define QPNP_ADC_TM_LOW_THR_INT_EN_M7 BIT(7)
  138. #define QPNP_ADC_TM_HIGH_THR_INT_EN 0x43
  139. #define QPNP_ADC_TM_HIGH_THR_INT_EN_M0 BIT(0)
  140. #define QPNP_ADC_TM_HIGH_THR_INT_EN_M1 BIT(1)
  141. #define QPNP_ADC_TM_HIGH_THR_INT_EN_M2 BIT(2)
  142. #define QPNP_ADC_TM_HIGH_THR_INT_EN_M3 BIT(3)
  143. #define QPNP_ADC_TM_HIGH_THR_INT_EN_M4 BIT(4)
  144. #define QPNP_ADC_TM_HIGH_THR_INT_EN_M5 BIT(5)
  145. #define QPNP_ADC_TM_HIGH_THR_INT_EN_M6 BIT(6)
  146. #define QPNP_ADC_TM_HIGH_THR_INT_EN_M7 BIT(7)
  147. #define QPNP_ADC_TM_M0_MEAS_INTERVAL_CTL 0x59
  148. #define QPNP_ADC_TM_M1_MEAS_INTERVAL_CTL 0x6d
  149. #define QPNP_ADC_TM_M2_MEAS_INTERVAL_CTL 0x75
  150. #define QPNP_ADC_TM_M3_MEAS_INTERVAL_CTL 0x7d
  151. #define QPNP_ADC_TM_M4_MEAS_INTERVAL_CTL 0x85
  152. #define QPNP_ADC_TM_M5_MEAS_INTERVAL_CTL 0x8d
  153. #define QPNP_ADC_TM_M6_MEAS_INTERVAL_CTL 0x95
  154. #define QPNP_ADC_TM_M7_MEAS_INTERVAL_CTL 0x9d
  155. #define QPNP_ADC_TM_STATUS1 0x8
  156. #define QPNP_ADC_TM_STATUS_LOW 0xa
  157. #define QPNP_ADC_TM_STATUS_HIGH 0xb
  158. #define QPNP_ADC_TM_M0_LOW_THR 0x5d5c
  159. #define QPNP_ADC_TM_M0_HIGH_THR 0x5f5e
  160. #define QPNP_ADC_TM_MEAS_INTERVAL 0x0
  161. #define QPNP_ADC_TM_THR_LSB_MASK(val) (val & 0xff)
  162. #define QPNP_ADC_TM_THR_MSB_MASK(val) ((val & 0xff00) >> 8)
  163. #define QPNP_MIN_TIME 2000
  164. #define QPNP_MAX_TIME 2100
  165. #define QPNP_RETRY 1000
  166. /* QPNP ADC TM HC start */
  167. #define QPNP_BTM_HC_STATUS1 0x08
  168. #define QPNP_BTM_HC_STATUS_LOW 0x0a
  169. #define QPNP_BTM_HC_STATUS_HIGH 0x0b
  170. #define QPNP_BTM_HC_ADC_DIG_PARAM 0x42
  171. #define QPNP_BTM_HC_FAST_AVG_CTL 0x43
  172. #define QPNP_BTM_EN_CTL1 0x46
  173. #define QPNP_BTM_CONV_REQ 0x47
  174. #define QPNP_BTM_MEAS_INTERVAL_CTL 0x50
  175. #define QPNP_BTM_MEAS_INTERVAL_CTL2 0x51
  176. #define QPNP_BTM_MEAS_INTERVAL_CTL_PM5 0x44
  177. #define QPNP_BTM_MEAS_INTERVAL_CTL2_PM5 0x45
  178. #define QPNP_ADC_TM_MEAS_INTERVAL_TIME_SHIFT 0x3
  179. #define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_SHIFT 0x4
  180. #define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_MASK 0xf0
  181. #define QPNP_ADC_TM_MEAS_INTERVAL_CTL3_MASK 0xf
  182. #define QPNP_BTM_Mn_ADC_CH_SEL_CTL(n) ((n * 8) + 0x60)
  183. #define QPNP_BTM_Mn_LOW_THR0(n) ((n * 8) + 0x61)
  184. #define QPNP_BTM_Mn_LOW_THR1(n) ((n * 8) + 0x62)
  185. #define QPNP_BTM_Mn_HIGH_THR0(n) ((n * 8) + 0x63)
  186. #define QPNP_BTM_Mn_HIGH_THR1(n) ((n * 8) + 0x64)
  187. #define QPNP_BTM_Mn_MEAS_INTERVAL_CTL(n) ((n * 8) + 0x65)
  188. #define QPNP_BTM_Mn_CTL(n) ((n * 8) + 0x66)
  189. #define QPNP_BTM_CTL_HW_SETTLE_DELAY_MASK 0xf
  190. #define QPNP_BTM_CTL_CAL_SEL 0x30
  191. #define QPNP_BTM_CTL_CAL_SEL_MASK_SHIFT 4
  192. #define QPNP_BTM_CTL_CAL_VAL 0x40
  193. #define QPNP_BTM_Mn_EN(n) ((n * 8) + 0x67)
  194. #define QPNP_BTM_Mn_MEAS_EN BIT(7)
  195. #define QPNP_BTM_Mn_HIGH_THR_INT_EN BIT(1)
  196. #define QPNP_BTM_Mn_LOW_THR_INT_EN BIT(0)
  197. #define QPNP_BTM_Mn_DATA0(n) ((n * 2) + 0xa0)
  198. #define QPNP_BTM_Mn_DATA1(n) ((n * 2) + 0xa1)
  199. #define QPNP_BTM_CHANNELS 8
  200. #define QPNP_ADC_WAKEUP_SRC_TIMEOUT_MS 2000
  201. /* QPNP ADC TM HC end */
  202. struct qpnp_adc_thr_info {
  203. u8 status_low;
  204. u8 status_high;
  205. u8 qpnp_adc_tm_meas_en;
  206. u8 adc_tm_low_enable;
  207. u8 adc_tm_high_enable;
  208. u8 adc_tm_low_thr_set;
  209. u8 adc_tm_high_thr_set;
  210. spinlock_t adc_tm_low_lock;
  211. spinlock_t adc_tm_high_lock;
  212. };
  213. struct qpnp_adc_thr_client_info {
  214. struct list_head list;
  215. struct qpnp_adc_tm_btm_param *btm_param;
  216. int32_t low_thr_requested;
  217. int32_t high_thr_requested;
  218. enum qpnp_state_request state_requested;
  219. enum qpnp_state_request state_req_copy;
  220. bool low_thr_set;
  221. bool high_thr_set;
  222. bool notify_low_thr;
  223. bool notify_high_thr;
  224. };
  225. struct qpnp_adc_tm_sensor {
  226. struct thermal_zone_device *tz_dev;
  227. struct qpnp_adc_tm_chip *chip;
  228. enum thermal_device_mode mode;
  229. uint32_t sensor_num;
  230. enum qpnp_adc_meas_timer_select timer_select;
  231. uint32_t meas_interval;
  232. uint32_t low_thr;
  233. uint32_t high_thr;
  234. uint32_t btm_channel_num;
  235. uint32_t vadc_channel_num;
  236. struct workqueue_struct *req_wq;
  237. struct work_struct work;
  238. bool thermal_node;
  239. uint32_t scale_type;
  240. struct list_head thr_list;
  241. bool high_thr_triggered;
  242. bool low_thr_triggered;
  243. int emul_temperature;
  244. };
  245. struct qpnp_adc_tm_chip {
  246. struct device *dev;
  247. struct qpnp_adc_drv *adc;
  248. struct list_head list;
  249. bool adc_tm_initialized;
  250. bool adc_tm_recalib_check;
  251. int max_channels_available;
  252. struct qpnp_vadc_chip *vadc_dev;
  253. struct workqueue_struct *high_thr_wq;
  254. struct workqueue_struct *low_thr_wq;
  255. struct workqueue_struct *thr_wq;
  256. struct work_struct trigger_high_thr_work;
  257. struct work_struct trigger_low_thr_work;
  258. struct work_struct trigger_thr_work;
  259. bool adc_vote_enable;
  260. struct qpnp_adc_thr_info th_info;
  261. bool adc_tm_hc;
  262. struct qpnp_adc_tm_sensor sensor[0];
  263. };
  264. LIST_HEAD(qpnp_adc_tm_device_list);
  265. struct qpnp_adc_tm_trip_reg_type {
  266. enum qpnp_adc_tm_channel_select btm_amux_chan;
  267. uint16_t low_thr_lsb_addr;
  268. uint16_t low_thr_msb_addr;
  269. uint16_t high_thr_lsb_addr;
  270. uint16_t high_thr_msb_addr;
  271. u8 multi_meas_en;
  272. u8 low_thr_int_chan_en;
  273. u8 high_thr_int_chan_en;
  274. u8 meas_interval_ctl;
  275. };
  276. static struct qpnp_adc_tm_trip_reg_type adc_tm_data[] = {
  277. [QPNP_ADC_TM_CHAN0] = {QPNP_ADC_TM_M0_ADC_CH_SEL_CTL,
  278. QPNP_M0_LOW_THR_LSB,
  279. QPNP_M0_LOW_THR_MSB, QPNP_M0_HIGH_THR_LSB,
  280. QPNP_M0_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M0,
  281. QPNP_ADC_TM_LOW_THR_INT_EN_M0, QPNP_ADC_TM_HIGH_THR_INT_EN_M0,
  282. QPNP_ADC_TM_M0_MEAS_INTERVAL_CTL},
  283. [QPNP_ADC_TM_CHAN1] = {QPNP_ADC_TM_M1_ADC_CH_SEL_CTL,
  284. QPNP_M1_LOW_THR_LSB,
  285. QPNP_M1_LOW_THR_MSB, QPNP_M1_HIGH_THR_LSB,
  286. QPNP_M1_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M1,
  287. QPNP_ADC_TM_LOW_THR_INT_EN_M1, QPNP_ADC_TM_HIGH_THR_INT_EN_M1,
  288. QPNP_ADC_TM_M1_MEAS_INTERVAL_CTL},
  289. [QPNP_ADC_TM_CHAN2] = {QPNP_ADC_TM_M2_ADC_CH_SEL_CTL,
  290. QPNP_M2_LOW_THR_LSB,
  291. QPNP_M2_LOW_THR_MSB, QPNP_M2_HIGH_THR_LSB,
  292. QPNP_M2_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M2,
  293. QPNP_ADC_TM_LOW_THR_INT_EN_M2, QPNP_ADC_TM_HIGH_THR_INT_EN_M2,
  294. QPNP_ADC_TM_M2_MEAS_INTERVAL_CTL},
  295. [QPNP_ADC_TM_CHAN3] = {QPNP_ADC_TM_M3_ADC_CH_SEL_CTL,
  296. QPNP_M3_LOW_THR_LSB,
  297. QPNP_M3_LOW_THR_MSB, QPNP_M3_HIGH_THR_LSB,
  298. QPNP_M3_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M3,
  299. QPNP_ADC_TM_LOW_THR_INT_EN_M3, QPNP_ADC_TM_HIGH_THR_INT_EN_M3,
  300. QPNP_ADC_TM_M3_MEAS_INTERVAL_CTL},
  301. [QPNP_ADC_TM_CHAN4] = {QPNP_ADC_TM_M4_ADC_CH_SEL_CTL,
  302. QPNP_M4_LOW_THR_LSB,
  303. QPNP_M4_LOW_THR_MSB, QPNP_M4_HIGH_THR_LSB,
  304. QPNP_M4_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M4,
  305. QPNP_ADC_TM_LOW_THR_INT_EN_M4, QPNP_ADC_TM_HIGH_THR_INT_EN_M4,
  306. QPNP_ADC_TM_M4_MEAS_INTERVAL_CTL},
  307. [QPNP_ADC_TM_CHAN5] = {QPNP_ADC_TM_M5_ADC_CH_SEL_CTL,
  308. QPNP_M5_LOW_THR_LSB,
  309. QPNP_M5_LOW_THR_MSB, QPNP_M5_HIGH_THR_LSB,
  310. QPNP_M5_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M5,
  311. QPNP_ADC_TM_LOW_THR_INT_EN_M5, QPNP_ADC_TM_HIGH_THR_INT_EN_M5,
  312. QPNP_ADC_TM_M5_MEAS_INTERVAL_CTL},
  313. [QPNP_ADC_TM_CHAN6] = {QPNP_ADC_TM_M6_ADC_CH_SEL_CTL,
  314. QPNP_M6_LOW_THR_LSB,
  315. QPNP_M6_LOW_THR_MSB, QPNP_M6_HIGH_THR_LSB,
  316. QPNP_M6_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M6,
  317. QPNP_ADC_TM_LOW_THR_INT_EN_M6, QPNP_ADC_TM_HIGH_THR_INT_EN_M6,
  318. QPNP_ADC_TM_M6_MEAS_INTERVAL_CTL},
  319. [QPNP_ADC_TM_CHAN7] = {QPNP_ADC_TM_M7_ADC_CH_SEL_CTL,
  320. QPNP_M7_LOW_THR_LSB,
  321. QPNP_M7_LOW_THR_MSB, QPNP_M7_HIGH_THR_LSB,
  322. QPNP_M7_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M7,
  323. QPNP_ADC_TM_LOW_THR_INT_EN_M7, QPNP_ADC_TM_HIGH_THR_INT_EN_M7,
  324. QPNP_ADC_TM_M7_MEAS_INTERVAL_CTL},
  325. };
  326. static struct qpnp_adc_tm_reverse_scale_fn adc_tm_rscale_fn[] = {
  327. [SCALE_R_VBATT] = {qpnp_adc_vbatt_rscaler},
  328. [SCALE_RBATT_THERM] = {qpnp_adc_btm_scaler},
  329. [SCALE_R_USB_ID] = {qpnp_adc_usb_scaler},
  330. [SCALE_RPMIC_THERM] = {qpnp_adc_scale_millidegc_pmic_voltage_thr},
  331. [SCALE_R_SMB_BATT_THERM] = {qpnp_adc_smb_btm_rscaler},
  332. [SCALE_R_ABSOLUTE] = {qpnp_adc_absolute_rthr},
  333. [SCALE_QRD_SKUH_RBATT_THERM] = {qpnp_adc_qrd_skuh_btm_scaler},
  334. [SCALE_QRD_SKUT1_RBATT_THERM] = {qpnp_adc_qrd_skut1_btm_scaler},
  335. };
  336. static int32_t qpnp_adc_tm_read_reg(struct qpnp_adc_tm_chip *chip,
  337. int16_t reg, u8 *data, int len)
  338. {
  339. int rc = 0;
  340. rc = regmap_bulk_read(chip->adc->regmap, (chip->adc->offset + reg),
  341. data, len);
  342. if (rc < 0)
  343. pr_err("adc-tm read reg %d failed with %d\n", reg, rc);
  344. return rc;
  345. }
  346. static int32_t qpnp_adc_tm_write_reg(struct qpnp_adc_tm_chip *chip,
  347. int16_t reg, u8 data, int len)
  348. {
  349. int rc = 0;
  350. u8 *buf;
  351. buf = &data;
  352. rc = regmap_bulk_write(chip->adc->regmap, (chip->adc->offset + reg),
  353. buf, len);
  354. if (rc < 0)
  355. pr_err("adc-tm write reg %d failed with %d\n", reg, rc);
  356. return rc;
  357. }
  358. static int32_t qpnp_adc_tm_fast_avg_en(struct qpnp_adc_tm_chip *chip,
  359. uint32_t *fast_avg_sample)
  360. {
  361. int rc = 0, version = 0;
  362. u8 fast_avg_en = 0;
  363. version = qpnp_adc_get_revid_version(chip->dev);
  364. if (!((version == QPNP_REV_ID_8916_1_0) ||
  365. (version == QPNP_REV_ID_8916_1_1) ||
  366. (version == QPNP_REV_ID_8916_2_0))) {
  367. pr_debug("fast-avg-en not required for this version\n");
  368. return rc;
  369. }
  370. fast_avg_en = QPNP_FAST_AVG_ENABLED;
  371. rc = qpnp_adc_tm_write_reg(chip, QPNP_FAST_AVG_EN, fast_avg_en, 1);
  372. if (rc < 0) {
  373. pr_err("adc-tm fast-avg enable err\n");
  374. return rc;
  375. }
  376. if (*fast_avg_sample >= 3)
  377. *fast_avg_sample = 2;
  378. return rc;
  379. }
  380. static int qpnp_adc_tm_check_vreg_vote(struct qpnp_adc_tm_chip *chip)
  381. {
  382. int rc = 0;
  383. if (!chip->adc_vote_enable) {
  384. if (chip->adc->hkadc_ldo && chip->adc->hkadc_ldo_ok) {
  385. rc = qpnp_adc_enable_voltage(chip->adc);
  386. if (rc) {
  387. pr_err("failed enabling VADC LDO\n");
  388. return rc;
  389. }
  390. chip->adc_vote_enable = true;
  391. }
  392. }
  393. return rc;
  394. }
  395. static int32_t qpnp_adc_tm_enable(struct qpnp_adc_tm_chip *chip)
  396. {
  397. int rc = 0;
  398. u8 data = 0;
  399. rc = qpnp_adc_tm_check_vreg_vote(chip);
  400. if (rc) {
  401. pr_err("ADC TM VREG enable failed:%d\n", rc);
  402. return rc;
  403. }
  404. data = QPNP_ADC_TM_EN;
  405. rc = qpnp_adc_tm_write_reg(chip, QPNP_EN_CTL1, data, 1);
  406. if (rc < 0) {
  407. pr_err("adc-tm enable failed\n");
  408. return rc;
  409. }
  410. if (chip->adc_tm_hc) {
  411. data = QPNP_ADC_CONV_REQ_EN;
  412. rc = qpnp_adc_tm_write_reg(chip, QPNP_BTM_CONV_REQ, data, 1);
  413. if (rc < 0) {
  414. pr_err("adc-tm enable failed\n");
  415. return rc;
  416. }
  417. }
  418. return rc;
  419. }
  420. static int32_t qpnp_adc_tm_disable(struct qpnp_adc_tm_chip *chip)
  421. {
  422. u8 data = 0;
  423. int rc = 0;
  424. if (!chip->adc_tm_hc) {
  425. rc = qpnp_adc_tm_write_reg(chip, QPNP_EN_CTL1, data, 1);
  426. if (rc < 0) {
  427. pr_err("adc-tm disable failed\n");
  428. return rc;
  429. }
  430. }
  431. return rc;
  432. }
  433. static int qpnp_adc_tm_is_valid(struct qpnp_adc_tm_chip *chip)
  434. {
  435. struct qpnp_adc_tm_chip *adc_tm_chip = NULL;
  436. list_for_each_entry(adc_tm_chip, &qpnp_adc_tm_device_list, list)
  437. if (chip == adc_tm_chip)
  438. return 0;
  439. return -EINVAL;
  440. }
  441. static int32_t qpnp_adc_tm_rc_check_channel_en(struct qpnp_adc_tm_chip *chip)
  442. {
  443. u8 adc_tm_ctl = 0, status_low = 0, status_high = 0;
  444. int rc = 0, i = 0;
  445. bool ldo_en = false;
  446. for (i = 0; i < chip->max_channels_available; i++) {
  447. rc = qpnp_adc_tm_read_reg(chip, QPNP_BTM_Mn_CTL(i),
  448. &adc_tm_ctl, 1);
  449. if (rc) {
  450. pr_err("adc-tm-tm read ctl failed with %d\n", rc);
  451. return rc;
  452. }
  453. adc_tm_ctl &= QPNP_BTM_Mn_MEAS_EN;
  454. status_low = adc_tm_ctl & QPNP_BTM_Mn_LOW_THR_INT_EN;
  455. status_high = adc_tm_ctl & QPNP_BTM_Mn_HIGH_THR_INT_EN;
  456. /* Enable only if there are pending measurement requests */
  457. if ((adc_tm_ctl && status_high) ||
  458. (adc_tm_ctl && status_low)) {
  459. qpnp_adc_tm_enable(chip);
  460. ldo_en = true;
  461. /* Request conversion */
  462. rc = qpnp_adc_tm_write_reg(chip, QPNP_CONV_REQ,
  463. QPNP_CONV_REQ_SET, 1);
  464. if (rc < 0) {
  465. pr_err("adc-tm request conversion failed\n");
  466. return rc;
  467. }
  468. }
  469. break;
  470. }
  471. if (!ldo_en) {
  472. /* disable the vote if applicable */
  473. if (chip->adc_vote_enable && chip->adc->hkadc_ldo &&
  474. chip->adc->hkadc_ldo_ok) {
  475. qpnp_adc_disable_voltage(chip->adc);
  476. chip->adc_vote_enable = false;
  477. }
  478. }
  479. return rc;
  480. }
  481. static int32_t qpnp_adc_tm_enable_if_channel_meas(
  482. struct qpnp_adc_tm_chip *chip)
  483. {
  484. u8 adc_tm_meas_en = 0, status_low = 0, status_high = 0;
  485. int rc = 0;
  486. if (chip->adc_tm_hc) {
  487. rc = qpnp_adc_tm_rc_check_channel_en(chip);
  488. if (rc) {
  489. pr_err("adc_tm channel check failed\n");
  490. return rc;
  491. }
  492. } else {
  493. /* Check if a measurement request is still required */
  494. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
  495. &adc_tm_meas_en, 1);
  496. if (rc) {
  497. pr_err("read status high failed with %d\n", rc);
  498. return rc;
  499. }
  500. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_LOW_THR_INT_EN,
  501. &status_low, 1);
  502. if (rc) {
  503. pr_err("read status low failed with %d\n", rc);
  504. return rc;
  505. }
  506. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_HIGH_THR_INT_EN,
  507. &status_high, 1);
  508. if (rc) {
  509. pr_err("read status high failed with %d\n", rc);
  510. return rc;
  511. }
  512. /* Enable only if there are pending measurement requests */
  513. if ((adc_tm_meas_en && status_high) ||
  514. (adc_tm_meas_en && status_low)) {
  515. qpnp_adc_tm_enable(chip);
  516. /* Request conversion */
  517. rc = qpnp_adc_tm_write_reg(chip, QPNP_CONV_REQ,
  518. QPNP_CONV_REQ_SET, 1);
  519. if (rc < 0) {
  520. pr_err("adc-tm request conversion failed\n");
  521. return rc;
  522. }
  523. } else {
  524. /* disable the vote if applicable */
  525. if (chip->adc_vote_enable && chip->adc->hkadc_ldo &&
  526. chip->adc->hkadc_ldo_ok) {
  527. qpnp_adc_disable_voltage(chip->adc);
  528. chip->adc_vote_enable = false;
  529. }
  530. }
  531. }
  532. return rc;
  533. }
  534. static int32_t qpnp_adc_tm_mode_select(struct qpnp_adc_tm_chip *chip,
  535. u8 mode_ctl)
  536. {
  537. int rc;
  538. mode_ctl |= (QPNP_ADC_TRIM_EN | QPNP_AMUX_TRIM_EN);
  539. /* VADC_BTM current sets mode to recurring measurements */
  540. rc = qpnp_adc_tm_write_reg(chip, QPNP_MODE_CTL, mode_ctl, 1);
  541. if (rc < 0)
  542. pr_err("adc-tm write mode selection err\n");
  543. return rc;
  544. }
  545. static int32_t qpnp_adc_tm_req_sts_check(struct qpnp_adc_tm_chip *chip)
  546. {
  547. u8 status1 = 0, mode_ctl = 0;
  548. int rc, count = 0;
  549. /* Re-enable the peripheral */
  550. rc = qpnp_adc_tm_enable(chip);
  551. if (rc) {
  552. pr_err("adc-tm re-enable peripheral failed\n");
  553. return rc;
  554. }
  555. /* The VADC_TM bank needs to be disabled for new conversion request */
  556. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS1, &status1, 1);
  557. if (rc) {
  558. pr_err("adc-tm read status1 failed\n");
  559. return rc;
  560. }
  561. /* Disable the bank if a conversion is occurring */
  562. while (status1 & QPNP_STATUS1_REQ_STS) {
  563. if (count > QPNP_RETRY) {
  564. pr_err("retry error=%d with 0x%x\n", count, status1);
  565. break;
  566. }
  567. /*
  568. * Wait time is based on the optimum sampling rate
  569. * and adding enough time buffer to account for ADC conversions
  570. * occurring on different peripheral banks
  571. */
  572. usleep_range(QPNP_MIN_TIME, QPNP_MAX_TIME);
  573. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS1,
  574. &status1, 1);
  575. if (rc < 0) {
  576. pr_err("adc-tm disable failed\n");
  577. return rc;
  578. }
  579. count++;
  580. }
  581. if (!chip->adc_tm_hc) {
  582. /* Change the mode back to recurring measurement mode */
  583. mode_ctl = ADC_OP_MEASUREMENT_INTERVAL << QPNP_OP_MODE_SHIFT;
  584. rc = qpnp_adc_tm_mode_select(chip, mode_ctl);
  585. if (rc < 0) {
  586. pr_err("adc-tm mode change to recurring failed\n");
  587. return rc;
  588. }
  589. }
  590. /* Disable the peripheral */
  591. rc = qpnp_adc_tm_disable(chip);
  592. if (rc < 0) {
  593. pr_err("adc-tm peripheral disable failed\n");
  594. return rc;
  595. }
  596. return rc;
  597. }
  598. static int32_t qpnp_adc_tm_get_btm_idx(struct qpnp_adc_tm_chip *chip,
  599. uint32_t btm_chan, uint32_t *btm_chan_idx)
  600. {
  601. int rc = 0, i;
  602. bool chan_found = false;
  603. if (!chip->adc_tm_hc) {
  604. for (i = 0; i < QPNP_ADC_TM_CHAN_NONE; i++) {
  605. if (adc_tm_data[i].btm_amux_chan == btm_chan) {
  606. *btm_chan_idx = i;
  607. chan_found = true;
  608. }
  609. }
  610. } else {
  611. for (i = 0; i < chip->max_channels_available; i++) {
  612. if (chip->sensor[i].btm_channel_num == btm_chan) {
  613. *btm_chan_idx = i;
  614. chan_found = true;
  615. break;
  616. }
  617. }
  618. }
  619. if (!chan_found)
  620. return -EINVAL;
  621. return rc;
  622. }
  623. static int32_t qpnp_adc_tm_check_revision(struct qpnp_adc_tm_chip *chip,
  624. uint32_t btm_chan_num)
  625. {
  626. u8 rev, perph_subtype;
  627. int rc = 0;
  628. rc = qpnp_adc_tm_read_reg(chip, QPNP_REVISION3, &rev, 1);
  629. if (rc) {
  630. pr_err("adc-tm revision read failed\n");
  631. return rc;
  632. }
  633. rc = qpnp_adc_tm_read_reg(chip, QPNP_PERPH_SUBTYPE, &perph_subtype, 1);
  634. if (rc) {
  635. pr_err("adc-tm perph_subtype read failed\n");
  636. return rc;
  637. }
  638. if (perph_subtype == QPNP_PERPH_TYPE2) {
  639. if ((rev < QPNP_REVISION_EIGHT_CHANNEL_SUPPORT) &&
  640. (btm_chan_num > QPNP_ADC_TM_M4_ADC_CH_SEL_CTL)) {
  641. pr_debug("Version does not support more than 5 channels\n");
  642. return -EINVAL;
  643. }
  644. }
  645. if (perph_subtype == QPNP_PERPH_SUBTYPE_TWO_CHANNEL_SUPPORT) {
  646. if (btm_chan_num > QPNP_ADC_TM_M1_ADC_CH_SEL_CTL) {
  647. pr_debug("Version does not support more than 2 channels\n");
  648. return -EINVAL;
  649. }
  650. }
  651. return rc;
  652. }
  653. static int32_t qpnp_adc_tm_timer_interval_select(
  654. struct qpnp_adc_tm_chip *chip, uint32_t btm_chan,
  655. struct qpnp_vadc_chan_properties *chan_prop)
  656. {
  657. int rc, chan_idx = 0, i = 0;
  658. bool chan_found = false;
  659. u8 meas_interval_timer2 = 0, timer_interval_store = 0;
  660. uint32_t btm_chan_idx = 0;
  661. bool is_pmic_5 = chip->adc->adc_prop->is_pmic_5;
  662. while (i < chip->max_channels_available) {
  663. if (chip->sensor[i].btm_channel_num == btm_chan) {
  664. chan_idx = i;
  665. chan_found = true;
  666. i++;
  667. } else
  668. i++;
  669. }
  670. if (!chan_found) {
  671. pr_err("Channel not found\n");
  672. return -EINVAL;
  673. }
  674. switch (chip->sensor[chan_idx].timer_select) {
  675. case ADC_MEAS_TIMER_SELECT1:
  676. if (!chip->adc_tm_hc)
  677. rc = qpnp_adc_tm_write_reg(chip,
  678. QPNP_ADC_TM_MEAS_INTERVAL_CTL,
  679. chip->sensor[chan_idx].meas_interval, 1);
  680. else {
  681. if (!is_pmic_5)
  682. rc = qpnp_adc_tm_write_reg(chip,
  683. QPNP_BTM_MEAS_INTERVAL_CTL,
  684. chip->sensor[chan_idx].meas_interval,
  685. 1);
  686. else
  687. rc = qpnp_adc_tm_write_reg(chip,
  688. QPNP_BTM_MEAS_INTERVAL_CTL_PM5,
  689. chip->sensor[chan_idx].meas_interval,
  690. 1);
  691. }
  692. if (rc < 0) {
  693. pr_err("timer1 configure failed\n");
  694. return rc;
  695. }
  696. break;
  697. case ADC_MEAS_TIMER_SELECT2:
  698. /* Thermal channels uses timer2, default to 1 second */
  699. if (!chip->adc_tm_hc)
  700. rc = qpnp_adc_tm_read_reg(chip,
  701. QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
  702. &meas_interval_timer2, 1);
  703. else {
  704. if (!is_pmic_5)
  705. rc = qpnp_adc_tm_read_reg(chip,
  706. QPNP_BTM_MEAS_INTERVAL_CTL2,
  707. &meas_interval_timer2, 1);
  708. else
  709. rc = qpnp_adc_tm_read_reg(chip,
  710. QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
  711. &meas_interval_timer2, 1);
  712. }
  713. if (rc < 0) {
  714. pr_err("timer2 configure read failed\n");
  715. return rc;
  716. }
  717. timer_interval_store = chip->sensor[chan_idx].meas_interval;
  718. timer_interval_store <<= QPNP_ADC_TM_MEAS_INTERVAL_CTL2_SHIFT;
  719. timer_interval_store &= QPNP_ADC_TM_MEAS_INTERVAL_CTL2_MASK;
  720. meas_interval_timer2 |= timer_interval_store;
  721. if (!chip->adc_tm_hc)
  722. rc = qpnp_adc_tm_write_reg(chip,
  723. QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
  724. meas_interval_timer2, 1);
  725. else {
  726. if (!is_pmic_5)
  727. rc = qpnp_adc_tm_write_reg(chip,
  728. QPNP_BTM_MEAS_INTERVAL_CTL2,
  729. meas_interval_timer2, 1);
  730. else
  731. rc = qpnp_adc_tm_write_reg(chip,
  732. QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
  733. meas_interval_timer2, 1);
  734. }
  735. if (rc < 0) {
  736. pr_err("timer2 configure failed\n");
  737. return rc;
  738. }
  739. break;
  740. case ADC_MEAS_TIMER_SELECT3:
  741. if (!chip->adc_tm_hc)
  742. rc = qpnp_adc_tm_read_reg(chip,
  743. QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
  744. &meas_interval_timer2, 1);
  745. else {
  746. if (!is_pmic_5)
  747. rc = qpnp_adc_tm_read_reg(chip,
  748. QPNP_BTM_MEAS_INTERVAL_CTL2,
  749. &meas_interval_timer2, 1);
  750. else
  751. rc = qpnp_adc_tm_read_reg(chip,
  752. QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
  753. &meas_interval_timer2, 1);
  754. }
  755. if (rc < 0) {
  756. pr_err("timer3 read failed\n");
  757. return rc;
  758. }
  759. timer_interval_store = chip->sensor[chan_idx].meas_interval;
  760. timer_interval_store &= QPNP_ADC_TM_MEAS_INTERVAL_CTL3_MASK;
  761. meas_interval_timer2 |= timer_interval_store;
  762. if (!chip->adc_tm_hc)
  763. rc = qpnp_adc_tm_write_reg(chip,
  764. QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
  765. meas_interval_timer2, 1);
  766. else {
  767. if (!is_pmic_5)
  768. rc = qpnp_adc_tm_write_reg(chip,
  769. QPNP_BTM_MEAS_INTERVAL_CTL2,
  770. meas_interval_timer2, 1);
  771. else
  772. rc = qpnp_adc_tm_write_reg(chip,
  773. QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
  774. meas_interval_timer2, 1);
  775. }
  776. if (rc < 0) {
  777. pr_err("timer3 configure failed\n");
  778. return rc;
  779. }
  780. break;
  781. default:
  782. pr_err("Invalid timer selection\n");
  783. return -EINVAL;
  784. }
  785. /* Select the timer to use for the corresponding channel */
  786. rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan, &btm_chan_idx);
  787. if (rc < 0) {
  788. pr_err("Invalid btm channel idx\n");
  789. return rc;
  790. }
  791. if (!chip->adc_tm_hc)
  792. rc = qpnp_adc_tm_write_reg(chip,
  793. adc_tm_data[btm_chan_idx].meas_interval_ctl,
  794. chip->sensor[chan_idx].timer_select, 1);
  795. else
  796. rc = qpnp_adc_tm_write_reg(chip,
  797. QPNP_BTM_Mn_MEAS_INTERVAL_CTL(btm_chan_idx),
  798. chip->sensor[chan_idx].timer_select, 1);
  799. if (rc < 0) {
  800. pr_err("TM channel timer configure failed\n");
  801. return rc;
  802. }
  803. pr_debug("timer select:%d, timer_value_within_select:%d, channel:%x\n",
  804. chip->sensor[chan_idx].timer_select,
  805. chip->sensor[chan_idx].meas_interval,
  806. btm_chan);
  807. return rc;
  808. }
  809. static int32_t qpnp_adc_tm_add_to_list(struct qpnp_adc_tm_chip *chip,
  810. uint32_t dt_index,
  811. struct qpnp_adc_tm_btm_param *param,
  812. struct qpnp_vadc_chan_properties *chan_prop)
  813. {
  814. struct qpnp_adc_thr_client_info *client_info = NULL;
  815. bool client_info_exists = false;
  816. list_for_each_entry(client_info,
  817. &chip->sensor[dt_index].thr_list, list) {
  818. if (client_info->btm_param == param) {
  819. client_info->low_thr_requested = chan_prop->low_thr;
  820. client_info->high_thr_requested = chan_prop->high_thr;
  821. client_info->state_requested = param->state_request;
  822. client_info->state_req_copy = param->state_request;
  823. client_info->notify_low_thr = false;
  824. client_info->notify_high_thr = false;
  825. client_info_exists = true;
  826. pr_debug("client found\n");
  827. }
  828. }
  829. if (!client_info_exists) {
  830. client_info = devm_kzalloc(chip->dev,
  831. sizeof(struct qpnp_adc_thr_client_info), GFP_KERNEL);
  832. if (!client_info)
  833. return -ENOMEM;
  834. pr_debug("new client\n");
  835. client_info->btm_param = param;
  836. client_info->low_thr_requested = chan_prop->low_thr;
  837. client_info->high_thr_requested = chan_prop->high_thr;
  838. client_info->state_requested = param->state_request;
  839. client_info->state_req_copy = param->state_request;
  840. list_add_tail(&client_info->list,
  841. &chip->sensor[dt_index].thr_list);
  842. }
  843. return 0;
  844. }
  845. static int32_t qpnp_adc_tm_reg_update(struct qpnp_adc_tm_chip *chip,
  846. uint16_t addr, u8 mask, bool state)
  847. {
  848. u8 reg_value = 0;
  849. int rc = 0;
  850. rc = qpnp_adc_tm_read_reg(chip, addr, &reg_value, 1);
  851. if (rc < 0) {
  852. pr_err("read failed for addr:0x%x\n", addr);
  853. return rc;
  854. }
  855. reg_value = reg_value & ~mask;
  856. if (state)
  857. reg_value |= mask;
  858. pr_debug("state:%d, reg:0x%x with bits:0x%x and mask:0x%x\n",
  859. state, addr, reg_value, ~mask);
  860. rc = qpnp_adc_tm_write_reg(chip, addr, reg_value, 1);
  861. if (rc < 0) {
  862. pr_err("write failed for addr:%x\n", addr);
  863. return rc;
  864. }
  865. return rc;
  866. }
  867. static int32_t qpnp_adc_tm_read_thr_value(struct qpnp_adc_tm_chip *chip,
  868. uint32_t btm_chan)
  869. {
  870. int rc = 0;
  871. u8 data_lsb = 0, data_msb = 0;
  872. uint32_t btm_chan_idx = 0;
  873. int32_t low_thr = 0, high_thr = 0;
  874. if (!chip->adc_tm_hc) {
  875. pr_err("Not applicable for VADC HC peripheral\n");
  876. return -EINVAL;
  877. }
  878. rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan, &btm_chan_idx);
  879. if (rc < 0) {
  880. pr_err("Invalid btm channel idx\n");
  881. return rc;
  882. }
  883. rc = qpnp_adc_tm_read_reg(chip,
  884. adc_tm_data[btm_chan_idx].low_thr_lsb_addr,
  885. &data_lsb, 1);
  886. if (rc < 0) {
  887. pr_err("low threshold lsb setting failed\n");
  888. return rc;
  889. }
  890. rc = qpnp_adc_tm_read_reg(chip,
  891. adc_tm_data[btm_chan_idx].low_thr_msb_addr,
  892. &data_msb, 1);
  893. if (rc < 0) {
  894. pr_err("low threshold msb setting failed\n");
  895. return rc;
  896. }
  897. low_thr = (data_msb << 8) | data_lsb;
  898. rc = qpnp_adc_tm_read_reg(chip,
  899. adc_tm_data[btm_chan_idx].high_thr_lsb_addr,
  900. &data_lsb, 1);
  901. if (rc < 0) {
  902. pr_err("high threshold lsb setting failed\n");
  903. return rc;
  904. }
  905. rc = qpnp_adc_tm_read_reg(chip,
  906. adc_tm_data[btm_chan_idx].high_thr_msb_addr,
  907. &data_msb, 1);
  908. if (rc < 0) {
  909. pr_err("high threshold msb setting failed\n");
  910. return rc;
  911. }
  912. high_thr = (data_msb << 8) | data_lsb;
  913. pr_debug("configured thresholds high:0x%x and low:0x%x\n",
  914. high_thr, low_thr);
  915. return rc;
  916. }
  917. static int32_t qpnp_adc_tm_thr_update(struct qpnp_adc_tm_chip *chip,
  918. uint32_t btm_chan, int32_t high_thr, int32_t low_thr)
  919. {
  920. int rc = 0;
  921. uint32_t btm_chan_idx = 0;
  922. rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan, &btm_chan_idx);
  923. if (rc < 0) {
  924. pr_err("Invalid btm channel idx\n");
  925. return rc;
  926. }
  927. if (!chip->adc_tm_hc) {
  928. rc = qpnp_adc_tm_write_reg(chip,
  929. adc_tm_data[btm_chan_idx].low_thr_lsb_addr,
  930. QPNP_ADC_TM_THR_LSB_MASK(low_thr), 1);
  931. if (rc < 0) {
  932. pr_err("low threshold lsb setting failed\n");
  933. return rc;
  934. }
  935. rc = qpnp_adc_tm_write_reg(chip,
  936. adc_tm_data[btm_chan_idx].low_thr_msb_addr,
  937. QPNP_ADC_TM_THR_MSB_MASK(low_thr), 1);
  938. if (rc < 0) {
  939. pr_err("low threshold msb setting failed\n");
  940. return rc;
  941. }
  942. rc = qpnp_adc_tm_write_reg(chip,
  943. adc_tm_data[btm_chan_idx].high_thr_lsb_addr,
  944. QPNP_ADC_TM_THR_LSB_MASK(high_thr), 1);
  945. if (rc < 0) {
  946. pr_err("high threshold lsb setting failed\n");
  947. return rc;
  948. }
  949. rc = qpnp_adc_tm_write_reg(chip,
  950. adc_tm_data[btm_chan_idx].high_thr_msb_addr,
  951. QPNP_ADC_TM_THR_MSB_MASK(high_thr), 1);
  952. if (rc < 0)
  953. pr_err("high threshold msb setting failed\n");
  954. } else {
  955. rc = qpnp_adc_tm_write_reg(chip,
  956. QPNP_BTM_Mn_LOW_THR0(btm_chan_idx),
  957. QPNP_ADC_TM_THR_LSB_MASK(low_thr), 1);
  958. if (rc < 0) {
  959. pr_err("low threshold lsb setting failed\n");
  960. return rc;
  961. }
  962. rc = qpnp_adc_tm_write_reg(chip,
  963. QPNP_BTM_Mn_LOW_THR1(btm_chan_idx),
  964. QPNP_ADC_TM_THR_MSB_MASK(low_thr), 1);
  965. if (rc < 0) {
  966. pr_err("low threshold msb setting failed\n");
  967. return rc;
  968. }
  969. rc = qpnp_adc_tm_write_reg(chip,
  970. QPNP_BTM_Mn_HIGH_THR0(btm_chan_idx),
  971. QPNP_ADC_TM_THR_LSB_MASK(high_thr), 1);
  972. if (rc < 0) {
  973. pr_err("high threshold lsb setting failed\n");
  974. return rc;
  975. }
  976. rc = qpnp_adc_tm_write_reg(chip,
  977. QPNP_BTM_Mn_HIGH_THR1(btm_chan_idx),
  978. QPNP_ADC_TM_THR_MSB_MASK(high_thr), 1);
  979. if (rc < 0)
  980. pr_err("high threshold msb setting failed\n");
  981. }
  982. pr_debug("client requested high:%d and low:%d\n",
  983. high_thr, low_thr);
  984. return rc;
  985. }
  986. static int32_t qpnp_adc_tm_manage_thresholds(struct qpnp_adc_tm_chip *chip,
  987. uint32_t dt_index, uint32_t btm_chan)
  988. {
  989. struct qpnp_adc_thr_client_info *client_info = NULL;
  990. struct list_head *thr_list;
  991. int high_thr = 0, low_thr = 0, rc = 0;
  992. /*
  993. * high_thr/low_thr starting point and reset the high_thr_set and
  994. * low_thr_set back to reset since the thresholds will be
  995. * recomputed.
  996. */
  997. list_for_each(thr_list,
  998. &chip->sensor[dt_index].thr_list) {
  999. client_info = list_entry(thr_list,
  1000. struct qpnp_adc_thr_client_info, list);
  1001. high_thr = client_info->high_thr_requested;
  1002. low_thr = client_info->low_thr_requested;
  1003. client_info->high_thr_set = false;
  1004. client_info->low_thr_set = false;
  1005. }
  1006. pr_debug("init threshold is high:%d and low:%d\n", high_thr, low_thr);
  1007. /* Find the min of high_thr and max of low_thr */
  1008. list_for_each(thr_list,
  1009. &chip->sensor[dt_index].thr_list) {
  1010. client_info = list_entry(thr_list,
  1011. struct qpnp_adc_thr_client_info, list);
  1012. if ((client_info->state_req_copy == ADC_TM_HIGH_THR_ENABLE) ||
  1013. (client_info->state_req_copy ==
  1014. ADC_TM_HIGH_LOW_THR_ENABLE))
  1015. if (client_info->high_thr_requested < high_thr)
  1016. high_thr = client_info->high_thr_requested;
  1017. if ((client_info->state_req_copy == ADC_TM_LOW_THR_ENABLE) ||
  1018. (client_info->state_req_copy ==
  1019. ADC_TM_HIGH_LOW_THR_ENABLE))
  1020. if (client_info->low_thr_requested > low_thr)
  1021. low_thr = client_info->low_thr_requested;
  1022. pr_debug("threshold compared is high:%d and low:%d\n",
  1023. client_info->high_thr_requested,
  1024. client_info->low_thr_requested);
  1025. pr_debug("current threshold is high:%d and low:%d\n",
  1026. high_thr, low_thr);
  1027. }
  1028. /* Check which of the high_thr and low_thr got set */
  1029. list_for_each(thr_list,
  1030. &chip->sensor[dt_index].thr_list) {
  1031. client_info = list_entry(thr_list,
  1032. struct qpnp_adc_thr_client_info, list);
  1033. if ((client_info->state_req_copy == ADC_TM_HIGH_THR_ENABLE) ||
  1034. (client_info->state_req_copy ==
  1035. ADC_TM_HIGH_LOW_THR_ENABLE))
  1036. if (high_thr == client_info->high_thr_requested)
  1037. client_info->high_thr_set = true;
  1038. if ((client_info->state_req_copy == ADC_TM_LOW_THR_ENABLE) ||
  1039. (client_info->state_req_copy ==
  1040. ADC_TM_HIGH_LOW_THR_ENABLE))
  1041. if (low_thr == client_info->low_thr_requested)
  1042. client_info->low_thr_set = true;
  1043. }
  1044. rc = qpnp_adc_tm_thr_update(chip, btm_chan, high_thr, low_thr);
  1045. if (rc < 0)
  1046. pr_err("setting chan:%d threshold failed\n", btm_chan);
  1047. pr_debug("threshold written is high:%d and low:%d\n",
  1048. high_thr, low_thr);
  1049. return 0;
  1050. }
  1051. static int32_t qpnp_adc_tm_channel_configure(struct qpnp_adc_tm_chip *chip,
  1052. uint32_t btm_chan,
  1053. struct qpnp_vadc_chan_properties *chan_prop,
  1054. uint32_t amux_channel)
  1055. {
  1056. int rc = 0, i = 0, chan_idx = 0;
  1057. bool chan_found = false, high_thr_set = false, low_thr_set = false;
  1058. u8 sensor_mask = 0;
  1059. struct qpnp_adc_thr_client_info *client_info = NULL;
  1060. uint32_t btm_chan_idx = 0;
  1061. while (i < chip->max_channels_available) {
  1062. if (chip->sensor[i].btm_channel_num == btm_chan) {
  1063. chan_idx = i;
  1064. chan_found = true;
  1065. i++;
  1066. } else
  1067. i++;
  1068. }
  1069. if (!chan_found) {
  1070. pr_err("Channel not found\n");
  1071. return -EINVAL;
  1072. }
  1073. rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan, &btm_chan_idx);
  1074. if (rc < 0) {
  1075. pr_err("Invalid btm channel idx\n");
  1076. return rc;
  1077. }
  1078. sensor_mask = 1 << chan_idx;
  1079. if (!chip->sensor[chan_idx].thermal_node) {
  1080. /* Update low and high notification thresholds */
  1081. rc = qpnp_adc_tm_manage_thresholds(chip, chan_idx,
  1082. btm_chan);
  1083. if (rc < 0) {
  1084. pr_err("setting chan:%d threshold failed\n", btm_chan);
  1085. return rc;
  1086. }
  1087. list_for_each_entry(client_info,
  1088. &chip->sensor[chan_idx].thr_list, list) {
  1089. if (client_info->high_thr_set == true)
  1090. high_thr_set = true;
  1091. if (client_info->low_thr_set == true)
  1092. low_thr_set = true;
  1093. }
  1094. if (low_thr_set) {
  1095. pr_debug("low sensor mask:%x with state:%d\n",
  1096. sensor_mask, chan_prop->state_request);
  1097. /* Enable low threshold's interrupt */
  1098. if (!chip->adc_tm_hc)
  1099. rc = qpnp_adc_tm_reg_update(chip,
  1100. QPNP_ADC_TM_LOW_THR_INT_EN,
  1101. sensor_mask, true);
  1102. else
  1103. rc = qpnp_adc_tm_reg_update(chip,
  1104. QPNP_BTM_Mn_EN(btm_chan_idx),
  1105. QPNP_BTM_Mn_LOW_THR_INT_EN, true);
  1106. if (rc < 0) {
  1107. pr_err("low thr enable err:%d\n", btm_chan);
  1108. return rc;
  1109. }
  1110. }
  1111. if (high_thr_set) {
  1112. /* Enable high threshold's interrupt */
  1113. pr_debug("high sensor mask:%x\n", sensor_mask);
  1114. if (!chip->adc_tm_hc)
  1115. rc = qpnp_adc_tm_reg_update(chip,
  1116. QPNP_ADC_TM_HIGH_THR_INT_EN,
  1117. sensor_mask, true);
  1118. else
  1119. rc = qpnp_adc_tm_reg_update(chip,
  1120. QPNP_BTM_Mn_EN(btm_chan_idx),
  1121. QPNP_BTM_Mn_HIGH_THR_INT_EN, true);
  1122. if (rc < 0) {
  1123. pr_err("high thr enable err:%d\n", btm_chan);
  1124. return rc;
  1125. }
  1126. }
  1127. }
  1128. /* Enable corresponding BTM channel measurement */
  1129. if (!chip->adc_tm_hc)
  1130. rc = qpnp_adc_tm_reg_update(chip,
  1131. QPNP_ADC_TM_MULTI_MEAS_EN, sensor_mask, true);
  1132. else
  1133. rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_idx),
  1134. QPNP_BTM_Mn_MEAS_EN, true);
  1135. if (rc < 0) {
  1136. pr_err("multi measurement en failed\n");
  1137. return rc;
  1138. }
  1139. return rc;
  1140. }
  1141. static int32_t qpnp_adc_tm_hc_configure(struct qpnp_adc_tm_chip *chip,
  1142. struct qpnp_adc_amux_properties *chan_prop)
  1143. {
  1144. u8 decimation = 0, fast_avg_ctl = 0;
  1145. u8 buf[8];
  1146. int rc = 0;
  1147. uint32_t btm_chan = 0, cal_type = 0, btm_chan_idx = 0;
  1148. /* Disable bank */
  1149. rc = qpnp_adc_tm_disable(chip);
  1150. if (rc)
  1151. return rc;
  1152. /* Decimation setup */
  1153. decimation = chan_prop->decimation;
  1154. rc = qpnp_adc_tm_write_reg(chip, QPNP_BTM_HC_ADC_DIG_PARAM,
  1155. decimation, 1);
  1156. if (rc < 0) {
  1157. pr_err("adc-tm digital parameter setup err\n");
  1158. return rc;
  1159. }
  1160. /* Fast averaging setup/enable */
  1161. rc = qpnp_adc_tm_read_reg(chip, QPNP_BTM_HC_FAST_AVG_CTL,
  1162. &fast_avg_ctl, 1);
  1163. if (rc < 0) {
  1164. pr_err("adc-tm fast-avg enable read err\n");
  1165. return rc;
  1166. }
  1167. fast_avg_ctl |= chan_prop->fast_avg_setup;
  1168. rc = qpnp_adc_tm_write_reg(chip, QPNP_BTM_HC_FAST_AVG_CTL,
  1169. fast_avg_ctl, 1);
  1170. if (rc < 0) {
  1171. pr_err("adc-tm fast-avg enable write err\n");
  1172. return rc;
  1173. }
  1174. /* Read block registers for respective BTM channel */
  1175. btm_chan = chan_prop->chan_prop->tm_channel_select;
  1176. rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan, &btm_chan_idx);
  1177. if (rc < 0) {
  1178. pr_err("Invalid btm channel idx\n");
  1179. return rc;
  1180. }
  1181. rc = qpnp_adc_tm_read_reg(chip,
  1182. QPNP_BTM_Mn_ADC_CH_SEL_CTL(btm_chan_idx), buf, 8);
  1183. if (rc < 0) {
  1184. pr_err("qpnp adc configure block read failed\n");
  1185. return rc;
  1186. }
  1187. /* Update ADC channel sel */
  1188. rc = qpnp_adc_tm_write_reg(chip,
  1189. QPNP_BTM_Mn_ADC_CH_SEL_CTL(btm_chan_idx),
  1190. chan_prop->amux_channel, 1);
  1191. if (rc < 0) {
  1192. pr_err("adc-tm channel amux select failed\n");
  1193. return rc;
  1194. }
  1195. /* Manage thresholds */
  1196. rc = qpnp_adc_tm_channel_configure(chip, btm_chan,
  1197. chan_prop->chan_prop, chan_prop->amux_channel);
  1198. if (rc < 0) {
  1199. pr_err("adc-tm channel threshold configure failed\n");
  1200. return rc;
  1201. }
  1202. /* Measurement interval setup */
  1203. rc = qpnp_adc_tm_timer_interval_select(chip, btm_chan,
  1204. chan_prop->chan_prop);
  1205. if (rc < 0) {
  1206. pr_err("adc-tm timer select failed\n");
  1207. return rc;
  1208. }
  1209. /* Set calibration select, hw_settle delay */
  1210. cal_type |= (chan_prop->calib_type << QPNP_BTM_CTL_CAL_SEL_MASK_SHIFT);
  1211. buf[6] &= ~QPNP_BTM_CTL_HW_SETTLE_DELAY_MASK;
  1212. buf[6] |= chan_prop->hw_settle_time;
  1213. buf[6] &= ~QPNP_BTM_CTL_CAL_SEL;
  1214. buf[6] |= cal_type;
  1215. rc = qpnp_adc_tm_write_reg(chip, QPNP_BTM_Mn_CTL(btm_chan_idx),
  1216. buf[6], 1);
  1217. if (rc < 0) {
  1218. pr_err("adc-tm hw-settle, calib sel failed\n");
  1219. return rc;
  1220. }
  1221. /* Enable bank */
  1222. rc = qpnp_adc_tm_enable(chip);
  1223. if (rc)
  1224. return rc;
  1225. /* Request conversion */
  1226. rc = qpnp_adc_tm_write_reg(chip, QPNP_CONV_REQ, QPNP_CONV_REQ_SET, 1);
  1227. if (rc < 0) {
  1228. pr_err("adc-tm request conversion failed\n");
  1229. return rc;
  1230. }
  1231. return 0;
  1232. }
  1233. static int32_t qpnp_adc_tm_configure(struct qpnp_adc_tm_chip *chip,
  1234. struct qpnp_adc_amux_properties *chan_prop)
  1235. {
  1236. u8 decimation = 0, op_cntrl = 0, mode_ctl = 0;
  1237. int rc = 0;
  1238. uint32_t btm_chan = 0;
  1239. /* Set measurement in single measurement mode */
  1240. mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
  1241. rc = qpnp_adc_tm_mode_select(chip, mode_ctl);
  1242. if (rc < 0) {
  1243. pr_err("adc-tm single mode select failed\n");
  1244. return rc;
  1245. }
  1246. /* Disable bank */
  1247. rc = qpnp_adc_tm_disable(chip);
  1248. if (rc)
  1249. return rc;
  1250. /* Check if a conversion is in progress */
  1251. rc = qpnp_adc_tm_req_sts_check(chip);
  1252. if (rc < 0) {
  1253. pr_err("adc-tm req_sts check failed\n");
  1254. return rc;
  1255. }
  1256. /* Configure AMUX channel select for the corresponding BTM channel*/
  1257. btm_chan = chan_prop->chan_prop->tm_channel_select;
  1258. rc = qpnp_adc_tm_write_reg(chip, btm_chan, chan_prop->amux_channel, 1);
  1259. if (rc < 0) {
  1260. pr_err("adc-tm channel selection err\n");
  1261. return rc;
  1262. }
  1263. /* Digital parameter setup */
  1264. decimation |= chan_prop->decimation <<
  1265. QPNP_ADC_DIG_DEC_RATIO_SEL_SHIFT;
  1266. rc = qpnp_adc_tm_write_reg(chip, QPNP_ADC_DIG_PARAM, decimation, 1);
  1267. if (rc < 0) {
  1268. pr_err("adc-tm digital parameter setup err\n");
  1269. return rc;
  1270. }
  1271. /* Hardware setting time */
  1272. rc = qpnp_adc_tm_write_reg(chip, QPNP_HW_SETTLE_DELAY,
  1273. chan_prop->hw_settle_time, 1);
  1274. if (rc < 0) {
  1275. pr_err("adc-tm hw settling time setup err\n");
  1276. return rc;
  1277. }
  1278. /* Fast averaging setup/enable */
  1279. rc = qpnp_adc_tm_fast_avg_en(chip, &chan_prop->fast_avg_setup);
  1280. if (rc < 0) {
  1281. pr_err("adc-tm fast-avg enable err\n");
  1282. return rc;
  1283. }
  1284. rc = qpnp_adc_tm_write_reg(chip, QPNP_FAST_AVG_CTL,
  1285. chan_prop->fast_avg_setup, 1);
  1286. if (rc < 0) {
  1287. pr_err("adc-tm fast-avg setup err\n");
  1288. return rc;
  1289. }
  1290. /* Measurement interval setup */
  1291. rc = qpnp_adc_tm_timer_interval_select(chip, btm_chan,
  1292. chan_prop->chan_prop);
  1293. if (rc < 0) {
  1294. pr_err("adc-tm timer select failed\n");
  1295. return rc;
  1296. }
  1297. /* Channel configuration setup */
  1298. rc = qpnp_adc_tm_channel_configure(chip, btm_chan,
  1299. chan_prop->chan_prop, chan_prop->amux_channel);
  1300. if (rc < 0) {
  1301. pr_err("adc-tm channel configure failed\n");
  1302. return rc;
  1303. }
  1304. /* Recurring interval measurement enable */
  1305. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_MEAS_INTERVAL_OP_CTL,
  1306. &op_cntrl, 1);
  1307. op_cntrl |= QPNP_ADC_MEAS_INTERVAL_OP;
  1308. rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_MEAS_INTERVAL_OP_CTL,
  1309. op_cntrl, true);
  1310. if (rc < 0) {
  1311. pr_err("adc-tm meas interval op configure failed\n");
  1312. return rc;
  1313. }
  1314. /* Enable bank */
  1315. rc = qpnp_adc_tm_enable(chip);
  1316. if (rc)
  1317. return rc;
  1318. /* Request conversion */
  1319. rc = qpnp_adc_tm_write_reg(chip, QPNP_CONV_REQ, QPNP_CONV_REQ_SET, 1);
  1320. if (rc < 0) {
  1321. pr_err("adc-tm request conversion failed\n");
  1322. return rc;
  1323. }
  1324. return 0;
  1325. }
  1326. static int qpnp_adc_tm_set_mode(struct qpnp_adc_tm_sensor *adc_tm,
  1327. enum thermal_device_mode mode)
  1328. {
  1329. struct qpnp_adc_tm_chip *chip = adc_tm->chip;
  1330. int rc = 0, channel;
  1331. u8 sensor_mask = 0, mode_ctl = 0;
  1332. uint32_t btm_chan_idx = 0, btm_chan = 0;
  1333. if (qpnp_adc_tm_is_valid(chip)) {
  1334. pr_err("invalid device\n");
  1335. return -ENODEV;
  1336. }
  1337. if (qpnp_adc_tm_check_revision(chip, adc_tm->btm_channel_num))
  1338. return -EINVAL;
  1339. mutex_lock(&chip->adc->adc_lock);
  1340. btm_chan = adc_tm->btm_channel_num;
  1341. rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan, &btm_chan_idx);
  1342. if (rc < 0) {
  1343. pr_err("Invalid btm channel idx\n");
  1344. goto fail;
  1345. }
  1346. if (mode == THERMAL_DEVICE_ENABLED) {
  1347. chip->adc->amux_prop->amux_channel =
  1348. adc_tm->vadc_channel_num;
  1349. channel = adc_tm->sensor_num;
  1350. chip->adc->amux_prop->decimation =
  1351. chip->adc->adc_channels[channel].adc_decimation;
  1352. chip->adc->amux_prop->hw_settle_time =
  1353. chip->adc->adc_channels[channel].hw_settle_time;
  1354. chip->adc->amux_prop->fast_avg_setup =
  1355. chip->adc->adc_channels[channel].fast_avg_setup;
  1356. chip->adc->amux_prop->mode_sel =
  1357. ADC_OP_MEASUREMENT_INTERVAL << QPNP_OP_MODE_SHIFT;
  1358. chip->adc->amux_prop->chan_prop->low_thr = adc_tm->low_thr;
  1359. chip->adc->amux_prop->chan_prop->high_thr = adc_tm->high_thr;
  1360. chip->adc->amux_prop->chan_prop->tm_channel_select =
  1361. adc_tm->btm_channel_num;
  1362. chip->adc->amux_prop->calib_type =
  1363. chip->adc->adc_channels[channel].calib_type;
  1364. if (!chip->adc_tm_hc) {
  1365. rc = qpnp_adc_tm_configure(chip, chip->adc->amux_prop);
  1366. if (rc) {
  1367. pr_err("adc-tm configure failed with %d\n", rc);
  1368. goto fail;
  1369. }
  1370. } else {
  1371. rc = qpnp_adc_tm_hc_configure(chip,
  1372. chip->adc->amux_prop);
  1373. if (rc) {
  1374. pr_err("hc configure failed with %d\n", rc);
  1375. goto fail;
  1376. }
  1377. }
  1378. } else if (mode == THERMAL_DEVICE_DISABLED) {
  1379. sensor_mask = 1 << adc_tm->sensor_num;
  1380. if (!chip->adc_tm_hc) {
  1381. mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
  1382. rc = qpnp_adc_tm_mode_select(chip, mode_ctl);
  1383. if (rc < 0) {
  1384. pr_err("adc-tm single mode select failed\n");
  1385. goto fail;
  1386. }
  1387. }
  1388. /* Disable bank */
  1389. rc = qpnp_adc_tm_disable(chip);
  1390. if (rc < 0) {
  1391. pr_err("adc-tm disable failed\n");
  1392. goto fail;
  1393. }
  1394. if (!chip->adc_tm_hc) {
  1395. /* Check if a conversion is in progress */
  1396. rc = qpnp_adc_tm_req_sts_check(chip);
  1397. if (rc < 0) {
  1398. pr_err("adc-tm req_sts check failed\n");
  1399. goto fail;
  1400. }
  1401. rc = qpnp_adc_tm_reg_update(chip,
  1402. QPNP_ADC_TM_MULTI_MEAS_EN,
  1403. sensor_mask, false);
  1404. if (rc < 0) {
  1405. pr_err("multi measurement update failed\n");
  1406. goto fail;
  1407. }
  1408. } else {
  1409. rc = qpnp_adc_tm_reg_update(chip,
  1410. QPNP_BTM_Mn_EN(btm_chan_idx),
  1411. QPNP_BTM_Mn_MEAS_EN, false);
  1412. if (rc < 0) {
  1413. pr_err("multi measurement disable failed\n");
  1414. goto fail;
  1415. }
  1416. }
  1417. rc = qpnp_adc_tm_enable_if_channel_meas(chip);
  1418. if (rc < 0) {
  1419. pr_err("re-enabling measurement failed\n");
  1420. goto fail;
  1421. }
  1422. }
  1423. adc_tm->mode = mode;
  1424. fail:
  1425. mutex_unlock(&chip->adc->adc_lock);
  1426. return 0;
  1427. }
  1428. static int qpnp_adc_tm_activate_trip_type(struct qpnp_adc_tm_sensor *adc_tm,
  1429. int trip, enum thermal_trip_activation_mode mode)
  1430. {
  1431. struct qpnp_adc_tm_chip *chip = adc_tm->chip;
  1432. int rc = 0, sensor_mask = 0;
  1433. u8 thr_int_en = 0;
  1434. bool state = false;
  1435. uint32_t btm_chan_idx = 0, btm_chan = 0;
  1436. if (qpnp_adc_tm_is_valid(chip))
  1437. return -ENODEV;
  1438. if (qpnp_adc_tm_check_revision(chip, adc_tm->btm_channel_num))
  1439. return -EINVAL;
  1440. if (mode == THERMAL_TRIP_ACTIVATION_ENABLED)
  1441. state = true;
  1442. sensor_mask = 1 << adc_tm->sensor_num;
  1443. pr_debug("Sensor number:%x with state:%d\n",
  1444. adc_tm->sensor_num, state);
  1445. btm_chan = adc_tm->btm_channel_num;
  1446. rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan, &btm_chan_idx);
  1447. if (rc < 0) {
  1448. pr_err("Invalid btm channel idx\n");
  1449. return rc;
  1450. }
  1451. switch (trip) {
  1452. case ADC_TM_TRIP_HIGH_WARM:
  1453. /* low_thr (lower voltage) for higher temp */
  1454. thr_int_en = adc_tm_data[btm_chan_idx].low_thr_int_chan_en;
  1455. if (!chip->adc_tm_hc)
  1456. rc = qpnp_adc_tm_reg_update(chip,
  1457. QPNP_ADC_TM_LOW_THR_INT_EN,
  1458. sensor_mask, state);
  1459. else
  1460. rc = qpnp_adc_tm_reg_update(chip,
  1461. QPNP_BTM_Mn_EN(btm_chan_idx),
  1462. QPNP_BTM_Mn_LOW_THR_INT_EN, state);
  1463. if (rc)
  1464. pr_err("channel:%x failed\n", btm_chan);
  1465. break;
  1466. case ADC_TM_TRIP_LOW_COOL:
  1467. /* high_thr (higher voltage) for cooler temp */
  1468. thr_int_en = adc_tm_data[btm_chan_idx].high_thr_int_chan_en;
  1469. if (!chip->adc_tm_hc)
  1470. rc = qpnp_adc_tm_reg_update(chip,
  1471. QPNP_ADC_TM_HIGH_THR_INT_EN,
  1472. sensor_mask, state);
  1473. else
  1474. rc = qpnp_adc_tm_reg_update(chip,
  1475. QPNP_BTM_Mn_EN(btm_chan_idx),
  1476. QPNP_BTM_Mn_HIGH_THR_INT_EN, state);
  1477. if (rc)
  1478. pr_err("channel:%x failed\n", btm_chan);
  1479. break;
  1480. default:
  1481. return -EINVAL;
  1482. }
  1483. return rc;
  1484. }
  1485. static int qpnp_adc_tm_set_trip_temp(void *data, int low_temp, int high_temp)
  1486. {
  1487. struct qpnp_adc_tm_sensor *adc_tm = data;
  1488. struct qpnp_adc_tm_chip *chip = adc_tm->chip;
  1489. struct qpnp_adc_tm_config tm_config;
  1490. u8 trip_cool_thr0, trip_cool_thr1, trip_warm_thr0, trip_warm_thr1;
  1491. uint16_t reg_low_thr_lsb, reg_low_thr_msb;
  1492. uint16_t reg_high_thr_lsb, reg_high_thr_msb;
  1493. int rc = 0;
  1494. uint32_t btm_chan = 0, btm_chan_idx = 0;
  1495. int emul_temp;
  1496. if (qpnp_adc_tm_is_valid(chip))
  1497. return -ENODEV;
  1498. if (qpnp_adc_tm_check_revision(chip, adc_tm->btm_channel_num))
  1499. return -EINVAL;
  1500. tm_config.channel = adc_tm->vadc_channel_num;
  1501. tm_config.high_thr_temp = tm_config.low_thr_temp = 0;
  1502. if (high_temp != INT_MAX)
  1503. tm_config.high_thr_temp = high_temp;
  1504. if (low_temp != INT_MIN)
  1505. tm_config.low_thr_temp = low_temp;
  1506. if ((high_temp == INT_MAX) && (low_temp == INT_MIN)) {
  1507. pr_err("No trips to set\n");
  1508. return -EINVAL;
  1509. }
  1510. /* Set threshold to extremely value while emul temp set */
  1511. emul_temp = adc_tm->emul_temperature;
  1512. if (emul_temp) {
  1513. high_temp = INT_MAX;
  1514. low_temp = INT_MIN;
  1515. }
  1516. pr_debug("requested a high - %d and low - %d\n",
  1517. tm_config.high_thr_temp, tm_config.low_thr_temp);
  1518. rc = qpnp_adc_tm_scale_therm_voltage_pu2(chip->vadc_dev,
  1519. chip->adc->adc_prop, &tm_config);
  1520. if (rc < 0) {
  1521. pr_err("Failed to lookup the adc-tm thresholds\n");
  1522. return rc;
  1523. }
  1524. trip_warm_thr0 = ((tm_config.low_thr_voltage << 24) >> 24);
  1525. trip_warm_thr1 = ((tm_config.low_thr_voltage << 16) >> 24);
  1526. trip_cool_thr0 = ((tm_config.high_thr_voltage << 24) >> 24);
  1527. trip_cool_thr1 = ((tm_config.high_thr_voltage << 16) >> 24);
  1528. pr_debug("low_thr:0x%llx, high_thr:0x%llx\n", tm_config.low_thr_voltage,
  1529. tm_config.high_thr_voltage);
  1530. btm_chan = adc_tm->btm_channel_num;
  1531. rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan, &btm_chan_idx);
  1532. if (rc < 0) {
  1533. pr_err("Invalid btm channel idx\n");
  1534. return rc;
  1535. }
  1536. if (!chip->adc_tm_hc) {
  1537. reg_low_thr_lsb = adc_tm_data[btm_chan_idx].low_thr_lsb_addr;
  1538. reg_low_thr_msb = adc_tm_data[btm_chan_idx].low_thr_msb_addr;
  1539. reg_high_thr_lsb = adc_tm_data[btm_chan_idx].high_thr_lsb_addr;
  1540. reg_high_thr_msb = adc_tm_data[btm_chan_idx].high_thr_msb_addr;
  1541. } else {
  1542. reg_low_thr_lsb = QPNP_BTM_Mn_LOW_THR0(btm_chan_idx);
  1543. reg_low_thr_msb = QPNP_BTM_Mn_LOW_THR1(btm_chan_idx);
  1544. reg_high_thr_lsb = QPNP_BTM_Mn_HIGH_THR0(btm_chan_idx);
  1545. reg_high_thr_msb = QPNP_BTM_Mn_HIGH_THR1(btm_chan_idx);
  1546. }
  1547. if (high_temp != INT_MAX) {
  1548. rc = qpnp_adc_tm_write_reg(chip, reg_low_thr_lsb,
  1549. trip_cool_thr0, 1);
  1550. if (rc) {
  1551. pr_err("adc-tm_tm read threshold err\n");
  1552. return rc;
  1553. }
  1554. rc = qpnp_adc_tm_write_reg(chip, reg_low_thr_msb,
  1555. trip_cool_thr1, 1);
  1556. if (rc) {
  1557. pr_err("adc-tm_tm read threshold err\n");
  1558. return rc;
  1559. }
  1560. adc_tm->low_thr = tm_config.high_thr_voltage;
  1561. rc = qpnp_adc_tm_activate_trip_type(adc_tm,
  1562. ADC_TM_TRIP_HIGH_WARM,
  1563. THERMAL_TRIP_ACTIVATION_ENABLED);
  1564. if (rc) {
  1565. pr_err("adc-tm warm activation failed\n");
  1566. return rc;
  1567. }
  1568. } else {
  1569. rc = qpnp_adc_tm_activate_trip_type(adc_tm,
  1570. ADC_TM_TRIP_HIGH_WARM,
  1571. THERMAL_TRIP_ACTIVATION_DISABLED);
  1572. if (rc) {
  1573. pr_err("adc-tm warm deactivation failed\n");
  1574. return rc;
  1575. }
  1576. }
  1577. if (low_temp != INT_MIN) {
  1578. rc = qpnp_adc_tm_write_reg(chip, reg_high_thr_lsb,
  1579. trip_warm_thr0, 1);
  1580. if (rc) {
  1581. pr_err("adc-tm_tm read threshold err\n");
  1582. return rc;
  1583. }
  1584. rc = qpnp_adc_tm_write_reg(chip, reg_high_thr_msb,
  1585. trip_warm_thr1, 1);
  1586. if (rc) {
  1587. pr_err("adc-tm_tm read threshold err\n");
  1588. return rc;
  1589. }
  1590. adc_tm->high_thr = tm_config.low_thr_voltage;
  1591. rc = qpnp_adc_tm_activate_trip_type(adc_tm,
  1592. ADC_TM_TRIP_LOW_COOL,
  1593. THERMAL_TRIP_ACTIVATION_ENABLED);
  1594. if (rc) {
  1595. pr_err("adc-tm cool activation failed\n");
  1596. return rc;
  1597. }
  1598. } else {
  1599. rc = qpnp_adc_tm_activate_trip_type(adc_tm,
  1600. ADC_TM_TRIP_LOW_COOL,
  1601. THERMAL_TRIP_ACTIVATION_DISABLED);
  1602. if (rc) {
  1603. pr_err("adc-tm cool deactivation failed\n");
  1604. return rc;
  1605. }
  1606. }
  1607. if ((high_temp != INT_MAX) || (low_temp != INT_MIN)) {
  1608. rc = qpnp_adc_tm_set_mode(adc_tm, THERMAL_DEVICE_ENABLED);
  1609. if (rc) {
  1610. pr_err("sensor enabled failed\n");
  1611. return rc;
  1612. }
  1613. } else {
  1614. rc = qpnp_adc_tm_set_mode(adc_tm, THERMAL_DEVICE_DISABLED);
  1615. if (rc) {
  1616. pr_err("sensor disable failed\n");
  1617. return rc;
  1618. }
  1619. }
  1620. return 0;
  1621. }
  1622. static int qpnp_adc_tm_set_emul_temp(void *data, int emul_temp)
  1623. {
  1624. struct qpnp_adc_tm_sensor *adc_tm_sensor = data;
  1625. adc_tm_sensor->emul_temperature = emul_temp;
  1626. return 0;
  1627. }
  1628. static void notify_battery_therm(struct qpnp_adc_tm_sensor *adc_tm)
  1629. {
  1630. struct qpnp_adc_thr_client_info *client_info = NULL;
  1631. list_for_each_entry(client_info,
  1632. &adc_tm->thr_list, list) {
  1633. /* Batt therm's warm temperature translates to low voltage */
  1634. if (client_info->notify_low_thr) {
  1635. /* HIGH_STATE = WARM_TEMP for battery client */
  1636. client_info->btm_param->threshold_notification(
  1637. ADC_TM_WARM_STATE, client_info->btm_param->btm_ctx);
  1638. client_info->notify_low_thr = false;
  1639. }
  1640. /* Batt therm's cool temperature translates to high voltage */
  1641. if (client_info->notify_high_thr) {
  1642. /* LOW_STATE = COOL_TEMP for battery client */
  1643. client_info->btm_param->threshold_notification(
  1644. ADC_TM_COOL_STATE, client_info->btm_param->btm_ctx);
  1645. client_info->notify_high_thr = false;
  1646. }
  1647. }
  1648. }
  1649. static void notify_clients(struct qpnp_adc_tm_sensor *adc_tm)
  1650. {
  1651. struct qpnp_adc_thr_client_info *client_info = NULL;
  1652. list_for_each_entry(client_info,
  1653. &adc_tm->thr_list, list) {
  1654. /* For non batt therm clients */
  1655. if (client_info->notify_low_thr) {
  1656. if (client_info->btm_param->threshold_notification
  1657. != NULL) {
  1658. pr_debug("notify kernel with low state\n");
  1659. client_info->btm_param->threshold_notification(
  1660. ADC_TM_LOW_STATE,
  1661. client_info->btm_param->btm_ctx);
  1662. client_info->notify_low_thr = false;
  1663. }
  1664. }
  1665. if (client_info->notify_high_thr) {
  1666. if (client_info->btm_param->threshold_notification
  1667. != NULL) {
  1668. pr_debug("notify kernel with high state\n");
  1669. client_info->btm_param->threshold_notification(
  1670. ADC_TM_HIGH_STATE,
  1671. client_info->btm_param->btm_ctx);
  1672. client_info->notify_high_thr = false;
  1673. }
  1674. }
  1675. }
  1676. }
  1677. static int qpnp_adc_read_temp(void *data, int *temp)
  1678. {
  1679. struct qpnp_adc_tm_sensor *adc_tm_sensor = data;
  1680. struct qpnp_adc_tm_chip *chip = adc_tm_sensor->chip;
  1681. struct qpnp_vadc_result result;
  1682. int rc = 0;
  1683. int emul_temp;
  1684. emul_temp = adc_tm_sensor->emul_temperature;
  1685. if (emul_temp) {
  1686. *temp = emul_temp;
  1687. return rc;
  1688. }
  1689. rc = qpnp_vadc_read(chip->vadc_dev,
  1690. adc_tm_sensor->vadc_channel_num, &result);
  1691. if (rc)
  1692. return rc;
  1693. *temp = result.physical;
  1694. return rc;
  1695. }
  1696. static void notify_adc_tm_fn(struct work_struct *work)
  1697. {
  1698. struct qpnp_adc_tm_sensor *adc_tm = container_of(work,
  1699. struct qpnp_adc_tm_sensor, work);
  1700. int temp;
  1701. int ret;
  1702. if (adc_tm->thermal_node) {
  1703. pr_debug("notifying uspace client\n");
  1704. ret = qpnp_adc_read_temp(adc_tm, &temp);
  1705. if (ret)
  1706. of_thermal_handle_trip(adc_tm->tz_dev);
  1707. else
  1708. of_thermal_handle_trip_temp(adc_tm->tz_dev, temp);
  1709. } else {
  1710. if (adc_tm->scale_type == SCALE_RBATT_THERM)
  1711. notify_battery_therm(adc_tm);
  1712. else
  1713. notify_clients(adc_tm);
  1714. }
  1715. }
  1716. static int qpnp_adc_tm_recalib_request_check(struct qpnp_adc_tm_chip *chip,
  1717. int sensor_num, u8 status_high, u8 *notify_check)
  1718. {
  1719. int rc = 0;
  1720. u8 sensor_mask = 0, mode_ctl = 0;
  1721. int32_t old_thr = 0, new_thr = 0;
  1722. uint32_t channel, btm_chan_num, scale_type;
  1723. struct qpnp_vadc_result result;
  1724. struct qpnp_adc_thr_client_info *client_info = NULL;
  1725. struct list_head *thr_list;
  1726. bool status = false;
  1727. if (!chip->adc_tm_recalib_check) {
  1728. *notify_check = 1;
  1729. return rc;
  1730. }
  1731. list_for_each(thr_list, &chip->sensor[sensor_num].thr_list) {
  1732. client_info = list_entry(thr_list,
  1733. struct qpnp_adc_thr_client_info, list);
  1734. channel = client_info->btm_param->channel;
  1735. btm_chan_num = chip->sensor[sensor_num].btm_channel_num;
  1736. sensor_mask = 1 << sensor_num;
  1737. rc = qpnp_vadc_read(chip->vadc_dev, channel, &result);
  1738. if (rc < 0) {
  1739. pr_err("failure to read vadc channel=%d\n",
  1740. client_info->btm_param->channel);
  1741. goto fail;
  1742. }
  1743. new_thr = result.physical;
  1744. if (status_high)
  1745. old_thr = client_info->btm_param->high_thr;
  1746. else
  1747. old_thr = client_info->btm_param->low_thr;
  1748. if (new_thr > old_thr)
  1749. status = (status_high) ? true : false;
  1750. else
  1751. status = (status_high) ? false : true;
  1752. pr_debug(
  1753. "recalib:sen=%d, new_thr=%d, new_thr_adc_code=0x%x, old_thr=%d status=%d valid_status=%d\n",
  1754. sensor_num, new_thr, result.adc_code,
  1755. old_thr, status_high, status);
  1756. rc = qpnp_adc_tm_read_thr_value(chip, btm_chan_num);
  1757. if (rc < 0) {
  1758. pr_err("adc-tm thresholds read failed\n");
  1759. goto fail;
  1760. }
  1761. if (status) {
  1762. *notify_check = 1;
  1763. pr_debug("Client can be notify\n");
  1764. return rc;
  1765. }
  1766. pr_debug("Client can not be notify, restart measurement\n");
  1767. /* Set measurement in single measurement mode */
  1768. mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
  1769. rc = qpnp_adc_tm_mode_select(chip, mode_ctl);
  1770. if (rc < 0) {
  1771. pr_err("adc-tm single mode select failed\n");
  1772. goto fail;
  1773. }
  1774. /* Disable bank */
  1775. rc = qpnp_adc_tm_disable(chip);
  1776. if (rc < 0) {
  1777. pr_err("adc-tm disable failed\n");
  1778. goto fail;
  1779. }
  1780. /* Check if a conversion is in progress */
  1781. rc = qpnp_adc_tm_req_sts_check(chip);
  1782. if (rc < 0) {
  1783. pr_err("adc-tm req_sts check failed\n");
  1784. goto fail;
  1785. }
  1786. rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_TM_LOW_THR_INT_EN,
  1787. sensor_mask, false);
  1788. if (rc < 0) {
  1789. pr_err("low threshold int write failed\n");
  1790. goto fail;
  1791. }
  1792. rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_TM_HIGH_THR_INT_EN,
  1793. sensor_mask, false);
  1794. if (rc < 0) {
  1795. pr_err("high threshold int enable failed\n");
  1796. goto fail;
  1797. }
  1798. rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
  1799. sensor_mask, false);
  1800. if (rc < 0) {
  1801. pr_err("multi measurement en failed\n");
  1802. goto fail;
  1803. }
  1804. /* restart measurement */
  1805. scale_type = chip->sensor[sensor_num].scale_type;
  1806. chip->adc->amux_prop->amux_channel = channel;
  1807. chip->adc->amux_prop->decimation =
  1808. chip->adc->adc_channels[sensor_num].adc_decimation;
  1809. chip->adc->amux_prop->hw_settle_time =
  1810. chip->adc->adc_channels[sensor_num].hw_settle_time;
  1811. chip->adc->amux_prop->fast_avg_setup =
  1812. chip->adc->adc_channels[sensor_num].fast_avg_setup;
  1813. chip->adc->amux_prop->mode_sel =
  1814. ADC_OP_MEASUREMENT_INTERVAL << QPNP_OP_MODE_SHIFT;
  1815. adc_tm_rscale_fn[scale_type].chan(chip->vadc_dev,
  1816. client_info->btm_param,
  1817. &chip->adc->amux_prop->chan_prop->low_thr,
  1818. &chip->adc->amux_prop->chan_prop->high_thr);
  1819. qpnp_adc_tm_add_to_list(chip, sensor_num,
  1820. client_info->btm_param,
  1821. chip->adc->amux_prop->chan_prop);
  1822. chip->adc->amux_prop->chan_prop->tm_channel_select =
  1823. chip->sensor[sensor_num].btm_channel_num;
  1824. chip->adc->amux_prop->chan_prop->state_request =
  1825. client_info->btm_param->state_request;
  1826. rc = qpnp_adc_tm_configure(chip, chip->adc->amux_prop);
  1827. if (rc) {
  1828. pr_err("adc-tm configure failed with %d\n", rc);
  1829. goto fail;
  1830. }
  1831. *notify_check = 0;
  1832. pr_debug("BTM channel reconfigured for measuremnt\n");
  1833. }
  1834. fail:
  1835. return rc;
  1836. }
  1837. static int qpnp_adc_tm_disable_rearm_high_thresholds(
  1838. struct qpnp_adc_tm_chip *chip, int sensor_num)
  1839. {
  1840. struct qpnp_adc_thr_client_info *client_info = NULL;
  1841. struct list_head *thr_list;
  1842. uint32_t btm_chan_num = 0, btm_chan_idx = 0;
  1843. u8 sensor_mask = 0, notify_check = 0;
  1844. int rc = 0;
  1845. btm_chan_num = chip->sensor[sensor_num].btm_channel_num;
  1846. rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan_num, &btm_chan_idx);
  1847. if (rc < 0) {
  1848. pr_err("Invalid btm channel idx\n");
  1849. return rc;
  1850. }
  1851. pr_debug("high:sen:%d, hs:0x%x, ls:0x%x, meas_en:0x%x\n",
  1852. sensor_num, chip->th_info.adc_tm_high_enable,
  1853. chip->th_info.adc_tm_low_enable,
  1854. chip->th_info.qpnp_adc_tm_meas_en);
  1855. if (!chip->sensor[sensor_num].thermal_node) {
  1856. /*
  1857. * For non thermal registered clients such as usb_id,
  1858. * vbatt, pmic_therm
  1859. */
  1860. sensor_mask = 1 << sensor_num;
  1861. pr_debug("non thermal node - mask:%x\n", sensor_mask);
  1862. if (!chip->adc_tm_hc) {
  1863. rc = qpnp_adc_tm_recalib_request_check(chip,
  1864. sensor_num, true, &notify_check);
  1865. if (rc < 0 || !notify_check) {
  1866. pr_debug("Calib recheck re-armed rc=%d\n", rc);
  1867. chip->th_info.adc_tm_high_enable = 0;
  1868. return rc;
  1869. }
  1870. } else {
  1871. rc = qpnp_adc_tm_reg_update(chip,
  1872. QPNP_BTM_Mn_EN(btm_chan_idx),
  1873. QPNP_BTM_Mn_HIGH_THR_INT_EN, false);
  1874. if (rc < 0) {
  1875. pr_err("high threshold int update failed\n");
  1876. return rc;
  1877. }
  1878. }
  1879. } else {
  1880. /*
  1881. * Uses the thermal sysfs registered device to disable
  1882. * the corresponding high voltage threshold which
  1883. * is triggered by low temp
  1884. */
  1885. sensor_mask = 1 << sensor_num;
  1886. pr_debug("thermal node with mask:%x\n", sensor_mask);
  1887. rc = qpnp_adc_tm_activate_trip_type(
  1888. &chip->sensor[sensor_num],
  1889. ADC_TM_TRIP_LOW_COOL,
  1890. THERMAL_TRIP_ACTIVATION_DISABLED);
  1891. if (rc < 0) {
  1892. pr_err("notify error:%d\n", sensor_num);
  1893. return rc;
  1894. }
  1895. }
  1896. list_for_each(thr_list, &chip->sensor[sensor_num].thr_list) {
  1897. client_info = list_entry(thr_list,
  1898. struct qpnp_adc_thr_client_info, list);
  1899. if (client_info->high_thr_set) {
  1900. client_info->high_thr_set = false;
  1901. client_info->notify_high_thr = true;
  1902. if (client_info->state_req_copy ==
  1903. ADC_TM_HIGH_LOW_THR_ENABLE)
  1904. client_info->state_req_copy =
  1905. ADC_TM_LOW_THR_ENABLE;
  1906. else
  1907. client_info->state_req_copy =
  1908. ADC_TM_HIGH_THR_DISABLE;
  1909. }
  1910. }
  1911. qpnp_adc_tm_manage_thresholds(chip, sensor_num, btm_chan_num);
  1912. if (!chip->adc_tm_hc) {
  1913. rc = qpnp_adc_tm_reg_update(chip,
  1914. QPNP_ADC_TM_MULTI_MEAS_EN,
  1915. sensor_mask, false);
  1916. if (rc < 0) {
  1917. pr_err("multi meas disable failed\n");
  1918. return rc;
  1919. }
  1920. } else {
  1921. rc = qpnp_adc_tm_reg_update(chip,
  1922. QPNP_BTM_Mn_EN(sensor_num),
  1923. QPNP_BTM_Mn_MEAS_EN, false);
  1924. if (rc < 0) {
  1925. pr_err("multi meas disable failed\n");
  1926. return rc;
  1927. }
  1928. }
  1929. rc = qpnp_adc_tm_enable_if_channel_meas(chip);
  1930. if (rc < 0) {
  1931. pr_err("re-enabling measurement failed\n");
  1932. return rc;
  1933. }
  1934. queue_work(chip->sensor[sensor_num].req_wq,
  1935. &chip->sensor[sensor_num].work);
  1936. return rc;
  1937. }
  1938. static int qpnp_adc_tm_disable_rearm_low_thresholds(
  1939. struct qpnp_adc_tm_chip *chip, int sensor_num)
  1940. {
  1941. struct qpnp_adc_thr_client_info *client_info = NULL;
  1942. struct list_head *thr_list;
  1943. uint32_t btm_chan_num = 0, btm_chan_idx = 0;
  1944. u8 sensor_mask = 0, notify_check = 0;
  1945. int rc = 0;
  1946. btm_chan_num = chip->sensor[sensor_num].btm_channel_num;
  1947. rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan_num, &btm_chan_idx);
  1948. if (rc < 0) {
  1949. pr_err("Invalid btm channel idx\n");
  1950. return rc;
  1951. }
  1952. pr_debug("low:sen:%d, hs:0x%x, ls:0x%x, meas_en:0x%x\n",
  1953. sensor_num, chip->th_info.adc_tm_high_enable,
  1954. chip->th_info.adc_tm_low_enable,
  1955. chip->th_info.qpnp_adc_tm_meas_en);
  1956. if (!chip->sensor[sensor_num].thermal_node) {
  1957. /*
  1958. * For non thermal registered clients such as usb_id,
  1959. * vbatt, pmic_therm
  1960. */
  1961. sensor_mask = 1 << sensor_num;
  1962. pr_debug("non thermal node - mask:%x\n", sensor_mask);
  1963. if (!chip->adc_tm_hc) {
  1964. rc = qpnp_adc_tm_recalib_request_check(chip,
  1965. sensor_num, false, &notify_check);
  1966. if (rc < 0 || !notify_check) {
  1967. pr_debug("Calib recheck re-armed rc=%d\n", rc);
  1968. chip->th_info.adc_tm_low_enable = 0;
  1969. return rc;
  1970. }
  1971. } else {
  1972. rc = qpnp_adc_tm_reg_update(chip,
  1973. QPNP_BTM_Mn_EN(btm_chan_idx),
  1974. QPNP_BTM_Mn_LOW_THR_INT_EN, false);
  1975. if (rc < 0) {
  1976. pr_err("low threshold int update failed\n");
  1977. return rc;
  1978. }
  1979. }
  1980. } else {
  1981. /*
  1982. * Uses the thermal sysfs registered device to disable
  1983. * the corresponding high voltage threshold which
  1984. * is triggered by low temp
  1985. */
  1986. sensor_mask = 1 << sensor_num;
  1987. pr_debug("thermal node with mask:%x\n", sensor_mask);
  1988. rc = qpnp_adc_tm_activate_trip_type(
  1989. &chip->sensor[sensor_num],
  1990. ADC_TM_TRIP_HIGH_WARM,
  1991. THERMAL_TRIP_ACTIVATION_DISABLED);
  1992. if (rc < 0) {
  1993. pr_err("notify error:%d\n", sensor_num);
  1994. return rc;
  1995. }
  1996. }
  1997. list_for_each(thr_list, &chip->sensor[sensor_num].thr_list) {
  1998. client_info = list_entry(thr_list,
  1999. struct qpnp_adc_thr_client_info, list);
  2000. if (client_info->low_thr_set) {
  2001. client_info->low_thr_set = false;
  2002. client_info->notify_low_thr = true;
  2003. if (client_info->state_req_copy ==
  2004. ADC_TM_HIGH_LOW_THR_ENABLE)
  2005. client_info->state_req_copy =
  2006. ADC_TM_HIGH_THR_ENABLE;
  2007. else
  2008. client_info->state_req_copy =
  2009. ADC_TM_LOW_THR_DISABLE;
  2010. }
  2011. }
  2012. qpnp_adc_tm_manage_thresholds(chip, sensor_num, btm_chan_num);
  2013. if (!chip->adc_tm_hc) {
  2014. rc = qpnp_adc_tm_reg_update(chip,
  2015. QPNP_ADC_TM_MULTI_MEAS_EN,
  2016. sensor_mask, false);
  2017. if (rc < 0) {
  2018. pr_err("multi meas disable failed\n");
  2019. return rc;
  2020. }
  2021. } else {
  2022. rc = qpnp_adc_tm_reg_update(chip,
  2023. QPNP_BTM_Mn_EN(sensor_num),
  2024. QPNP_BTM_Mn_MEAS_EN, false);
  2025. if (rc < 0) {
  2026. pr_err("multi meas disable failed\n");
  2027. return rc;
  2028. }
  2029. }
  2030. rc = qpnp_adc_tm_enable_if_channel_meas(chip);
  2031. if (rc < 0) {
  2032. pr_err("re-enabling measurement failed\n");
  2033. return rc;
  2034. }
  2035. queue_work(chip->sensor[sensor_num].req_wq,
  2036. &chip->sensor[sensor_num].work);
  2037. return rc;
  2038. }
  2039. static int qpnp_adc_tm_read_status(struct qpnp_adc_tm_chip *chip)
  2040. {
  2041. int rc = 0, sensor_notify_num = 0, i = 0, sensor_num = 0;
  2042. unsigned long flags;
  2043. if (qpnp_adc_tm_is_valid(chip))
  2044. return -ENODEV;
  2045. mutex_lock(&chip->adc->adc_lock);
  2046. rc = qpnp_adc_tm_req_sts_check(chip);
  2047. if (rc) {
  2048. pr_err("adc-tm-tm req sts check failed with %d\n", rc);
  2049. goto fail;
  2050. }
  2051. if (chip->th_info.adc_tm_high_enable) {
  2052. spin_lock_irqsave(&chip->th_info.adc_tm_high_lock, flags);
  2053. sensor_notify_num = chip->th_info.adc_tm_high_enable;
  2054. chip->th_info.adc_tm_high_enable = 0;
  2055. spin_unlock_irqrestore(&chip->th_info.adc_tm_high_lock, flags);
  2056. while (i < chip->max_channels_available) {
  2057. if ((sensor_notify_num & 0x1) == 1) {
  2058. sensor_num = i;
  2059. rc = qpnp_adc_tm_disable_rearm_high_thresholds(
  2060. chip, sensor_num);
  2061. if (rc < 0) {
  2062. pr_err("rearm threshold failed\n");
  2063. goto fail;
  2064. }
  2065. }
  2066. sensor_notify_num >>= 1;
  2067. i++;
  2068. }
  2069. }
  2070. if (chip->th_info.adc_tm_low_enable) {
  2071. spin_lock_irqsave(&chip->th_info.adc_tm_low_lock, flags);
  2072. sensor_notify_num = chip->th_info.adc_tm_low_enable;
  2073. chip->th_info.adc_tm_low_enable = 0;
  2074. spin_unlock_irqrestore(&chip->th_info.adc_tm_low_lock, flags);
  2075. i = 0;
  2076. while (i < chip->max_channels_available) {
  2077. if ((sensor_notify_num & 0x1) == 1) {
  2078. sensor_num = i;
  2079. rc = qpnp_adc_tm_disable_rearm_low_thresholds(
  2080. chip, sensor_num);
  2081. if (rc < 0) {
  2082. pr_err("rearm threshold failed\n");
  2083. goto fail;
  2084. }
  2085. }
  2086. sensor_notify_num >>= 1;
  2087. i++;
  2088. }
  2089. }
  2090. fail:
  2091. mutex_unlock(&chip->adc->adc_lock);
  2092. return rc;
  2093. }
  2094. static int qpnp_adc_tm_hc_read_status(struct qpnp_adc_tm_chip *chip)
  2095. {
  2096. int rc = 0, sensor_num = 0;
  2097. if (qpnp_adc_tm_is_valid(chip))
  2098. return -ENODEV;
  2099. pr_debug("%s\n", __func__);
  2100. mutex_lock(&chip->adc->adc_lock);
  2101. if (!chip->adc_tm_hc) {
  2102. rc = qpnp_adc_tm_req_sts_check(chip);
  2103. if (rc) {
  2104. pr_err("adc-tm-tm req sts check failed with %d\n", rc);
  2105. goto fail;
  2106. }
  2107. }
  2108. while (sensor_num < chip->max_channels_available) {
  2109. if (chip->sensor[sensor_num].high_thr_triggered) {
  2110. rc = qpnp_adc_tm_disable_rearm_high_thresholds(
  2111. chip, sensor_num);
  2112. if (rc) {
  2113. pr_err("rearm threshold failed\n");
  2114. goto fail;
  2115. }
  2116. chip->sensor[sensor_num].high_thr_triggered = false;
  2117. }
  2118. sensor_num++;
  2119. }
  2120. sensor_num = 0;
  2121. while (sensor_num < chip->max_channels_available) {
  2122. if (chip->sensor[sensor_num].low_thr_triggered) {
  2123. rc = qpnp_adc_tm_disable_rearm_low_thresholds(
  2124. chip, sensor_num);
  2125. if (rc) {
  2126. pr_err("rearm threshold failed\n");
  2127. goto fail;
  2128. }
  2129. chip->sensor[sensor_num].low_thr_triggered = false;
  2130. }
  2131. sensor_num++;
  2132. }
  2133. fail:
  2134. mutex_unlock(&chip->adc->adc_lock);
  2135. return rc;
  2136. }
  2137. static void qpnp_adc_tm_high_thr_work(struct work_struct *work)
  2138. {
  2139. struct qpnp_adc_tm_chip *chip = container_of(work,
  2140. struct qpnp_adc_tm_chip, trigger_high_thr_work);
  2141. int rc;
  2142. /* disable the vote if applicable */
  2143. if (chip->adc_vote_enable && chip->adc->hkadc_ldo &&
  2144. chip->adc->hkadc_ldo_ok) {
  2145. qpnp_adc_disable_voltage(chip->adc);
  2146. chip->adc_vote_enable = false;
  2147. }
  2148. pr_debug("thr:0x%x\n", chip->th_info.adc_tm_high_enable);
  2149. if (!chip->adc_tm_hc) {
  2150. rc = qpnp_adc_tm_read_status(chip);
  2151. if (rc < 0)
  2152. pr_err("adc-tm high thr work failed\n");
  2153. } else {
  2154. rc = qpnp_adc_tm_hc_read_status(chip);
  2155. if (rc < 0)
  2156. pr_err("adc-tm-hc high thr work failed\n");
  2157. }
  2158. }
  2159. static irqreturn_t qpnp_adc_tm_high_thr_isr(int irq, void *data)
  2160. {
  2161. struct qpnp_adc_tm_chip *chip = data;
  2162. u8 mode_ctl = 0, status1 = 0, sensor_mask = 0;
  2163. int rc = 0, sensor_notify_num = 0, i = 0, sensor_num = 0;
  2164. mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
  2165. /* Set measurement in single measurement mode */
  2166. qpnp_adc_tm_mode_select(chip, mode_ctl);
  2167. qpnp_adc_tm_disable(chip);
  2168. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS1, &status1, 1);
  2169. if (rc) {
  2170. pr_err("adc-tm read status1 failed\n");
  2171. return IRQ_HANDLED;
  2172. }
  2173. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS_HIGH,
  2174. &chip->th_info.status_high, 1);
  2175. if (rc) {
  2176. pr_err("adc-tm-tm read status high failed with %d\n", rc);
  2177. return IRQ_HANDLED;
  2178. }
  2179. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_HIGH_THR_INT_EN,
  2180. &chip->th_info.adc_tm_high_thr_set, 1);
  2181. if (rc) {
  2182. pr_err("adc-tm-tm read high thr failed with %d\n", rc);
  2183. return IRQ_HANDLED;
  2184. }
  2185. /* Check which interrupt threshold is lower and measure against the
  2186. * enabled channel
  2187. */
  2188. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
  2189. &chip->th_info.qpnp_adc_tm_meas_en, 1);
  2190. if (rc) {
  2191. pr_err("adc-tm-tm read status high failed with %d\n", rc);
  2192. return IRQ_HANDLED;
  2193. }
  2194. chip->th_info.adc_tm_high_enable = chip->th_info.qpnp_adc_tm_meas_en &
  2195. chip->th_info.status_high;
  2196. chip->th_info.adc_tm_high_enable &= chip->th_info.adc_tm_high_thr_set;
  2197. sensor_notify_num = chip->th_info.adc_tm_high_enable;
  2198. while (i < chip->max_channels_available) {
  2199. if ((sensor_notify_num & 0x1) == 1)
  2200. sensor_num = i;
  2201. sensor_notify_num >>= 1;
  2202. i++;
  2203. }
  2204. if (!chip->sensor[sensor_num].thermal_node) {
  2205. sensor_mask = 1 << sensor_num;
  2206. rc = qpnp_adc_tm_reg_update(chip,
  2207. QPNP_ADC_TM_HIGH_THR_INT_EN,
  2208. sensor_mask, false);
  2209. if (rc < 0) {
  2210. pr_err("high threshold int read failed\n");
  2211. return IRQ_HANDLED;
  2212. }
  2213. } else {
  2214. /*
  2215. * Uses the thermal sysfs registered device to disable
  2216. * the corresponding high voltage threshold which
  2217. * is triggered by low temp
  2218. */
  2219. pr_debug("thermal node with mask:%x\n", sensor_mask);
  2220. rc = qpnp_adc_tm_activate_trip_type(
  2221. &chip->sensor[sensor_num],
  2222. ADC_TM_TRIP_LOW_COOL,
  2223. THERMAL_TRIP_ACTIVATION_DISABLED);
  2224. if (rc < 0) {
  2225. pr_err("notify error:%d\n", sensor_num);
  2226. return IRQ_HANDLED;
  2227. }
  2228. }
  2229. queue_work(chip->high_thr_wq, &chip->trigger_high_thr_work);
  2230. return IRQ_HANDLED;
  2231. }
  2232. static void qpnp_adc_tm_low_thr_work(struct work_struct *work)
  2233. {
  2234. struct qpnp_adc_tm_chip *chip = container_of(work,
  2235. struct qpnp_adc_tm_chip, trigger_low_thr_work);
  2236. int rc;
  2237. /* disable the vote if applicable */
  2238. if (chip->adc_vote_enable && chip->adc->hkadc_ldo &&
  2239. chip->adc->hkadc_ldo_ok) {
  2240. qpnp_adc_disable_voltage(chip->adc);
  2241. chip->adc_vote_enable = false;
  2242. }
  2243. pr_debug("thr:0x%x\n", chip->th_info.adc_tm_low_enable);
  2244. if (!chip->adc_tm_hc) {
  2245. rc = qpnp_adc_tm_read_status(chip);
  2246. if (rc < 0)
  2247. pr_err("adc-tm low thr work failed\n");
  2248. } else {
  2249. rc = qpnp_adc_tm_hc_read_status(chip);
  2250. if (rc < 0)
  2251. pr_err("adc-tm-hc low thr work failed\n");
  2252. }
  2253. }
  2254. static irqreturn_t qpnp_adc_tm_low_thr_isr(int irq, void *data)
  2255. {
  2256. struct qpnp_adc_tm_chip *chip = data;
  2257. u8 mode_ctl = 0, status1 = 0, sensor_mask = 0;
  2258. int rc = 0, sensor_notify_num = 0, i = 0, sensor_num = 0;
  2259. mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
  2260. /* Set measurement in single measurement mode */
  2261. qpnp_adc_tm_mode_select(chip, mode_ctl);
  2262. qpnp_adc_tm_disable(chip);
  2263. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS1, &status1, 1);
  2264. if (rc) {
  2265. pr_err("adc-tm read status1 failed\n");
  2266. return IRQ_HANDLED;
  2267. }
  2268. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS_LOW,
  2269. &chip->th_info.status_low, 1);
  2270. if (rc) {
  2271. pr_err("adc-tm-tm read status low failed with %d\n", rc);
  2272. return IRQ_HANDLED;
  2273. }
  2274. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_LOW_THR_INT_EN,
  2275. &chip->th_info.adc_tm_low_thr_set, 1);
  2276. if (rc) {
  2277. pr_err("adc-tm-tm read low thr failed with %d\n", rc);
  2278. return IRQ_HANDLED;
  2279. }
  2280. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
  2281. &chip->th_info.qpnp_adc_tm_meas_en, 1);
  2282. if (rc) {
  2283. pr_err("adc-tm-tm read status high failed with %d\n", rc);
  2284. return IRQ_HANDLED;
  2285. }
  2286. chip->th_info.adc_tm_low_enable = chip->th_info.qpnp_adc_tm_meas_en &
  2287. chip->th_info.status_low;
  2288. chip->th_info.adc_tm_low_enable &= chip->th_info.adc_tm_low_thr_set;
  2289. sensor_notify_num = chip->th_info.adc_tm_low_enable;
  2290. while (i < chip->max_channels_available) {
  2291. if ((sensor_notify_num & 0x1) == 1)
  2292. sensor_num = i;
  2293. sensor_notify_num >>= 1;
  2294. i++;
  2295. }
  2296. if (!chip->sensor[sensor_num].thermal_node) {
  2297. sensor_mask = 1 << sensor_num;
  2298. rc = qpnp_adc_tm_reg_update(chip,
  2299. QPNP_ADC_TM_LOW_THR_INT_EN,
  2300. sensor_mask, false);
  2301. if (rc < 0) {
  2302. pr_err("low threshold int read failed\n");
  2303. return IRQ_HANDLED;
  2304. }
  2305. } else {
  2306. /*
  2307. * Uses the thermal sysfs registered device to disable
  2308. * the corresponding low voltage threshold which
  2309. * is triggered by high temp
  2310. */
  2311. pr_debug("thermal node with mask:%x\n", sensor_mask);
  2312. rc = qpnp_adc_tm_activate_trip_type(
  2313. &chip->sensor[sensor_num],
  2314. ADC_TM_TRIP_HIGH_WARM,
  2315. THERMAL_TRIP_ACTIVATION_DISABLED);
  2316. if (rc < 0) {
  2317. pr_err("notify error:%d\n", sensor_num);
  2318. return IRQ_HANDLED;
  2319. }
  2320. }
  2321. queue_work(chip->low_thr_wq, &chip->trigger_low_thr_work);
  2322. return IRQ_HANDLED;
  2323. }
  2324. static int qpnp_adc_tm_rc_check_sensor_trip(struct qpnp_adc_tm_chip *chip,
  2325. u8 status_low, u8 status_high, int i,
  2326. int *sensor_low_notify_num, int *sensor_high_notify_num)
  2327. {
  2328. int rc = 0;
  2329. u8 ctl = 0, sensor_mask = 0;
  2330. if (((status_low & 0x1) == 1) || ((status_high & 0x1) == 1)) {
  2331. rc = qpnp_adc_tm_read_reg(chip,
  2332. QPNP_BTM_Mn_EN(i), &ctl, 1);
  2333. if (rc) {
  2334. pr_err("ctl read failed with %d\n", rc);
  2335. return IRQ_HANDLED;
  2336. }
  2337. if ((status_low & 0x1) && (ctl & QPNP_BTM_Mn_MEAS_EN)
  2338. && (ctl & QPNP_BTM_Mn_LOW_THR_INT_EN)) {
  2339. /* Mask the corresponding low threshold interrupt en */
  2340. if (!chip->sensor[i].thermal_node) {
  2341. rc = qpnp_adc_tm_reg_update(chip,
  2342. QPNP_BTM_Mn_EN(i),
  2343. QPNP_BTM_Mn_LOW_THR_INT_EN, false);
  2344. if (rc < 0) {
  2345. pr_err("low thr_int en failed\n");
  2346. return IRQ_HANDLED;
  2347. }
  2348. } else {
  2349. /*
  2350. * Uses the thermal sysfs registered device to disable
  2351. * the corresponding low voltage threshold which
  2352. * is triggered by high temp
  2353. */
  2354. pr_debug("thermal node with mask:%x\n", sensor_mask);
  2355. rc = qpnp_adc_tm_activate_trip_type(
  2356. &chip->sensor[i],
  2357. ADC_TM_TRIP_HIGH_WARM,
  2358. THERMAL_TRIP_ACTIVATION_DISABLED);
  2359. if (rc < 0) {
  2360. pr_err("notify error:%d\n", i);
  2361. return IRQ_HANDLED;
  2362. }
  2363. }
  2364. *sensor_low_notify_num |= (status_low & 0x1);
  2365. chip->sensor[i].low_thr_triggered = true;
  2366. }
  2367. if ((status_high & 0x1) && (ctl & QPNP_BTM_Mn_MEAS_EN) &&
  2368. (ctl & QPNP_BTM_Mn_HIGH_THR_INT_EN)) {
  2369. /* Mask the corresponding high threshold interrupt en */
  2370. if (!chip->sensor[i].thermal_node) {
  2371. rc = qpnp_adc_tm_reg_update(chip,
  2372. QPNP_BTM_Mn_EN(i),
  2373. QPNP_BTM_Mn_HIGH_THR_INT_EN, false);
  2374. if (rc < 0) {
  2375. pr_err("high thr_int en failed\n");
  2376. return IRQ_HANDLED;
  2377. }
  2378. } else {
  2379. /*
  2380. * Uses the thermal sysfs registered device to disable
  2381. * the corresponding high voltage threshold which
  2382. * is triggered by low temp
  2383. */
  2384. pr_debug("thermal node with mask:%x\n", i);
  2385. rc = qpnp_adc_tm_activate_trip_type(
  2386. &chip->sensor[i],
  2387. ADC_TM_TRIP_LOW_COOL,
  2388. THERMAL_TRIP_ACTIVATION_DISABLED);
  2389. if (rc < 0) {
  2390. pr_err("notify error:%d\n", i);
  2391. return IRQ_HANDLED;
  2392. }
  2393. }
  2394. *sensor_high_notify_num |= (status_high & 0x1);
  2395. chip->sensor[i].high_thr_triggered = true;
  2396. }
  2397. }
  2398. return rc;
  2399. }
  2400. static irqreturn_t qpnp_adc_tm_rc_thr_isr(int irq, void *data)
  2401. {
  2402. struct qpnp_adc_tm_chip *chip = data;
  2403. u8 status_low = 0, status_high = 0;
  2404. int rc = 0, sensor_low_notify_num = 0, i = 0;
  2405. int sensor_high_notify_num = 0;
  2406. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS_LOW,
  2407. &status_low, 1);
  2408. if (rc) {
  2409. pr_err("adc-tm-tm read status low failed with %d\n", rc);
  2410. return IRQ_HANDLED;
  2411. }
  2412. if (status_low)
  2413. chip->th_info.adc_tm_low_enable = status_low;
  2414. rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS_HIGH,
  2415. &status_high, 1);
  2416. if (rc) {
  2417. pr_err("adc-tm-tm read status high failed with %d\n", rc);
  2418. return IRQ_HANDLED;
  2419. }
  2420. if (status_high)
  2421. chip->th_info.adc_tm_high_enable = status_high;
  2422. while (i < chip->max_channels_available) {
  2423. rc = qpnp_adc_tm_rc_check_sensor_trip(chip,
  2424. status_low, status_high, i,
  2425. &sensor_low_notify_num,
  2426. &sensor_high_notify_num);
  2427. if (rc) {
  2428. pr_err("Sensor trip read failed\n");
  2429. return IRQ_HANDLED;
  2430. }
  2431. status_low >>= 1;
  2432. status_high >>= 1;
  2433. i++;
  2434. }
  2435. if (sensor_low_notify_num) {
  2436. pm_wakeup_event(chip->dev,
  2437. QPNP_ADC_WAKEUP_SRC_TIMEOUT_MS);
  2438. queue_work(chip->low_thr_wq, &chip->trigger_low_thr_work);
  2439. }
  2440. if (sensor_high_notify_num) {
  2441. pm_wakeup_event(chip->dev,
  2442. QPNP_ADC_WAKEUP_SRC_TIMEOUT_MS);
  2443. queue_work(chip->high_thr_wq,
  2444. &chip->trigger_high_thr_work);
  2445. }
  2446. return IRQ_HANDLED;
  2447. }
  2448. static struct thermal_zone_of_device_ops qpnp_adc_tm_thermal_ops = {
  2449. .get_temp = qpnp_adc_read_temp,
  2450. .set_trips = qpnp_adc_tm_set_trip_temp,
  2451. .set_emul_temp = qpnp_adc_tm_set_emul_temp,
  2452. };
  2453. int32_t qpnp_adc_tm_channel_measure(struct qpnp_adc_tm_chip *chip,
  2454. struct qpnp_adc_tm_btm_param *param)
  2455. {
  2456. uint32_t channel, amux_prescaling, dt_index = 0, scale_type = 0;
  2457. int rc = 0, i = 0, version = 0;
  2458. bool chan_found = false;
  2459. if (qpnp_adc_tm_is_valid(chip)) {
  2460. pr_err("chip not valid\n");
  2461. return -ENODEV;
  2462. }
  2463. if (param->threshold_notification == NULL) {
  2464. pr_debug("No notification for high/low temp??\n");
  2465. return -EINVAL;
  2466. }
  2467. mutex_lock(&chip->adc->adc_lock);
  2468. channel = param->channel;
  2469. if (channel == VSYS) {
  2470. version = qpnp_adc_get_revid_version(chip->dev);
  2471. if (version == QPNP_REV_ID_PM8950_1_0) {
  2472. pr_debug("Channel not supported\n");
  2473. rc = -EINVAL;
  2474. goto fail_unlock;
  2475. }
  2476. }
  2477. while (i < chip->max_channels_available) {
  2478. if (chip->adc->adc_channels[i].channel_num ==
  2479. channel) {
  2480. dt_index = i;
  2481. chan_found = true;
  2482. i++;
  2483. } else
  2484. i++;
  2485. }
  2486. if (!chan_found) {
  2487. pr_err("not a valid ADC_TM channel\n");
  2488. rc = -EINVAL;
  2489. goto fail_unlock;
  2490. }
  2491. rc = qpnp_adc_tm_check_revision(chip,
  2492. chip->sensor[dt_index].btm_channel_num);
  2493. if (rc < 0)
  2494. goto fail_unlock;
  2495. scale_type = chip->adc->adc_channels[dt_index].adc_scale_fn;
  2496. if (scale_type >= SCALE_RSCALE_NONE) {
  2497. rc = -EBADF;
  2498. goto fail_unlock;
  2499. }
  2500. amux_prescaling =
  2501. chip->adc->adc_channels[dt_index].chan_path_prescaling;
  2502. if (amux_prescaling >= PATH_SCALING_NONE) {
  2503. rc = -EINVAL;
  2504. goto fail_unlock;
  2505. }
  2506. pr_debug("channel:%d, scale_type:%d, dt_idx:%d",
  2507. channel, scale_type, dt_index);
  2508. param->gain_num = qpnp_vadc_amux_scaling_ratio[amux_prescaling].num;
  2509. param->gain_den = qpnp_vadc_amux_scaling_ratio[amux_prescaling].den;
  2510. param->adc_tm_hc = chip->adc_tm_hc;
  2511. param->full_scale_code = chip->adc->adc_prop->full_scale_code;
  2512. chip->adc->amux_prop->amux_channel = channel;
  2513. chip->adc->amux_prop->decimation =
  2514. chip->adc->adc_channels[dt_index].adc_decimation;
  2515. chip->adc->amux_prop->hw_settle_time =
  2516. chip->adc->adc_channels[dt_index].hw_settle_time;
  2517. chip->adc->amux_prop->fast_avg_setup =
  2518. chip->adc->adc_channels[dt_index].fast_avg_setup;
  2519. chip->adc->amux_prop->mode_sel =
  2520. ADC_OP_MEASUREMENT_INTERVAL << QPNP_OP_MODE_SHIFT;
  2521. adc_tm_rscale_fn[scale_type].chan(chip->vadc_dev, param,
  2522. &chip->adc->amux_prop->chan_prop->low_thr,
  2523. &chip->adc->amux_prop->chan_prop->high_thr);
  2524. qpnp_adc_tm_add_to_list(chip, dt_index, param,
  2525. chip->adc->amux_prop->chan_prop);
  2526. chip->adc->amux_prop->chan_prop->tm_channel_select =
  2527. chip->sensor[dt_index].btm_channel_num;
  2528. chip->adc->amux_prop->chan_prop->state_request =
  2529. param->state_request;
  2530. chip->adc->amux_prop->calib_type =
  2531. chip->adc->adc_channels[dt_index].calib_type;
  2532. if (!chip->adc_tm_hc) {
  2533. rc = qpnp_adc_tm_configure(chip, chip->adc->amux_prop);
  2534. if (rc) {
  2535. pr_err("adc-tm configure failed with %d\n", rc);
  2536. goto fail_unlock;
  2537. }
  2538. } else {
  2539. rc = qpnp_adc_tm_hc_configure(chip, chip->adc->amux_prop);
  2540. if (rc) {
  2541. pr_err("adc-tm hc configure failed with %d\n", rc);
  2542. goto fail_unlock;
  2543. }
  2544. }
  2545. chip->sensor[dt_index].scale_type = scale_type;
  2546. fail_unlock:
  2547. mutex_unlock(&chip->adc->adc_lock);
  2548. return rc;
  2549. }
  2550. EXPORT_SYMBOL(qpnp_adc_tm_channel_measure);
  2551. int32_t qpnp_adc_tm_disable_chan_meas(struct qpnp_adc_tm_chip *chip,
  2552. struct qpnp_adc_tm_btm_param *param)
  2553. {
  2554. uint32_t channel, dt_index = 0, btm_chan_num;
  2555. u8 sensor_mask = 0, mode_ctl = 0;
  2556. int rc = 0;
  2557. if (qpnp_adc_tm_is_valid(chip))
  2558. return -ENODEV;
  2559. mutex_lock(&chip->adc->adc_lock);
  2560. if (!chip->adc_tm_hc) {
  2561. /* Set measurement in single measurement mode */
  2562. mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
  2563. rc = qpnp_adc_tm_mode_select(chip, mode_ctl);
  2564. if (rc < 0) {
  2565. pr_err("adc-tm single mode select failed\n");
  2566. goto fail;
  2567. }
  2568. }
  2569. /* Disable bank */
  2570. rc = qpnp_adc_tm_disable(chip);
  2571. if (rc < 0) {
  2572. pr_err("adc-tm disable failed\n");
  2573. goto fail;
  2574. }
  2575. if (!chip->adc_tm_hc) {
  2576. /* Check if a conversion is in progress */
  2577. rc = qpnp_adc_tm_req_sts_check(chip);
  2578. if (rc < 0) {
  2579. pr_err("adc-tm req_sts check failed\n");
  2580. goto fail;
  2581. }
  2582. }
  2583. channel = param->channel;
  2584. while ((chip->adc->adc_channels[dt_index].channel_num
  2585. != channel) && (dt_index < chip->max_channels_available))
  2586. dt_index++;
  2587. if (dt_index >= chip->max_channels_available) {
  2588. pr_err("not a valid ADC_TMN channel\n");
  2589. rc = -EINVAL;
  2590. goto fail;
  2591. }
  2592. btm_chan_num = chip->sensor[dt_index].btm_channel_num;
  2593. if (!chip->adc_tm_hc) {
  2594. sensor_mask = 1 << chip->sensor[dt_index].sensor_num;
  2595. rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_TM_LOW_THR_INT_EN,
  2596. sensor_mask, false);
  2597. if (rc < 0) {
  2598. pr_err("high threshold int enable failed\n");
  2599. goto fail;
  2600. }
  2601. rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
  2602. sensor_mask, false);
  2603. if (rc < 0) {
  2604. pr_err("multi measurement en failed\n");
  2605. goto fail;
  2606. }
  2607. } else {
  2608. rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_num),
  2609. QPNP_BTM_Mn_HIGH_THR_INT_EN, false);
  2610. if (rc < 0) {
  2611. pr_err("high thr disable err:%d\n", btm_chan_num);
  2612. goto fail;
  2613. }
  2614. rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_num),
  2615. QPNP_BTM_Mn_LOW_THR_INT_EN, false);
  2616. if (rc < 0) {
  2617. pr_err("low thr disable err:%d\n", btm_chan_num);
  2618. goto fail;
  2619. }
  2620. rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_num),
  2621. QPNP_BTM_Mn_MEAS_EN, false);
  2622. if (rc < 0) {
  2623. pr_err("multi measurement disable failed\n");
  2624. goto fail;
  2625. }
  2626. }
  2627. rc = qpnp_adc_tm_enable_if_channel_meas(chip);
  2628. if (rc < 0)
  2629. pr_err("re-enabling measurement failed\n");
  2630. fail:
  2631. mutex_unlock(&chip->adc->adc_lock);
  2632. return rc;
  2633. }
  2634. EXPORT_SYMBOL(qpnp_adc_tm_disable_chan_meas);
  2635. struct qpnp_adc_tm_chip *qpnp_get_adc_tm(struct device *dev, const char *name)
  2636. {
  2637. struct qpnp_adc_tm_chip *chip;
  2638. struct device_node *node = NULL;
  2639. char prop_name[QPNP_MAX_PROP_NAME_LEN];
  2640. snprintf(prop_name, QPNP_MAX_PROP_NAME_LEN, "qcom,%s-adc_tm", name);
  2641. node = of_parse_phandle(dev->of_node, prop_name, 0);
  2642. if (node == NULL)
  2643. return ERR_PTR(-ENODEV);
  2644. list_for_each_entry(chip, &qpnp_adc_tm_device_list, list)
  2645. if (chip->adc->pdev->dev.of_node == node)
  2646. return chip;
  2647. return ERR_PTR(-EPROBE_DEFER);
  2648. }
  2649. EXPORT_SYMBOL(qpnp_get_adc_tm);
  2650. static int qpnp_adc_tm_initial_setup(struct qpnp_adc_tm_chip *chip)
  2651. {
  2652. u8 thr_init = 0;
  2653. int rc = 0;
  2654. rc = qpnp_adc_tm_write_reg(chip, QPNP_ADC_TM_HIGH_THR_INT_EN,
  2655. thr_init, 1);
  2656. if (rc < 0) {
  2657. pr_err("high thr init failed\n");
  2658. return rc;
  2659. }
  2660. rc = qpnp_adc_tm_write_reg(chip, QPNP_ADC_TM_LOW_THR_INT_EN,
  2661. thr_init, 1);
  2662. if (rc < 0) {
  2663. pr_err("low thr init failed\n");
  2664. return rc;
  2665. }
  2666. rc = qpnp_adc_tm_write_reg(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
  2667. thr_init, 1);
  2668. if (rc < 0) {
  2669. pr_err("multi meas en failed\n");
  2670. return rc;
  2671. }
  2672. return rc;
  2673. }
  2674. static const struct of_device_id qpnp_adc_tm_match_table[] = {
  2675. { .compatible = "qcom,qpnp-adc-tm" },
  2676. { .compatible = "qcom,qpnp-adc-tm-hc" },
  2677. { .compatible = "qcom,qpnp-adc-tm-hc-pm5" },
  2678. {}
  2679. };
  2680. static int qpnp_adc_tm_probe(struct platform_device *pdev)
  2681. {
  2682. struct device_node *node = pdev->dev.of_node, *child;
  2683. struct qpnp_adc_tm_chip *chip;
  2684. struct qpnp_adc_drv *adc_qpnp;
  2685. int32_t count_adc_channel_list = 0, rc, sen_idx = 0, i = 0;
  2686. bool thermal_node = false;
  2687. const struct of_device_id *id;
  2688. for_each_child_of_node(node, child)
  2689. count_adc_channel_list++;
  2690. if (!count_adc_channel_list) {
  2691. pr_err("No channel listing\n");
  2692. return -EINVAL;
  2693. }
  2694. id = of_match_node(qpnp_adc_tm_match_table, node);
  2695. if (id == NULL) {
  2696. pr_err("qpnp_adc_tm_match of_node prop not present\n");
  2697. return -ENODEV;
  2698. }
  2699. chip = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_adc_tm_chip) +
  2700. (count_adc_channel_list *
  2701. sizeof(struct qpnp_adc_tm_sensor)),
  2702. GFP_KERNEL);
  2703. if (!chip)
  2704. return -ENOMEM;
  2705. list_add(&chip->list, &qpnp_adc_tm_device_list);
  2706. chip->max_channels_available = count_adc_channel_list;
  2707. adc_qpnp = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_adc_drv),
  2708. GFP_KERNEL);
  2709. if (!adc_qpnp) {
  2710. rc = -ENOMEM;
  2711. goto fail;
  2712. }
  2713. chip->dev = &(pdev->dev);
  2714. chip->adc = adc_qpnp;
  2715. chip->adc->regmap = dev_get_regmap(pdev->dev.parent, NULL);
  2716. if (!chip->adc->regmap) {
  2717. dev_err(&pdev->dev, "Couldn't get parent's regmap\n");
  2718. rc = -EINVAL;
  2719. goto fail;
  2720. }
  2721. if (of_device_is_compatible(node, "qcom,qpnp-adc-tm-hc")) {
  2722. chip->adc_tm_hc = true;
  2723. chip->adc->adc_hc = true;
  2724. }
  2725. rc = qpnp_adc_get_devicetree_data(pdev, chip->adc);
  2726. if (rc) {
  2727. dev_err(&pdev->dev, "failed to read device tree\n");
  2728. goto fail;
  2729. }
  2730. mutex_init(&chip->adc->adc_lock);
  2731. /* Register the ADC peripheral interrupt */
  2732. if (!chip->adc_tm_hc) {
  2733. chip->adc->adc_high_thr_irq = platform_get_irq_byname(pdev,
  2734. "high-thr-en-set");
  2735. if (chip->adc->adc_high_thr_irq < 0) {
  2736. pr_err("Invalid irq\n");
  2737. rc = -ENXIO;
  2738. goto fail;
  2739. }
  2740. chip->adc->adc_low_thr_irq = platform_get_irq_byname(pdev,
  2741. "low-thr-en-set");
  2742. if (chip->adc->adc_low_thr_irq < 0) {
  2743. pr_err("Invalid irq\n");
  2744. rc = -ENXIO;
  2745. goto fail;
  2746. }
  2747. }
  2748. chip->vadc_dev = qpnp_get_vadc(&pdev->dev, "adc_tm");
  2749. if (IS_ERR(chip->vadc_dev)) {
  2750. rc = PTR_ERR(chip->vadc_dev);
  2751. if (rc != -EPROBE_DEFER)
  2752. pr_err("vadc property missing, rc=%d\n", rc);
  2753. goto fail;
  2754. }
  2755. chip->adc_tm_recalib_check = of_property_read_bool(node,
  2756. "qcom,adc-tm-recalib-check");
  2757. for_each_child_of_node(node, child) {
  2758. char name[25];
  2759. int btm_channel_num, timer_select = 0;
  2760. rc = of_property_read_u32(child,
  2761. "qcom,btm-channel-number", &btm_channel_num);
  2762. if (rc) {
  2763. pr_err("Invalid btm channel number\n");
  2764. goto fail;
  2765. }
  2766. rc = of_property_read_u32(child,
  2767. "qcom,meas-interval-timer-idx", &timer_select);
  2768. if (rc) {
  2769. pr_debug("Default to timer2 with interval of 1 sec\n");
  2770. chip->sensor[sen_idx].timer_select =
  2771. ADC_MEAS_TIMER_SELECT2;
  2772. chip->sensor[sen_idx].meas_interval =
  2773. ADC_MEAS2_INTERVAL_1S;
  2774. } else {
  2775. if (timer_select >= ADC_MEAS_TIMER_NUM) {
  2776. pr_err("Invalid timer selection number\n");
  2777. goto fail;
  2778. }
  2779. chip->sensor[sen_idx].timer_select = timer_select;
  2780. if (timer_select == ADC_MEAS_TIMER_SELECT1)
  2781. chip->sensor[sen_idx].meas_interval =
  2782. ADC_MEAS1_INTERVAL_3P9MS;
  2783. else if (timer_select == ADC_MEAS_TIMER_SELECT3)
  2784. chip->sensor[sen_idx].meas_interval =
  2785. ADC_MEAS3_INTERVAL_4S;
  2786. else if (timer_select == ADC_MEAS_TIMER_SELECT2)
  2787. chip->sensor[sen_idx].meas_interval =
  2788. ADC_MEAS2_INTERVAL_1S;
  2789. }
  2790. chip->sensor[sen_idx].btm_channel_num = btm_channel_num;
  2791. chip->sensor[sen_idx].vadc_channel_num =
  2792. chip->adc->adc_channels[sen_idx].channel_num;
  2793. chip->sensor[sen_idx].sensor_num = sen_idx;
  2794. chip->sensor[sen_idx].chip = chip;
  2795. pr_debug("btm_chan:%x, vadc_chan:%x\n", btm_channel_num,
  2796. chip->adc->adc_channels[sen_idx].channel_num);
  2797. thermal_node = of_property_read_bool(child,
  2798. "qcom,thermal-node");
  2799. if (thermal_node) {
  2800. /* Register with the thermal zone */
  2801. pr_debug("thermal node%x\n", btm_channel_num);
  2802. chip->sensor[sen_idx].mode = THERMAL_DEVICE_DISABLED;
  2803. chip->sensor[sen_idx].thermal_node = true;
  2804. snprintf(name, sizeof(name), "%s",
  2805. chip->adc->adc_channels[sen_idx].name);
  2806. chip->sensor[sen_idx].low_thr =
  2807. QPNP_ADC_TM_M0_LOW_THR;
  2808. chip->sensor[sen_idx].high_thr =
  2809. QPNP_ADC_TM_M0_HIGH_THR;
  2810. chip->sensor[sen_idx].emul_temperature = 0;
  2811. chip->sensor[sen_idx].tz_dev =
  2812. devm_thermal_zone_of_sensor_register(
  2813. chip->dev,
  2814. chip->sensor[sen_idx].vadc_channel_num,
  2815. &chip->sensor[sen_idx],
  2816. &qpnp_adc_tm_thermal_ops);
  2817. if (IS_ERR(chip->sensor[sen_idx].tz_dev))
  2818. pr_err("thermal device register failed.\n");
  2819. }
  2820. chip->sensor[sen_idx].req_wq = alloc_workqueue(
  2821. "qpnp_adc_notify_wq", WQ_HIGHPRI, 0);
  2822. if (!chip->sensor[sen_idx].req_wq) {
  2823. pr_err("Requesting priority wq failed\n");
  2824. goto fail;
  2825. }
  2826. INIT_WORK(&chip->sensor[sen_idx].work, notify_adc_tm_fn);
  2827. INIT_LIST_HEAD(&chip->sensor[sen_idx].thr_list);
  2828. sen_idx++;
  2829. }
  2830. chip->high_thr_wq = alloc_workqueue("qpnp_adc_tm_high_thr_wq",
  2831. WQ_HIGHPRI, 0);
  2832. if (!chip->high_thr_wq) {
  2833. pr_err("Requesting high thr priority wq failed\n");
  2834. goto fail;
  2835. }
  2836. chip->low_thr_wq = alloc_workqueue("qpnp_adc_tm_low_thr_wq",
  2837. WQ_HIGHPRI, 0);
  2838. if (!chip->low_thr_wq) {
  2839. pr_err("Requesting low thr priority wq failed\n");
  2840. goto fail;
  2841. }
  2842. chip->thr_wq = alloc_workqueue("qpnp_adc_tm_thr_wq",
  2843. WQ_HIGHPRI, 0);
  2844. if (!chip->thr_wq) {
  2845. pr_err("Requesting thr priority wq failed\n");
  2846. goto fail;
  2847. }
  2848. INIT_WORK(&chip->trigger_high_thr_work, qpnp_adc_tm_high_thr_work);
  2849. INIT_WORK(&chip->trigger_low_thr_work, qpnp_adc_tm_low_thr_work);
  2850. if (!chip->adc_tm_hc) {
  2851. rc = qpnp_adc_tm_initial_setup(chip);
  2852. if (rc)
  2853. goto fail;
  2854. rc = devm_request_irq(&pdev->dev, chip->adc->adc_high_thr_irq,
  2855. qpnp_adc_tm_high_thr_isr,
  2856. IRQF_TRIGGER_RISING, "qpnp_adc_tm_high_interrupt", chip);
  2857. if (rc) {
  2858. dev_err(&pdev->dev, "failed to request adc irq\n");
  2859. goto fail;
  2860. } else {
  2861. enable_irq_wake(chip->adc->adc_high_thr_irq);
  2862. }
  2863. rc = devm_request_irq(&pdev->dev, chip->adc->adc_low_thr_irq,
  2864. qpnp_adc_tm_low_thr_isr,
  2865. IRQF_TRIGGER_RISING,
  2866. "qpnp_adc_tm_low_interrupt", chip);
  2867. if (rc) {
  2868. dev_err(&pdev->dev, "failed to request adc irq\n");
  2869. goto fail;
  2870. } else {
  2871. enable_irq_wake(chip->adc->adc_low_thr_irq);
  2872. }
  2873. } else {
  2874. rc = devm_request_irq(&pdev->dev, chip->adc->adc_irq_eoc,
  2875. qpnp_adc_tm_rc_thr_isr,
  2876. IRQF_TRIGGER_HIGH, "qpnp_adc_tm_interrupt", chip);
  2877. if (rc)
  2878. dev_err(&pdev->dev, "failed to request adc irq\n");
  2879. else
  2880. enable_irq_wake(chip->adc->adc_irq_eoc);
  2881. }
  2882. chip->adc_vote_enable = false;
  2883. dev_set_drvdata(&pdev->dev, chip);
  2884. spin_lock_init(&chip->th_info.adc_tm_low_lock);
  2885. spin_lock_init(&chip->th_info.adc_tm_high_lock);
  2886. pr_debug("OK\n");
  2887. return 0;
  2888. fail:
  2889. for_each_child_of_node(node, child) {
  2890. thermal_node = of_property_read_bool(child,
  2891. "qcom,thermal-node");
  2892. if (thermal_node) {
  2893. thermal_zone_device_unregister(chip->sensor[i].tz_dev);
  2894. if (chip->sensor[i].req_wq)
  2895. destroy_workqueue(chip->sensor[sen_idx].req_wq);
  2896. }
  2897. }
  2898. if (chip->high_thr_wq)
  2899. destroy_workqueue(chip->high_thr_wq);
  2900. if (chip->low_thr_wq)
  2901. destroy_workqueue(chip->low_thr_wq);
  2902. list_del(&chip->list);
  2903. dev_set_drvdata(&pdev->dev, NULL);
  2904. return rc;
  2905. }
  2906. static int qpnp_adc_tm_remove(struct platform_device *pdev)
  2907. {
  2908. struct qpnp_adc_tm_chip *chip = dev_get_drvdata(&pdev->dev);
  2909. struct device_node *node = pdev->dev.of_node, *child;
  2910. int i = 0;
  2911. for_each_child_of_node(node, child) {
  2912. if (chip->sensor[i].req_wq)
  2913. destroy_workqueue(chip->sensor[i].req_wq);
  2914. i++;
  2915. }
  2916. if (chip->high_thr_wq)
  2917. destroy_workqueue(chip->high_thr_wq);
  2918. if (chip->low_thr_wq)
  2919. destroy_workqueue(chip->low_thr_wq);
  2920. if (chip->adc->hkadc_ldo && chip->adc->hkadc_ldo_ok)
  2921. qpnp_adc_free_voltage_resource(chip->adc);
  2922. dev_set_drvdata(&pdev->dev, NULL);
  2923. return 0;
  2924. }
  2925. static void qpnp_adc_tm_shutdown(struct platform_device *pdev)
  2926. {
  2927. struct qpnp_adc_tm_chip *chip = dev_get_drvdata(&pdev->dev);
  2928. int rc = 0, i = 0;
  2929. /* Disable bank */
  2930. rc = qpnp_adc_tm_disable(chip);
  2931. if (rc < 0)
  2932. pr_err("adc-tm disable failed\n");
  2933. for (i = 0; i < QPNP_BTM_CHANNELS; i++) {
  2934. rc = qpnp_adc_tm_reg_update(chip,
  2935. QPNP_BTM_Mn_EN(i),
  2936. QPNP_BTM_Mn_MEAS_EN, false);
  2937. if (rc < 0)
  2938. pr_err("multi measurement disable failed\n");
  2939. }
  2940. }
  2941. static int qpnp_adc_tm_suspend_noirq(struct device *dev)
  2942. {
  2943. struct qpnp_adc_tm_chip *chip = dev_get_drvdata(dev);
  2944. struct device_node *node = dev->of_node, *child;
  2945. int i = 0;
  2946. flush_workqueue(chip->high_thr_wq);
  2947. flush_workqueue(chip->low_thr_wq);
  2948. for_each_child_of_node(node, child) {
  2949. if (chip->sensor[i].req_wq) {
  2950. pr_debug("flushing queue for sensor %d\n", i);
  2951. flush_workqueue(chip->sensor[i].req_wq);
  2952. }
  2953. i++;
  2954. }
  2955. return 0;
  2956. }
  2957. static const struct dev_pm_ops qpnp_adc_tm_pm_ops = {
  2958. .suspend_noirq = qpnp_adc_tm_suspend_noirq,
  2959. };
  2960. static struct platform_driver qpnp_adc_tm_driver = {
  2961. .driver = {
  2962. .name = "qcom,qpnp-adc-tm",
  2963. .of_match_table = qpnp_adc_tm_match_table,
  2964. .pm = &qpnp_adc_tm_pm_ops,
  2965. },
  2966. .probe = qpnp_adc_tm_probe,
  2967. .remove = qpnp_adc_tm_remove,
  2968. .shutdown = qpnp_adc_tm_shutdown,
  2969. };
  2970. static int __init qpnp_adc_tm_init(void)
  2971. {
  2972. return platform_driver_register(&qpnp_adc_tm_driver);
  2973. }
  2974. module_init(qpnp_adc_tm_init);
  2975. static void __exit qpnp_adc_tm_exit(void)
  2976. {
  2977. platform_driver_unregister(&qpnp_adc_tm_driver);
  2978. }
  2979. module_exit(qpnp_adc_tm_exit);
  2980. MODULE_DESCRIPTION("QPNP PMIC ADC Threshold Monitoring driver");
  2981. MODULE_LICENSE("GPL v2");