8250_pci.c 149 KB

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  1. /*
  2. * Probe module for 8250/16550-type PCI serial ports.
  3. *
  4. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5. *
  6. * Copyright (C) 2001 Russell King, All Rights Reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License.
  11. */
  12. #undef DEBUG
  13. #include <linux/module.h>
  14. #include <linux/pci.h>
  15. #include <linux/string.h>
  16. #include <linux/kernel.h>
  17. #include <linux/slab.h>
  18. #include <linux/delay.h>
  19. #include <linux/tty.h>
  20. #include <linux/serial_reg.h>
  21. #include <linux/serial_core.h>
  22. #include <linux/8250_pci.h>
  23. #include <linux/bitops.h>
  24. #include <asm/byteorder.h>
  25. #include <asm/io.h>
  26. #include "8250.h"
  27. /*
  28. * init function returns:
  29. * > 0 - number of ports
  30. * = 0 - use board->num_ports
  31. * < 0 - error
  32. */
  33. struct pci_serial_quirk {
  34. u32 vendor;
  35. u32 device;
  36. u32 subvendor;
  37. u32 subdevice;
  38. int (*probe)(struct pci_dev *dev);
  39. int (*init)(struct pci_dev *dev);
  40. int (*setup)(struct serial_private *,
  41. const struct pciserial_board *,
  42. struct uart_8250_port *, int);
  43. void (*exit)(struct pci_dev *dev);
  44. };
  45. #define PCI_NUM_BAR_RESOURCES 6
  46. struct serial_private {
  47. struct pci_dev *dev;
  48. unsigned int nr;
  49. struct pci_serial_quirk *quirk;
  50. const struct pciserial_board *board;
  51. int line[0];
  52. };
  53. static int pci_default_setup(struct serial_private*,
  54. const struct pciserial_board*, struct uart_8250_port *, int);
  55. static void moan_device(const char *str, struct pci_dev *dev)
  56. {
  57. dev_err(&dev->dev,
  58. "%s: %s\n"
  59. "Please send the output of lspci -vv, this\n"
  60. "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  61. "manufacturer and name of serial board or\n"
  62. "modem board to <[email protected]>.\n",
  63. pci_name(dev), str, dev->vendor, dev->device,
  64. dev->subsystem_vendor, dev->subsystem_device);
  65. }
  66. static int
  67. setup_port(struct serial_private *priv, struct uart_8250_port *port,
  68. int bar, int offset, int regshift)
  69. {
  70. struct pci_dev *dev = priv->dev;
  71. if (bar >= PCI_NUM_BAR_RESOURCES)
  72. return -EINVAL;
  73. if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  74. if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
  75. return -ENOMEM;
  76. port->port.iotype = UPIO_MEM;
  77. port->port.iobase = 0;
  78. port->port.mapbase = pci_resource_start(dev, bar) + offset;
  79. port->port.membase = pcim_iomap_table(dev)[bar] + offset;
  80. port->port.regshift = regshift;
  81. } else {
  82. port->port.iotype = UPIO_PORT;
  83. port->port.iobase = pci_resource_start(dev, bar) + offset;
  84. port->port.mapbase = 0;
  85. port->port.membase = NULL;
  86. port->port.regshift = 0;
  87. }
  88. return 0;
  89. }
  90. /*
  91. * ADDI-DATA GmbH communication cards <[email protected]>
  92. */
  93. static int addidata_apci7800_setup(struct serial_private *priv,
  94. const struct pciserial_board *board,
  95. struct uart_8250_port *port, int idx)
  96. {
  97. unsigned int bar = 0, offset = board->first_offset;
  98. bar = FL_GET_BASE(board->flags);
  99. if (idx < 2) {
  100. offset += idx * board->uart_offset;
  101. } else if ((idx >= 2) && (idx < 4)) {
  102. bar += 1;
  103. offset += ((idx - 2) * board->uart_offset);
  104. } else if ((idx >= 4) && (idx < 6)) {
  105. bar += 2;
  106. offset += ((idx - 4) * board->uart_offset);
  107. } else if (idx >= 6) {
  108. bar += 3;
  109. offset += ((idx - 6) * board->uart_offset);
  110. }
  111. return setup_port(priv, port, bar, offset, board->reg_shift);
  112. }
  113. /*
  114. * AFAVLAB uses a different mixture of BARs and offsets
  115. * Not that ugly ;) -- HW
  116. */
  117. static int
  118. afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
  119. struct uart_8250_port *port, int idx)
  120. {
  121. unsigned int bar, offset = board->first_offset;
  122. bar = FL_GET_BASE(board->flags);
  123. if (idx < 4)
  124. bar += idx;
  125. else {
  126. bar = 4;
  127. offset += (idx - 4) * board->uart_offset;
  128. }
  129. return setup_port(priv, port, bar, offset, board->reg_shift);
  130. }
  131. /*
  132. * HP's Remote Management Console. The Diva chip came in several
  133. * different versions. N-class, L2000 and A500 have two Diva chips, each
  134. * with 3 UARTs (the third UART on the second chip is unused). Superdome
  135. * and Keystone have one Diva chip with 3 UARTs. Some later machines have
  136. * one Diva chip, but it has been expanded to 5 UARTs.
  137. */
  138. static int pci_hp_diva_init(struct pci_dev *dev)
  139. {
  140. int rc = 0;
  141. switch (dev->subsystem_device) {
  142. case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
  143. case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
  144. case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
  145. case PCI_DEVICE_ID_HP_DIVA_EVEREST:
  146. rc = 3;
  147. break;
  148. case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
  149. rc = 2;
  150. break;
  151. case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
  152. rc = 4;
  153. break;
  154. case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
  155. case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
  156. rc = 1;
  157. break;
  158. }
  159. return rc;
  160. }
  161. /*
  162. * HP's Diva chip puts the 4th/5th serial port further out, and
  163. * some serial ports are supposed to be hidden on certain models.
  164. */
  165. static int
  166. pci_hp_diva_setup(struct serial_private *priv,
  167. const struct pciserial_board *board,
  168. struct uart_8250_port *port, int idx)
  169. {
  170. unsigned int offset = board->first_offset;
  171. unsigned int bar = FL_GET_BASE(board->flags);
  172. switch (priv->dev->subsystem_device) {
  173. case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
  174. if (idx == 3)
  175. idx++;
  176. break;
  177. case PCI_DEVICE_ID_HP_DIVA_EVEREST:
  178. if (idx > 0)
  179. idx++;
  180. if (idx > 2)
  181. idx++;
  182. break;
  183. }
  184. if (idx > 2)
  185. offset = 0x18;
  186. offset += idx * board->uart_offset;
  187. return setup_port(priv, port, bar, offset, board->reg_shift);
  188. }
  189. /*
  190. * Added for EKF Intel i960 serial boards
  191. */
  192. static int pci_inteli960ni_init(struct pci_dev *dev)
  193. {
  194. u32 oldval;
  195. if (!(dev->subsystem_device & 0x1000))
  196. return -ENODEV;
  197. /* is firmware started? */
  198. pci_read_config_dword(dev, 0x44, &oldval);
  199. if (oldval == 0x00001000L) { /* RESET value */
  200. dev_dbg(&dev->dev, "Local i960 firmware missing\n");
  201. return -ENODEV;
  202. }
  203. return 0;
  204. }
  205. /*
  206. * Some PCI serial cards using the PLX 9050 PCI interface chip require
  207. * that the card interrupt be explicitly enabled or disabled. This
  208. * seems to be mainly needed on card using the PLX which also use I/O
  209. * mapped memory.
  210. */
  211. static int pci_plx9050_init(struct pci_dev *dev)
  212. {
  213. u8 irq_config;
  214. void __iomem *p;
  215. if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
  216. moan_device("no memory in bar 0", dev);
  217. return 0;
  218. }
  219. irq_config = 0x41;
  220. if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
  221. dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
  222. irq_config = 0x43;
  223. if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
  224. (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
  225. /*
  226. * As the megawolf cards have the int pins active
  227. * high, and have 2 UART chips, both ints must be
  228. * enabled on the 9050. Also, the UARTS are set in
  229. * 16450 mode by default, so we have to enable the
  230. * 16C950 'enhanced' mode so that we can use the
  231. * deep FIFOs
  232. */
  233. irq_config = 0x5b;
  234. /*
  235. * enable/disable interrupts
  236. */
  237. p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
  238. if (p == NULL)
  239. return -ENOMEM;
  240. writel(irq_config, p + 0x4c);
  241. /*
  242. * Read the register back to ensure that it took effect.
  243. */
  244. readl(p + 0x4c);
  245. iounmap(p);
  246. return 0;
  247. }
  248. static void pci_plx9050_exit(struct pci_dev *dev)
  249. {
  250. u8 __iomem *p;
  251. if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
  252. return;
  253. /*
  254. * disable interrupts
  255. */
  256. p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
  257. if (p != NULL) {
  258. writel(0, p + 0x4c);
  259. /*
  260. * Read the register back to ensure that it took effect.
  261. */
  262. readl(p + 0x4c);
  263. iounmap(p);
  264. }
  265. }
  266. #define NI8420_INT_ENABLE_REG 0x38
  267. #define NI8420_INT_ENABLE_BIT 0x2000
  268. static void pci_ni8420_exit(struct pci_dev *dev)
  269. {
  270. void __iomem *p;
  271. unsigned int bar = 0;
  272. if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
  273. moan_device("no memory in bar", dev);
  274. return;
  275. }
  276. p = pci_ioremap_bar(dev, bar);
  277. if (p == NULL)
  278. return;
  279. /* Disable the CPU Interrupt */
  280. writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
  281. p + NI8420_INT_ENABLE_REG);
  282. iounmap(p);
  283. }
  284. /* MITE registers */
  285. #define MITE_IOWBSR1 0xc4
  286. #define MITE_IOWCR1 0xf4
  287. #define MITE_LCIMR1 0x08
  288. #define MITE_LCIMR2 0x10
  289. #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
  290. static void pci_ni8430_exit(struct pci_dev *dev)
  291. {
  292. void __iomem *p;
  293. unsigned int bar = 0;
  294. if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
  295. moan_device("no memory in bar", dev);
  296. return;
  297. }
  298. p = pci_ioremap_bar(dev, bar);
  299. if (p == NULL)
  300. return;
  301. /* Disable the CPU Interrupt */
  302. writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
  303. iounmap(p);
  304. }
  305. /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
  306. static int
  307. sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
  308. struct uart_8250_port *port, int idx)
  309. {
  310. unsigned int bar, offset = board->first_offset;
  311. bar = 0;
  312. if (idx < 4) {
  313. /* first four channels map to 0, 0x100, 0x200, 0x300 */
  314. offset += idx * board->uart_offset;
  315. } else if (idx < 8) {
  316. /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
  317. offset += idx * board->uart_offset + 0xC00;
  318. } else /* we have only 8 ports on PMC-OCTALPRO */
  319. return 1;
  320. return setup_port(priv, port, bar, offset, board->reg_shift);
  321. }
  322. /*
  323. * This does initialization for PMC OCTALPRO cards:
  324. * maps the device memory, resets the UARTs (needed, bc
  325. * if the module is removed and inserted again, the card
  326. * is in the sleep mode) and enables global interrupt.
  327. */
  328. /* global control register offset for SBS PMC-OctalPro */
  329. #define OCT_REG_CR_OFF 0x500
  330. static int sbs_init(struct pci_dev *dev)
  331. {
  332. u8 __iomem *p;
  333. p = pci_ioremap_bar(dev, 0);
  334. if (p == NULL)
  335. return -ENOMEM;
  336. /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
  337. writeb(0x10, p + OCT_REG_CR_OFF);
  338. udelay(50);
  339. writeb(0x0, p + OCT_REG_CR_OFF);
  340. /* Set bit-2 (INTENABLE) of Control Register */
  341. writeb(0x4, p + OCT_REG_CR_OFF);
  342. iounmap(p);
  343. return 0;
  344. }
  345. /*
  346. * Disables the global interrupt of PMC-OctalPro
  347. */
  348. static void sbs_exit(struct pci_dev *dev)
  349. {
  350. u8 __iomem *p;
  351. p = pci_ioremap_bar(dev, 0);
  352. /* FIXME: What if resource_len < OCT_REG_CR_OFF */
  353. if (p != NULL)
  354. writeb(0, p + OCT_REG_CR_OFF);
  355. iounmap(p);
  356. }
  357. /*
  358. * SIIG serial cards have an PCI interface chip which also controls
  359. * the UART clocking frequency. Each UART can be clocked independently
  360. * (except cards equipped with 4 UARTs) and initial clocking settings
  361. * are stored in the EEPROM chip. It can cause problems because this
  362. * version of serial driver doesn't support differently clocked UART's
  363. * on single PCI card. To prevent this, initialization functions set
  364. * high frequency clocking for all UART's on given card. It is safe (I
  365. * hope) because it doesn't touch EEPROM settings to prevent conflicts
  366. * with other OSes (like M$ DOS).
  367. *
  368. * SIIG support added by Andrey Panin <[email protected]>, 10/1999
  369. *
  370. * There is two family of SIIG serial cards with different PCI
  371. * interface chip and different configuration methods:
  372. * - 10x cards have control registers in IO and/or memory space;
  373. * - 20x cards have control registers in standard PCI configuration space.
  374. *
  375. * Note: all 10x cards have PCI device ids 0x10..
  376. * all 20x cards have PCI device ids 0x20..
  377. *
  378. * There are also Quartet Serial cards which use Oxford Semiconductor
  379. * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
  380. *
  381. * Note: some SIIG cards are probed by the parport_serial object.
  382. */
  383. #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
  384. #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
  385. static int pci_siig10x_init(struct pci_dev *dev)
  386. {
  387. u16 data;
  388. void __iomem *p;
  389. switch (dev->device & 0xfff8) {
  390. case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
  391. data = 0xffdf;
  392. break;
  393. case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
  394. data = 0xf7ff;
  395. break;
  396. default: /* 1S1P, 4S */
  397. data = 0xfffb;
  398. break;
  399. }
  400. p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
  401. if (p == NULL)
  402. return -ENOMEM;
  403. writew(readw(p + 0x28) & data, p + 0x28);
  404. readw(p + 0x28);
  405. iounmap(p);
  406. return 0;
  407. }
  408. #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
  409. #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
  410. static int pci_siig20x_init(struct pci_dev *dev)
  411. {
  412. u8 data;
  413. /* Change clock frequency for the first UART. */
  414. pci_read_config_byte(dev, 0x6f, &data);
  415. pci_write_config_byte(dev, 0x6f, data & 0xef);
  416. /* If this card has 2 UART, we have to do the same with second UART. */
  417. if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
  418. ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
  419. pci_read_config_byte(dev, 0x73, &data);
  420. pci_write_config_byte(dev, 0x73, data & 0xef);
  421. }
  422. return 0;
  423. }
  424. static int pci_siig_init(struct pci_dev *dev)
  425. {
  426. unsigned int type = dev->device & 0xff00;
  427. if (type == 0x1000)
  428. return pci_siig10x_init(dev);
  429. else if (type == 0x2000)
  430. return pci_siig20x_init(dev);
  431. moan_device("Unknown SIIG card", dev);
  432. return -ENODEV;
  433. }
  434. static int pci_siig_setup(struct serial_private *priv,
  435. const struct pciserial_board *board,
  436. struct uart_8250_port *port, int idx)
  437. {
  438. unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
  439. if (idx > 3) {
  440. bar = 4;
  441. offset = (idx - 4) * 8;
  442. }
  443. return setup_port(priv, port, bar, offset, 0);
  444. }
  445. /*
  446. * Timedia has an explosion of boards, and to avoid the PCI table from
  447. * growing *huge*, we use this function to collapse some 70 entries
  448. * in the PCI table into one, for sanity's and compactness's sake.
  449. */
  450. static const unsigned short timedia_single_port[] = {
  451. 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
  452. };
  453. static const unsigned short timedia_dual_port[] = {
  454. 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
  455. 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
  456. 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
  457. 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
  458. 0xD079, 0
  459. };
  460. static const unsigned short timedia_quad_port[] = {
  461. 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
  462. 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
  463. 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
  464. 0xB157, 0
  465. };
  466. static const unsigned short timedia_eight_port[] = {
  467. 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
  468. 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
  469. };
  470. static const struct timedia_struct {
  471. int num;
  472. const unsigned short *ids;
  473. } timedia_data[] = {
  474. { 1, timedia_single_port },
  475. { 2, timedia_dual_port },
  476. { 4, timedia_quad_port },
  477. { 8, timedia_eight_port }
  478. };
  479. /*
  480. * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
  481. * listing them individually, this driver merely grabs them all with
  482. * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
  483. * and should be left free to be claimed by parport_serial instead.
  484. */
  485. static int pci_timedia_probe(struct pci_dev *dev)
  486. {
  487. /*
  488. * Check the third digit of the subdevice ID
  489. * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
  490. */
  491. if ((dev->subsystem_device & 0x00f0) >= 0x70) {
  492. dev_info(&dev->dev,
  493. "ignoring Timedia subdevice %04x for parport_serial\n",
  494. dev->subsystem_device);
  495. return -ENODEV;
  496. }
  497. return 0;
  498. }
  499. static int pci_timedia_init(struct pci_dev *dev)
  500. {
  501. const unsigned short *ids;
  502. int i, j;
  503. for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
  504. ids = timedia_data[i].ids;
  505. for (j = 0; ids[j]; j++)
  506. if (dev->subsystem_device == ids[j])
  507. return timedia_data[i].num;
  508. }
  509. return 0;
  510. }
  511. /*
  512. * Timedia/SUNIX uses a mixture of BARs and offsets
  513. * Ugh, this is ugly as all hell --- TYT
  514. */
  515. static int
  516. pci_timedia_setup(struct serial_private *priv,
  517. const struct pciserial_board *board,
  518. struct uart_8250_port *port, int idx)
  519. {
  520. unsigned int bar = 0, offset = board->first_offset;
  521. switch (idx) {
  522. case 0:
  523. bar = 0;
  524. break;
  525. case 1:
  526. offset = board->uart_offset;
  527. bar = 0;
  528. break;
  529. case 2:
  530. bar = 1;
  531. break;
  532. case 3:
  533. offset = board->uart_offset;
  534. /* FALLTHROUGH */
  535. case 4: /* BAR 2 */
  536. case 5: /* BAR 3 */
  537. case 6: /* BAR 4 */
  538. case 7: /* BAR 5 */
  539. bar = idx - 2;
  540. }
  541. return setup_port(priv, port, bar, offset, board->reg_shift);
  542. }
  543. /*
  544. * Some Titan cards are also a little weird
  545. */
  546. static int
  547. titan_400l_800l_setup(struct serial_private *priv,
  548. const struct pciserial_board *board,
  549. struct uart_8250_port *port, int idx)
  550. {
  551. unsigned int bar, offset = board->first_offset;
  552. switch (idx) {
  553. case 0:
  554. bar = 1;
  555. break;
  556. case 1:
  557. bar = 2;
  558. break;
  559. default:
  560. bar = 4;
  561. offset = (idx - 2) * board->uart_offset;
  562. }
  563. return setup_port(priv, port, bar, offset, board->reg_shift);
  564. }
  565. static int pci_xircom_init(struct pci_dev *dev)
  566. {
  567. msleep(100);
  568. return 0;
  569. }
  570. static int pci_ni8420_init(struct pci_dev *dev)
  571. {
  572. void __iomem *p;
  573. unsigned int bar = 0;
  574. if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
  575. moan_device("no memory in bar", dev);
  576. return 0;
  577. }
  578. p = pci_ioremap_bar(dev, bar);
  579. if (p == NULL)
  580. return -ENOMEM;
  581. /* Enable CPU Interrupt */
  582. writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
  583. p + NI8420_INT_ENABLE_REG);
  584. iounmap(p);
  585. return 0;
  586. }
  587. #define MITE_IOWBSR1_WSIZE 0xa
  588. #define MITE_IOWBSR1_WIN_OFFSET 0x800
  589. #define MITE_IOWBSR1_WENAB (1 << 7)
  590. #define MITE_LCIMR1_IO_IE_0 (1 << 24)
  591. #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
  592. #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
  593. static int pci_ni8430_init(struct pci_dev *dev)
  594. {
  595. void __iomem *p;
  596. struct pci_bus_region region;
  597. u32 device_window;
  598. unsigned int bar = 0;
  599. if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
  600. moan_device("no memory in bar", dev);
  601. return 0;
  602. }
  603. p = pci_ioremap_bar(dev, bar);
  604. if (p == NULL)
  605. return -ENOMEM;
  606. /*
  607. * Set device window address and size in BAR0, while acknowledging that
  608. * the resource structure may contain a translated address that differs
  609. * from the address the device responds to.
  610. */
  611. pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
  612. device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
  613. | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
  614. writel(device_window, p + MITE_IOWBSR1);
  615. /* Set window access to go to RAMSEL IO address space */
  616. writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
  617. p + MITE_IOWCR1);
  618. /* Enable IO Bus Interrupt 0 */
  619. writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
  620. /* Enable CPU Interrupt */
  621. writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
  622. iounmap(p);
  623. return 0;
  624. }
  625. /* UART Port Control Register */
  626. #define NI8430_PORTCON 0x0f
  627. #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
  628. static int
  629. pci_ni8430_setup(struct serial_private *priv,
  630. const struct pciserial_board *board,
  631. struct uart_8250_port *port, int idx)
  632. {
  633. struct pci_dev *dev = priv->dev;
  634. void __iomem *p;
  635. unsigned int bar, offset = board->first_offset;
  636. if (idx >= board->num_ports)
  637. return 1;
  638. bar = FL_GET_BASE(board->flags);
  639. offset += idx * board->uart_offset;
  640. p = pci_ioremap_bar(dev, bar);
  641. if (!p)
  642. return -ENOMEM;
  643. /* enable the transceiver */
  644. writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
  645. p + offset + NI8430_PORTCON);
  646. iounmap(p);
  647. return setup_port(priv, port, bar, offset, board->reg_shift);
  648. }
  649. static int pci_netmos_9900_setup(struct serial_private *priv,
  650. const struct pciserial_board *board,
  651. struct uart_8250_port *port, int idx)
  652. {
  653. unsigned int bar;
  654. if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
  655. (priv->dev->subsystem_device & 0xff00) == 0x3000) {
  656. /* netmos apparently orders BARs by datasheet layout, so serial
  657. * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
  658. */
  659. bar = 3 * idx;
  660. return setup_port(priv, port, bar, 0, board->reg_shift);
  661. } else {
  662. return pci_default_setup(priv, board, port, idx);
  663. }
  664. }
  665. /* the 99xx series comes with a range of device IDs and a variety
  666. * of capabilities:
  667. *
  668. * 9900 has varying capabilities and can cascade to sub-controllers
  669. * (cascading should be purely internal)
  670. * 9904 is hardwired with 4 serial ports
  671. * 9912 and 9922 are hardwired with 2 serial ports
  672. */
  673. static int pci_netmos_9900_numports(struct pci_dev *dev)
  674. {
  675. unsigned int c = dev->class;
  676. unsigned int pi;
  677. unsigned short sub_serports;
  678. pi = c & 0xff;
  679. if (pi == 2)
  680. return 1;
  681. if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
  682. /* two possibilities: 0x30ps encodes number of parallel and
  683. * serial ports, or 0x1000 indicates *something*. This is not
  684. * immediately obvious, since the 2s1p+4s configuration seems
  685. * to offer all functionality on functions 0..2, while still
  686. * advertising the same function 3 as the 4s+2s1p config.
  687. */
  688. sub_serports = dev->subsystem_device & 0xf;
  689. if (sub_serports > 0)
  690. return sub_serports;
  691. dev_err(&dev->dev,
  692. "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
  693. return 0;
  694. }
  695. moan_device("unknown NetMos/Mostech program interface", dev);
  696. return 0;
  697. }
  698. static int pci_netmos_init(struct pci_dev *dev)
  699. {
  700. /* subdevice 0x00PS means <P> parallel, <S> serial */
  701. unsigned int num_serial = dev->subsystem_device & 0xf;
  702. if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
  703. (dev->device == PCI_DEVICE_ID_NETMOS_9865))
  704. return 0;
  705. if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
  706. dev->subsystem_device == 0x0299)
  707. return 0;
  708. switch (dev->device) { /* FALLTHROUGH on all */
  709. case PCI_DEVICE_ID_NETMOS_9904:
  710. case PCI_DEVICE_ID_NETMOS_9912:
  711. case PCI_DEVICE_ID_NETMOS_9922:
  712. case PCI_DEVICE_ID_NETMOS_9900:
  713. num_serial = pci_netmos_9900_numports(dev);
  714. break;
  715. default:
  716. break;
  717. }
  718. if (num_serial == 0) {
  719. moan_device("unknown NetMos/Mostech device", dev);
  720. return -ENODEV;
  721. }
  722. return num_serial;
  723. }
  724. /*
  725. * These chips are available with optionally one parallel port and up to
  726. * two serial ports. Unfortunately they all have the same product id.
  727. *
  728. * Basic configuration is done over a region of 32 I/O ports. The base
  729. * ioport is called INTA or INTC, depending on docs/other drivers.
  730. *
  731. * The region of the 32 I/O ports is configured in POSIO0R...
  732. */
  733. /* registers */
  734. #define ITE_887x_MISCR 0x9c
  735. #define ITE_887x_INTCBAR 0x78
  736. #define ITE_887x_UARTBAR 0x7c
  737. #define ITE_887x_PS0BAR 0x10
  738. #define ITE_887x_POSIO0 0x60
  739. /* I/O space size */
  740. #define ITE_887x_IOSIZE 32
  741. /* I/O space size (bits 26-24; 8 bytes = 011b) */
  742. #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
  743. /* I/O space size (bits 26-24; 32 bytes = 101b) */
  744. #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
  745. /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
  746. #define ITE_887x_POSIO_SPEED (3 << 29)
  747. /* enable IO_Space bit */
  748. #define ITE_887x_POSIO_ENABLE (1 << 31)
  749. static int pci_ite887x_init(struct pci_dev *dev)
  750. {
  751. /* inta_addr are the configuration addresses of the ITE */
  752. static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
  753. 0x200, 0x280, 0 };
  754. int ret, i, type;
  755. struct resource *iobase = NULL;
  756. u32 miscr, uartbar, ioport;
  757. /* search for the base-ioport */
  758. i = 0;
  759. while (inta_addr[i] && iobase == NULL) {
  760. iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
  761. "ite887x");
  762. if (iobase != NULL) {
  763. /* write POSIO0R - speed | size | ioport */
  764. pci_write_config_dword(dev, ITE_887x_POSIO0,
  765. ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
  766. ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
  767. /* write INTCBAR - ioport */
  768. pci_write_config_dword(dev, ITE_887x_INTCBAR,
  769. inta_addr[i]);
  770. ret = inb(inta_addr[i]);
  771. if (ret != 0xff) {
  772. /* ioport connected */
  773. break;
  774. }
  775. release_region(iobase->start, ITE_887x_IOSIZE);
  776. iobase = NULL;
  777. }
  778. i++;
  779. }
  780. if (!inta_addr[i]) {
  781. dev_err(&dev->dev, "ite887x: could not find iobase\n");
  782. return -ENODEV;
  783. }
  784. /* start of undocumented type checking (see parport_pc.c) */
  785. type = inb(iobase->start + 0x18) & 0x0f;
  786. switch (type) {
  787. case 0x2: /* ITE8871 (1P) */
  788. case 0xa: /* ITE8875 (1P) */
  789. ret = 0;
  790. break;
  791. case 0xe: /* ITE8872 (2S1P) */
  792. ret = 2;
  793. break;
  794. case 0x6: /* ITE8873 (1S) */
  795. ret = 1;
  796. break;
  797. case 0x8: /* ITE8874 (2S) */
  798. ret = 2;
  799. break;
  800. default:
  801. moan_device("Unknown ITE887x", dev);
  802. ret = -ENODEV;
  803. }
  804. /* configure all serial ports */
  805. for (i = 0; i < ret; i++) {
  806. /* read the I/O port from the device */
  807. pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
  808. &ioport);
  809. ioport &= 0x0000FF00; /* the actual base address */
  810. pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
  811. ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
  812. ITE_887x_POSIO_IOSIZE_8 | ioport);
  813. /* write the ioport to the UARTBAR */
  814. pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
  815. uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
  816. uartbar |= (ioport << (16 * i)); /* set the ioport */
  817. pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
  818. /* get current config */
  819. pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
  820. /* disable interrupts (UARTx_Routing[3:0]) */
  821. miscr &= ~(0xf << (12 - 4 * i));
  822. /* activate the UART (UARTx_En) */
  823. miscr |= 1 << (23 - i);
  824. /* write new config with activated UART */
  825. pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
  826. }
  827. if (ret <= 0) {
  828. /* the device has no UARTs if we get here */
  829. release_region(iobase->start, ITE_887x_IOSIZE);
  830. }
  831. return ret;
  832. }
  833. static void pci_ite887x_exit(struct pci_dev *dev)
  834. {
  835. u32 ioport;
  836. /* the ioport is bit 0-15 in POSIO0R */
  837. pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
  838. ioport &= 0xffff;
  839. release_region(ioport, ITE_887x_IOSIZE);
  840. }
  841. /*
  842. * EndRun Technologies.
  843. * Determine the number of ports available on the device.
  844. */
  845. #define PCI_VENDOR_ID_ENDRUN 0x7401
  846. #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
  847. static int pci_endrun_init(struct pci_dev *dev)
  848. {
  849. u8 __iomem *p;
  850. unsigned long deviceID;
  851. unsigned int number_uarts = 0;
  852. /* EndRun device is all 0xexxx */
  853. if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
  854. (dev->device & 0xf000) != 0xe000)
  855. return 0;
  856. p = pci_iomap(dev, 0, 5);
  857. if (p == NULL)
  858. return -ENOMEM;
  859. deviceID = ioread32(p);
  860. /* EndRun device */
  861. if (deviceID == 0x07000200) {
  862. number_uarts = ioread8(p + 4);
  863. dev_dbg(&dev->dev,
  864. "%d ports detected on EndRun PCI Express device\n",
  865. number_uarts);
  866. }
  867. pci_iounmap(dev, p);
  868. return number_uarts;
  869. }
  870. /*
  871. * Oxford Semiconductor Inc.
  872. * Check that device is part of the Tornado range of devices, then determine
  873. * the number of ports available on the device.
  874. */
  875. static int pci_oxsemi_tornado_init(struct pci_dev *dev)
  876. {
  877. u8 __iomem *p;
  878. unsigned long deviceID;
  879. unsigned int number_uarts = 0;
  880. /* OxSemi Tornado devices are all 0xCxxx */
  881. if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
  882. (dev->device & 0xF000) != 0xC000)
  883. return 0;
  884. p = pci_iomap(dev, 0, 5);
  885. if (p == NULL)
  886. return -ENOMEM;
  887. deviceID = ioread32(p);
  888. /* Tornado device */
  889. if (deviceID == 0x07000200) {
  890. number_uarts = ioread8(p + 4);
  891. dev_dbg(&dev->dev,
  892. "%d ports detected on Oxford PCI Express device\n",
  893. number_uarts);
  894. }
  895. pci_iounmap(dev, p);
  896. return number_uarts;
  897. }
  898. static int pci_asix_setup(struct serial_private *priv,
  899. const struct pciserial_board *board,
  900. struct uart_8250_port *port, int idx)
  901. {
  902. port->bugs |= UART_BUG_PARITY;
  903. return pci_default_setup(priv, board, port, idx);
  904. }
  905. /* Quatech devices have their own extra interface features */
  906. struct quatech_feature {
  907. u16 devid;
  908. bool amcc;
  909. };
  910. #define QPCR_TEST_FOR1 0x3F
  911. #define QPCR_TEST_GET1 0x00
  912. #define QPCR_TEST_FOR2 0x40
  913. #define QPCR_TEST_GET2 0x40
  914. #define QPCR_TEST_FOR3 0x80
  915. #define QPCR_TEST_GET3 0x40
  916. #define QPCR_TEST_FOR4 0xC0
  917. #define QPCR_TEST_GET4 0x80
  918. #define QOPR_CLOCK_X1 0x0000
  919. #define QOPR_CLOCK_X2 0x0001
  920. #define QOPR_CLOCK_X4 0x0002
  921. #define QOPR_CLOCK_X8 0x0003
  922. #define QOPR_CLOCK_RATE_MASK 0x0003
  923. static struct quatech_feature quatech_cards[] = {
  924. { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
  925. { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
  926. { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
  927. { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
  928. { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
  929. { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
  930. { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
  931. { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
  932. { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
  933. { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
  934. { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
  935. { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
  936. { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
  937. { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
  938. { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
  939. { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
  940. { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
  941. { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
  942. { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
  943. { 0, }
  944. };
  945. static int pci_quatech_amcc(u16 devid)
  946. {
  947. struct quatech_feature *qf = &quatech_cards[0];
  948. while (qf->devid) {
  949. if (qf->devid == devid)
  950. return qf->amcc;
  951. qf++;
  952. }
  953. pr_err("quatech: unknown port type '0x%04X'.\n", devid);
  954. return 0;
  955. };
  956. static int pci_quatech_rqopr(struct uart_8250_port *port)
  957. {
  958. unsigned long base = port->port.iobase;
  959. u8 LCR, val;
  960. LCR = inb(base + UART_LCR);
  961. outb(0xBF, base + UART_LCR);
  962. val = inb(base + UART_SCR);
  963. outb(LCR, base + UART_LCR);
  964. return val;
  965. }
  966. static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
  967. {
  968. unsigned long base = port->port.iobase;
  969. u8 LCR;
  970. LCR = inb(base + UART_LCR);
  971. outb(0xBF, base + UART_LCR);
  972. inb(base + UART_SCR);
  973. outb(qopr, base + UART_SCR);
  974. outb(LCR, base + UART_LCR);
  975. }
  976. static int pci_quatech_rqmcr(struct uart_8250_port *port)
  977. {
  978. unsigned long base = port->port.iobase;
  979. u8 LCR, val, qmcr;
  980. LCR = inb(base + UART_LCR);
  981. outb(0xBF, base + UART_LCR);
  982. val = inb(base + UART_SCR);
  983. outb(val | 0x10, base + UART_SCR);
  984. qmcr = inb(base + UART_MCR);
  985. outb(val, base + UART_SCR);
  986. outb(LCR, base + UART_LCR);
  987. return qmcr;
  988. }
  989. static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
  990. {
  991. unsigned long base = port->port.iobase;
  992. u8 LCR, val;
  993. LCR = inb(base + UART_LCR);
  994. outb(0xBF, base + UART_LCR);
  995. val = inb(base + UART_SCR);
  996. outb(val | 0x10, base + UART_SCR);
  997. outb(qmcr, base + UART_MCR);
  998. outb(val, base + UART_SCR);
  999. outb(LCR, base + UART_LCR);
  1000. }
  1001. static int pci_quatech_has_qmcr(struct uart_8250_port *port)
  1002. {
  1003. unsigned long base = port->port.iobase;
  1004. u8 LCR, val;
  1005. LCR = inb(base + UART_LCR);
  1006. outb(0xBF, base + UART_LCR);
  1007. val = inb(base + UART_SCR);
  1008. if (val & 0x20) {
  1009. outb(0x80, UART_LCR);
  1010. if (!(inb(UART_SCR) & 0x20)) {
  1011. outb(LCR, base + UART_LCR);
  1012. return 1;
  1013. }
  1014. }
  1015. return 0;
  1016. }
  1017. static int pci_quatech_test(struct uart_8250_port *port)
  1018. {
  1019. u8 reg, qopr;
  1020. qopr = pci_quatech_rqopr(port);
  1021. pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
  1022. reg = pci_quatech_rqopr(port) & 0xC0;
  1023. if (reg != QPCR_TEST_GET1)
  1024. return -EINVAL;
  1025. pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
  1026. reg = pci_quatech_rqopr(port) & 0xC0;
  1027. if (reg != QPCR_TEST_GET2)
  1028. return -EINVAL;
  1029. pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
  1030. reg = pci_quatech_rqopr(port) & 0xC0;
  1031. if (reg != QPCR_TEST_GET3)
  1032. return -EINVAL;
  1033. pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
  1034. reg = pci_quatech_rqopr(port) & 0xC0;
  1035. if (reg != QPCR_TEST_GET4)
  1036. return -EINVAL;
  1037. pci_quatech_wqopr(port, qopr);
  1038. return 0;
  1039. }
  1040. static int pci_quatech_clock(struct uart_8250_port *port)
  1041. {
  1042. u8 qopr, reg, set;
  1043. unsigned long clock;
  1044. if (pci_quatech_test(port) < 0)
  1045. return 1843200;
  1046. qopr = pci_quatech_rqopr(port);
  1047. pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
  1048. reg = pci_quatech_rqopr(port);
  1049. if (reg & QOPR_CLOCK_X8) {
  1050. clock = 1843200;
  1051. goto out;
  1052. }
  1053. pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
  1054. reg = pci_quatech_rqopr(port);
  1055. if (!(reg & QOPR_CLOCK_X8)) {
  1056. clock = 1843200;
  1057. goto out;
  1058. }
  1059. reg &= QOPR_CLOCK_X8;
  1060. if (reg == QOPR_CLOCK_X2) {
  1061. clock = 3685400;
  1062. set = QOPR_CLOCK_X2;
  1063. } else if (reg == QOPR_CLOCK_X4) {
  1064. clock = 7372800;
  1065. set = QOPR_CLOCK_X4;
  1066. } else if (reg == QOPR_CLOCK_X8) {
  1067. clock = 14745600;
  1068. set = QOPR_CLOCK_X8;
  1069. } else {
  1070. clock = 1843200;
  1071. set = QOPR_CLOCK_X1;
  1072. }
  1073. qopr &= ~QOPR_CLOCK_RATE_MASK;
  1074. qopr |= set;
  1075. out:
  1076. pci_quatech_wqopr(port, qopr);
  1077. return clock;
  1078. }
  1079. static int pci_quatech_rs422(struct uart_8250_port *port)
  1080. {
  1081. u8 qmcr;
  1082. int rs422 = 0;
  1083. if (!pci_quatech_has_qmcr(port))
  1084. return 0;
  1085. qmcr = pci_quatech_rqmcr(port);
  1086. pci_quatech_wqmcr(port, 0xFF);
  1087. if (pci_quatech_rqmcr(port))
  1088. rs422 = 1;
  1089. pci_quatech_wqmcr(port, qmcr);
  1090. return rs422;
  1091. }
  1092. static int pci_quatech_init(struct pci_dev *dev)
  1093. {
  1094. if (pci_quatech_amcc(dev->device)) {
  1095. unsigned long base = pci_resource_start(dev, 0);
  1096. if (base) {
  1097. u32 tmp;
  1098. outl(inl(base + 0x38) | 0x00002000, base + 0x38);
  1099. tmp = inl(base + 0x3c);
  1100. outl(tmp | 0x01000000, base + 0x3c);
  1101. outl(tmp &= ~0x01000000, base + 0x3c);
  1102. }
  1103. }
  1104. return 0;
  1105. }
  1106. static int pci_quatech_setup(struct serial_private *priv,
  1107. const struct pciserial_board *board,
  1108. struct uart_8250_port *port, int idx)
  1109. {
  1110. /* Needed by pci_quatech calls below */
  1111. port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
  1112. /* Set up the clocking */
  1113. port->port.uartclk = pci_quatech_clock(port);
  1114. /* For now just warn about RS422 */
  1115. if (pci_quatech_rs422(port))
  1116. pr_warn("quatech: software control of RS422 features not currently supported.\n");
  1117. return pci_default_setup(priv, board, port, idx);
  1118. }
  1119. static void pci_quatech_exit(struct pci_dev *dev)
  1120. {
  1121. }
  1122. static int pci_default_setup(struct serial_private *priv,
  1123. const struct pciserial_board *board,
  1124. struct uart_8250_port *port, int idx)
  1125. {
  1126. unsigned int bar, offset = board->first_offset, maxnr;
  1127. bar = FL_GET_BASE(board->flags);
  1128. if (board->flags & FL_BASE_BARS)
  1129. bar += idx;
  1130. else
  1131. offset += idx * board->uart_offset;
  1132. maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
  1133. (board->reg_shift + 3);
  1134. if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
  1135. return 1;
  1136. return setup_port(priv, port, bar, offset, board->reg_shift);
  1137. }
  1138. static int pci_pericom_setup(struct serial_private *priv,
  1139. const struct pciserial_board *board,
  1140. struct uart_8250_port *port, int idx)
  1141. {
  1142. unsigned int bar, offset = board->first_offset, maxnr;
  1143. bar = FL_GET_BASE(board->flags);
  1144. if (board->flags & FL_BASE_BARS)
  1145. bar += idx;
  1146. else
  1147. offset += idx * board->uart_offset;
  1148. if (idx==3)
  1149. offset = 0x38;
  1150. maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
  1151. (board->reg_shift + 3);
  1152. if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
  1153. return 1;
  1154. return setup_port(priv, port, bar, offset, board->reg_shift);
  1155. }
  1156. static int
  1157. ce4100_serial_setup(struct serial_private *priv,
  1158. const struct pciserial_board *board,
  1159. struct uart_8250_port *port, int idx)
  1160. {
  1161. int ret;
  1162. ret = setup_port(priv, port, idx, 0, board->reg_shift);
  1163. port->port.iotype = UPIO_MEM32;
  1164. port->port.type = PORT_XSCALE;
  1165. port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
  1166. port->port.regshift = 2;
  1167. return ret;
  1168. }
  1169. static int
  1170. pci_omegapci_setup(struct serial_private *priv,
  1171. const struct pciserial_board *board,
  1172. struct uart_8250_port *port, int idx)
  1173. {
  1174. return setup_port(priv, port, 2, idx * 8, 0);
  1175. }
  1176. static int
  1177. pci_brcm_trumanage_setup(struct serial_private *priv,
  1178. const struct pciserial_board *board,
  1179. struct uart_8250_port *port, int idx)
  1180. {
  1181. int ret = pci_default_setup(priv, board, port, idx);
  1182. port->port.type = PORT_BRCM_TRUMANAGE;
  1183. port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
  1184. return ret;
  1185. }
  1186. /* RTS will control by MCR if this bit is 0 */
  1187. #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
  1188. /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
  1189. #define FINTEK_RTS_INVERT BIT(5)
  1190. /* We should do proper H/W transceiver setting before change to RS485 mode */
  1191. static int pci_fintek_rs485_config(struct uart_port *port,
  1192. struct serial_rs485 *rs485)
  1193. {
  1194. struct pci_dev *pci_dev = to_pci_dev(port->dev);
  1195. u8 setting;
  1196. u8 *index = (u8 *) port->private_data;
  1197. pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
  1198. if (!rs485)
  1199. rs485 = &port->rs485;
  1200. else if (rs485->flags & SER_RS485_ENABLED)
  1201. memset(rs485->padding, 0, sizeof(rs485->padding));
  1202. else
  1203. memset(rs485, 0, sizeof(*rs485));
  1204. /* F81504/508/512 not support RTS delay before or after send */
  1205. rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
  1206. if (rs485->flags & SER_RS485_ENABLED) {
  1207. /* Enable RTS H/W control mode */
  1208. setting |= FINTEK_RTS_CONTROL_BY_HW;
  1209. if (rs485->flags & SER_RS485_RTS_ON_SEND) {
  1210. /* RTS driving high on TX */
  1211. setting &= ~FINTEK_RTS_INVERT;
  1212. } else {
  1213. /* RTS driving low on TX */
  1214. setting |= FINTEK_RTS_INVERT;
  1215. }
  1216. rs485->delay_rts_after_send = 0;
  1217. rs485->delay_rts_before_send = 0;
  1218. } else {
  1219. /* Disable RTS H/W control mode */
  1220. setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
  1221. }
  1222. pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
  1223. if (rs485 != &port->rs485)
  1224. port->rs485 = *rs485;
  1225. return 0;
  1226. }
  1227. static int pci_fintek_setup(struct serial_private *priv,
  1228. const struct pciserial_board *board,
  1229. struct uart_8250_port *port, int idx)
  1230. {
  1231. struct pci_dev *pdev = priv->dev;
  1232. u8 *data;
  1233. u8 config_base;
  1234. u16 iobase;
  1235. config_base = 0x40 + 0x08 * idx;
  1236. /* Get the io address from configuration space */
  1237. pci_read_config_word(pdev, config_base + 4, &iobase);
  1238. dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
  1239. port->port.iotype = UPIO_PORT;
  1240. port->port.iobase = iobase;
  1241. port->port.rs485_config = pci_fintek_rs485_config;
  1242. data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
  1243. if (!data)
  1244. return -ENOMEM;
  1245. /* preserve index in PCI configuration space */
  1246. *data = idx;
  1247. port->port.private_data = data;
  1248. return 0;
  1249. }
  1250. static int pci_fintek_init(struct pci_dev *dev)
  1251. {
  1252. unsigned long iobase;
  1253. u32 max_port, i;
  1254. u32 bar_data[3];
  1255. u8 config_base;
  1256. struct serial_private *priv = pci_get_drvdata(dev);
  1257. struct uart_8250_port *port;
  1258. switch (dev->device) {
  1259. case 0x1104: /* 4 ports */
  1260. case 0x1108: /* 8 ports */
  1261. max_port = dev->device & 0xff;
  1262. break;
  1263. case 0x1112: /* 12 ports */
  1264. max_port = 12;
  1265. break;
  1266. default:
  1267. return -EINVAL;
  1268. }
  1269. /* Get the io address dispatch from the BIOS */
  1270. pci_read_config_dword(dev, 0x24, &bar_data[0]);
  1271. pci_read_config_dword(dev, 0x20, &bar_data[1]);
  1272. pci_read_config_dword(dev, 0x1c, &bar_data[2]);
  1273. for (i = 0; i < max_port; ++i) {
  1274. /* UART0 configuration offset start from 0x40 */
  1275. config_base = 0x40 + 0x08 * i;
  1276. /* Calculate Real IO Port */
  1277. iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
  1278. /* Enable UART I/O port */
  1279. pci_write_config_byte(dev, config_base + 0x00, 0x01);
  1280. /* Select 128-byte FIFO and 8x FIFO threshold */
  1281. pci_write_config_byte(dev, config_base + 0x01, 0x33);
  1282. /* LSB UART */
  1283. pci_write_config_byte(dev, config_base + 0x04,
  1284. (u8)(iobase & 0xff));
  1285. /* MSB UART */
  1286. pci_write_config_byte(dev, config_base + 0x05,
  1287. (u8)((iobase & 0xff00) >> 8));
  1288. pci_write_config_byte(dev, config_base + 0x06, dev->irq);
  1289. if (priv) {
  1290. /* re-apply RS232/485 mode when
  1291. * pciserial_resume_ports()
  1292. */
  1293. port = serial8250_get_port(priv->line[i]);
  1294. pci_fintek_rs485_config(&port->port, NULL);
  1295. } else {
  1296. /* First init without port data
  1297. * force init to RS232 Mode
  1298. */
  1299. pci_write_config_byte(dev, config_base + 0x07, 0x01);
  1300. }
  1301. }
  1302. return max_port;
  1303. }
  1304. static int skip_tx_en_setup(struct serial_private *priv,
  1305. const struct pciserial_board *board,
  1306. struct uart_8250_port *port, int idx)
  1307. {
  1308. port->port.flags |= UPF_NO_TXEN_TEST;
  1309. dev_dbg(&priv->dev->dev,
  1310. "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
  1311. priv->dev->vendor, priv->dev->device,
  1312. priv->dev->subsystem_vendor, priv->dev->subsystem_device);
  1313. return pci_default_setup(priv, board, port, idx);
  1314. }
  1315. static void kt_handle_break(struct uart_port *p)
  1316. {
  1317. struct uart_8250_port *up = up_to_u8250p(p);
  1318. /*
  1319. * On receipt of a BI, serial device in Intel ME (Intel
  1320. * management engine) needs to have its fifos cleared for sane
  1321. * SOL (Serial Over Lan) output.
  1322. */
  1323. serial8250_clear_and_reinit_fifos(up);
  1324. }
  1325. static unsigned int kt_serial_in(struct uart_port *p, int offset)
  1326. {
  1327. struct uart_8250_port *up = up_to_u8250p(p);
  1328. unsigned int val;
  1329. /*
  1330. * When the Intel ME (management engine) gets reset its serial
  1331. * port registers could return 0 momentarily. Functions like
  1332. * serial8250_console_write, read and save the IER, perform
  1333. * some operation and then restore it. In order to avoid
  1334. * setting IER register inadvertently to 0, if the value read
  1335. * is 0, double check with ier value in uart_8250_port and use
  1336. * that instead. up->ier should be the same value as what is
  1337. * currently configured.
  1338. */
  1339. val = inb(p->iobase + offset);
  1340. if (offset == UART_IER) {
  1341. if (val == 0)
  1342. val = up->ier;
  1343. }
  1344. return val;
  1345. }
  1346. static int kt_serial_setup(struct serial_private *priv,
  1347. const struct pciserial_board *board,
  1348. struct uart_8250_port *port, int idx)
  1349. {
  1350. port->port.flags |= UPF_BUG_THRE;
  1351. port->port.serial_in = kt_serial_in;
  1352. port->port.handle_break = kt_handle_break;
  1353. return skip_tx_en_setup(priv, board, port, idx);
  1354. }
  1355. static int pci_eg20t_init(struct pci_dev *dev)
  1356. {
  1357. #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
  1358. return -ENODEV;
  1359. #else
  1360. return 0;
  1361. #endif
  1362. }
  1363. #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
  1364. #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
  1365. #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
  1366. #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
  1367. #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
  1368. #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
  1369. #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
  1370. #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
  1371. #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
  1372. #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
  1373. #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
  1374. #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
  1375. #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
  1376. #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
  1377. static int
  1378. pci_xr17c154_setup(struct serial_private *priv,
  1379. const struct pciserial_board *board,
  1380. struct uart_8250_port *port, int idx)
  1381. {
  1382. port->port.flags |= UPF_EXAR_EFR;
  1383. return pci_default_setup(priv, board, port, idx);
  1384. }
  1385. static inline int
  1386. xr17v35x_has_slave(struct serial_private *priv)
  1387. {
  1388. const int dev_id = priv->dev->device;
  1389. return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
  1390. (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
  1391. }
  1392. static int
  1393. pci_xr17v35x_setup(struct serial_private *priv,
  1394. const struct pciserial_board *board,
  1395. struct uart_8250_port *port, int idx)
  1396. {
  1397. u8 __iomem *p;
  1398. p = pci_ioremap_bar(priv->dev, 0);
  1399. if (p == NULL)
  1400. return -ENOMEM;
  1401. port->port.flags |= UPF_EXAR_EFR;
  1402. /*
  1403. * Setup the uart clock for the devices on expansion slot to
  1404. * half the clock speed of the main chip (which is 125MHz)
  1405. */
  1406. if (xr17v35x_has_slave(priv) && idx >= 8)
  1407. port->port.uartclk = (7812500 * 16 / 2);
  1408. /*
  1409. * Setup Multipurpose Input/Output pins.
  1410. */
  1411. if (idx == 0) {
  1412. writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
  1413. writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
  1414. writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
  1415. writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
  1416. writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
  1417. writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
  1418. writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
  1419. writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
  1420. writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
  1421. writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
  1422. writeb(0x00, p + UART_EXAR_MPIOSEL_15_8);
  1423. writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
  1424. }
  1425. writeb(0x00, p + UART_EXAR_8XMODE);
  1426. writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
  1427. writeb(128, p + UART_EXAR_TXTRG);
  1428. writeb(128, p + UART_EXAR_RXTRG);
  1429. iounmap(p);
  1430. return pci_default_setup(priv, board, port, idx);
  1431. }
  1432. #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
  1433. #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
  1434. #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
  1435. #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
  1436. static int
  1437. pci_fastcom335_setup(struct serial_private *priv,
  1438. const struct pciserial_board *board,
  1439. struct uart_8250_port *port, int idx)
  1440. {
  1441. u8 __iomem *p;
  1442. p = pci_ioremap_bar(priv->dev, 0);
  1443. if (p == NULL)
  1444. return -ENOMEM;
  1445. port->port.flags |= UPF_EXAR_EFR;
  1446. /*
  1447. * Setup Multipurpose Input/Output pins.
  1448. */
  1449. if (idx == 0) {
  1450. switch (priv->dev->device) {
  1451. case PCI_DEVICE_ID_COMMTECH_4222PCI335:
  1452. case PCI_DEVICE_ID_COMMTECH_4224PCI335:
  1453. writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
  1454. writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
  1455. writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
  1456. break;
  1457. case PCI_DEVICE_ID_COMMTECH_2324PCI335:
  1458. case PCI_DEVICE_ID_COMMTECH_2328PCI335:
  1459. writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
  1460. writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
  1461. writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
  1462. break;
  1463. }
  1464. writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
  1465. writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
  1466. writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
  1467. }
  1468. writeb(0x00, p + UART_EXAR_8XMODE);
  1469. writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
  1470. writeb(32, p + UART_EXAR_TXTRG);
  1471. writeb(32, p + UART_EXAR_RXTRG);
  1472. iounmap(p);
  1473. return pci_default_setup(priv, board, port, idx);
  1474. }
  1475. static int
  1476. pci_wch_ch353_setup(struct serial_private *priv,
  1477. const struct pciserial_board *board,
  1478. struct uart_8250_port *port, int idx)
  1479. {
  1480. port->port.flags |= UPF_FIXED_TYPE;
  1481. port->port.type = PORT_16550A;
  1482. return pci_default_setup(priv, board, port, idx);
  1483. }
  1484. static int
  1485. pci_wch_ch355_setup(struct serial_private *priv,
  1486. const struct pciserial_board *board,
  1487. struct uart_8250_port *port, int idx)
  1488. {
  1489. port->port.flags |= UPF_FIXED_TYPE;
  1490. port->port.type = PORT_16550A;
  1491. return pci_default_setup(priv, board, port, idx);
  1492. }
  1493. static int
  1494. pci_wch_ch38x_setup(struct serial_private *priv,
  1495. const struct pciserial_board *board,
  1496. struct uart_8250_port *port, int idx)
  1497. {
  1498. port->port.flags |= UPF_FIXED_TYPE;
  1499. port->port.type = PORT_16850;
  1500. return pci_default_setup(priv, board, port, idx);
  1501. }
  1502. #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
  1503. #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
  1504. #define PCI_DEVICE_ID_OCTPRO 0x0001
  1505. #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
  1506. #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
  1507. #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
  1508. #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
  1509. #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
  1510. #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
  1511. #define PCI_VENDOR_ID_ADVANTECH 0x13fe
  1512. #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
  1513. #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
  1514. #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
  1515. #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
  1516. #define PCI_DEVICE_ID_TITAN_200I 0x8028
  1517. #define PCI_DEVICE_ID_TITAN_400I 0x8048
  1518. #define PCI_DEVICE_ID_TITAN_800I 0x8088
  1519. #define PCI_DEVICE_ID_TITAN_800EH 0xA007
  1520. #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
  1521. #define PCI_DEVICE_ID_TITAN_400EH 0xA009
  1522. #define PCI_DEVICE_ID_TITAN_100E 0xA010
  1523. #define PCI_DEVICE_ID_TITAN_200E 0xA012
  1524. #define PCI_DEVICE_ID_TITAN_400E 0xA013
  1525. #define PCI_DEVICE_ID_TITAN_800E 0xA014
  1526. #define PCI_DEVICE_ID_TITAN_200EI 0xA016
  1527. #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
  1528. #define PCI_DEVICE_ID_TITAN_200V3 0xA306
  1529. #define PCI_DEVICE_ID_TITAN_400V3 0xA310
  1530. #define PCI_DEVICE_ID_TITAN_410V3 0xA312
  1531. #define PCI_DEVICE_ID_TITAN_800V3 0xA314
  1532. #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
  1533. #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
  1534. #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
  1535. #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
  1536. #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
  1537. #define PCI_VENDOR_ID_WCH 0x4348
  1538. #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
  1539. #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
  1540. #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
  1541. #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
  1542. #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
  1543. #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
  1544. #define PCI_VENDOR_ID_AGESTAR 0x5372
  1545. #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
  1546. #define PCI_VENDOR_ID_ASIX 0x9710
  1547. #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
  1548. #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
  1549. #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
  1550. #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
  1551. #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
  1552. #define PCI_VENDOR_ID_SUNIX 0x1fd4
  1553. #define PCI_DEVICE_ID_SUNIX_1999 0x1999
  1554. #define PCIE_VENDOR_ID_WCH 0x1c00
  1555. #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
  1556. #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
  1557. #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
  1558. #define PCI_VENDOR_ID_PERICOM 0x12D8
  1559. #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
  1560. #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
  1561. #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
  1562. #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
  1563. #define PCI_VENDOR_ID_ACCESIO 0x494f
  1564. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
  1565. #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
  1566. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
  1567. #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
  1568. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
  1569. #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
  1570. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
  1571. #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
  1572. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
  1573. #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
  1574. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
  1575. #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
  1576. #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
  1577. #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
  1578. #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
  1579. #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
  1580. #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
  1581. #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
  1582. #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
  1583. #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
  1584. #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
  1585. #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
  1586. #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
  1587. #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
  1588. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
  1589. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
  1590. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
  1591. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
  1592. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
  1593. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
  1594. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
  1595. #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
  1596. #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
  1597. /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
  1598. #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
  1599. #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
  1600. /*
  1601. * Master list of serial port init/setup/exit quirks.
  1602. * This does not describe the general nature of the port.
  1603. * (ie, baud base, number and location of ports, etc)
  1604. *
  1605. * This list is ordered alphabetically by vendor then device.
  1606. * Specific entries must come before more generic entries.
  1607. */
  1608. static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
  1609. /*
  1610. * ADDI-DATA GmbH communication cards <[email protected]>
  1611. */
  1612. {
  1613. .vendor = PCI_VENDOR_ID_AMCC,
  1614. .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
  1615. .subvendor = PCI_ANY_ID,
  1616. .subdevice = PCI_ANY_ID,
  1617. .setup = addidata_apci7800_setup,
  1618. },
  1619. /*
  1620. * AFAVLAB cards - these may be called via parport_serial
  1621. * It is not clear whether this applies to all products.
  1622. */
  1623. {
  1624. .vendor = PCI_VENDOR_ID_AFAVLAB,
  1625. .device = PCI_ANY_ID,
  1626. .subvendor = PCI_ANY_ID,
  1627. .subdevice = PCI_ANY_ID,
  1628. .setup = afavlab_setup,
  1629. },
  1630. /*
  1631. * HP Diva
  1632. */
  1633. {
  1634. .vendor = PCI_VENDOR_ID_HP,
  1635. .device = PCI_DEVICE_ID_HP_DIVA,
  1636. .subvendor = PCI_ANY_ID,
  1637. .subdevice = PCI_ANY_ID,
  1638. .init = pci_hp_diva_init,
  1639. .setup = pci_hp_diva_setup,
  1640. },
  1641. /*
  1642. * Intel
  1643. */
  1644. {
  1645. .vendor = PCI_VENDOR_ID_INTEL,
  1646. .device = PCI_DEVICE_ID_INTEL_80960_RP,
  1647. .subvendor = 0xe4bf,
  1648. .subdevice = PCI_ANY_ID,
  1649. .init = pci_inteli960ni_init,
  1650. .setup = pci_default_setup,
  1651. },
  1652. {
  1653. .vendor = PCI_VENDOR_ID_INTEL,
  1654. .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
  1655. .subvendor = PCI_ANY_ID,
  1656. .subdevice = PCI_ANY_ID,
  1657. .setup = skip_tx_en_setup,
  1658. },
  1659. {
  1660. .vendor = PCI_VENDOR_ID_INTEL,
  1661. .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
  1662. .subvendor = PCI_ANY_ID,
  1663. .subdevice = PCI_ANY_ID,
  1664. .setup = skip_tx_en_setup,
  1665. },
  1666. {
  1667. .vendor = PCI_VENDOR_ID_INTEL,
  1668. .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
  1669. .subvendor = PCI_ANY_ID,
  1670. .subdevice = PCI_ANY_ID,
  1671. .setup = skip_tx_en_setup,
  1672. },
  1673. {
  1674. .vendor = PCI_VENDOR_ID_INTEL,
  1675. .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
  1676. .subvendor = PCI_ANY_ID,
  1677. .subdevice = PCI_ANY_ID,
  1678. .setup = ce4100_serial_setup,
  1679. },
  1680. {
  1681. .vendor = PCI_VENDOR_ID_INTEL,
  1682. .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
  1683. .subvendor = PCI_ANY_ID,
  1684. .subdevice = PCI_ANY_ID,
  1685. .setup = kt_serial_setup,
  1686. },
  1687. /*
  1688. * ITE
  1689. */
  1690. {
  1691. .vendor = PCI_VENDOR_ID_ITE,
  1692. .device = PCI_DEVICE_ID_ITE_8872,
  1693. .subvendor = PCI_ANY_ID,
  1694. .subdevice = PCI_ANY_ID,
  1695. .init = pci_ite887x_init,
  1696. .setup = pci_default_setup,
  1697. .exit = pci_ite887x_exit,
  1698. },
  1699. /*
  1700. * National Instruments
  1701. */
  1702. {
  1703. .vendor = PCI_VENDOR_ID_NI,
  1704. .device = PCI_DEVICE_ID_NI_PCI23216,
  1705. .subvendor = PCI_ANY_ID,
  1706. .subdevice = PCI_ANY_ID,
  1707. .init = pci_ni8420_init,
  1708. .setup = pci_default_setup,
  1709. .exit = pci_ni8420_exit,
  1710. },
  1711. {
  1712. .vendor = PCI_VENDOR_ID_NI,
  1713. .device = PCI_DEVICE_ID_NI_PCI2328,
  1714. .subvendor = PCI_ANY_ID,
  1715. .subdevice = PCI_ANY_ID,
  1716. .init = pci_ni8420_init,
  1717. .setup = pci_default_setup,
  1718. .exit = pci_ni8420_exit,
  1719. },
  1720. {
  1721. .vendor = PCI_VENDOR_ID_NI,
  1722. .device = PCI_DEVICE_ID_NI_PCI2324,
  1723. .subvendor = PCI_ANY_ID,
  1724. .subdevice = PCI_ANY_ID,
  1725. .init = pci_ni8420_init,
  1726. .setup = pci_default_setup,
  1727. .exit = pci_ni8420_exit,
  1728. },
  1729. {
  1730. .vendor = PCI_VENDOR_ID_NI,
  1731. .device = PCI_DEVICE_ID_NI_PCI2322,
  1732. .subvendor = PCI_ANY_ID,
  1733. .subdevice = PCI_ANY_ID,
  1734. .init = pci_ni8420_init,
  1735. .setup = pci_default_setup,
  1736. .exit = pci_ni8420_exit,
  1737. },
  1738. {
  1739. .vendor = PCI_VENDOR_ID_NI,
  1740. .device = PCI_DEVICE_ID_NI_PCI2324I,
  1741. .subvendor = PCI_ANY_ID,
  1742. .subdevice = PCI_ANY_ID,
  1743. .init = pci_ni8420_init,
  1744. .setup = pci_default_setup,
  1745. .exit = pci_ni8420_exit,
  1746. },
  1747. {
  1748. .vendor = PCI_VENDOR_ID_NI,
  1749. .device = PCI_DEVICE_ID_NI_PCI2322I,
  1750. .subvendor = PCI_ANY_ID,
  1751. .subdevice = PCI_ANY_ID,
  1752. .init = pci_ni8420_init,
  1753. .setup = pci_default_setup,
  1754. .exit = pci_ni8420_exit,
  1755. },
  1756. {
  1757. .vendor = PCI_VENDOR_ID_NI,
  1758. .device = PCI_DEVICE_ID_NI_PXI8420_23216,
  1759. .subvendor = PCI_ANY_ID,
  1760. .subdevice = PCI_ANY_ID,
  1761. .init = pci_ni8420_init,
  1762. .setup = pci_default_setup,
  1763. .exit = pci_ni8420_exit,
  1764. },
  1765. {
  1766. .vendor = PCI_VENDOR_ID_NI,
  1767. .device = PCI_DEVICE_ID_NI_PXI8420_2328,
  1768. .subvendor = PCI_ANY_ID,
  1769. .subdevice = PCI_ANY_ID,
  1770. .init = pci_ni8420_init,
  1771. .setup = pci_default_setup,
  1772. .exit = pci_ni8420_exit,
  1773. },
  1774. {
  1775. .vendor = PCI_VENDOR_ID_NI,
  1776. .device = PCI_DEVICE_ID_NI_PXI8420_2324,
  1777. .subvendor = PCI_ANY_ID,
  1778. .subdevice = PCI_ANY_ID,
  1779. .init = pci_ni8420_init,
  1780. .setup = pci_default_setup,
  1781. .exit = pci_ni8420_exit,
  1782. },
  1783. {
  1784. .vendor = PCI_VENDOR_ID_NI,
  1785. .device = PCI_DEVICE_ID_NI_PXI8420_2322,
  1786. .subvendor = PCI_ANY_ID,
  1787. .subdevice = PCI_ANY_ID,
  1788. .init = pci_ni8420_init,
  1789. .setup = pci_default_setup,
  1790. .exit = pci_ni8420_exit,
  1791. },
  1792. {
  1793. .vendor = PCI_VENDOR_ID_NI,
  1794. .device = PCI_DEVICE_ID_NI_PXI8422_2324,
  1795. .subvendor = PCI_ANY_ID,
  1796. .subdevice = PCI_ANY_ID,
  1797. .init = pci_ni8420_init,
  1798. .setup = pci_default_setup,
  1799. .exit = pci_ni8420_exit,
  1800. },
  1801. {
  1802. .vendor = PCI_VENDOR_ID_NI,
  1803. .device = PCI_DEVICE_ID_NI_PXI8422_2322,
  1804. .subvendor = PCI_ANY_ID,
  1805. .subdevice = PCI_ANY_ID,
  1806. .init = pci_ni8420_init,
  1807. .setup = pci_default_setup,
  1808. .exit = pci_ni8420_exit,
  1809. },
  1810. {
  1811. .vendor = PCI_VENDOR_ID_NI,
  1812. .device = PCI_ANY_ID,
  1813. .subvendor = PCI_ANY_ID,
  1814. .subdevice = PCI_ANY_ID,
  1815. .init = pci_ni8430_init,
  1816. .setup = pci_ni8430_setup,
  1817. .exit = pci_ni8430_exit,
  1818. },
  1819. /* Quatech */
  1820. {
  1821. .vendor = PCI_VENDOR_ID_QUATECH,
  1822. .device = PCI_ANY_ID,
  1823. .subvendor = PCI_ANY_ID,
  1824. .subdevice = PCI_ANY_ID,
  1825. .init = pci_quatech_init,
  1826. .setup = pci_quatech_setup,
  1827. .exit = pci_quatech_exit,
  1828. },
  1829. /*
  1830. * Panacom
  1831. */
  1832. {
  1833. .vendor = PCI_VENDOR_ID_PANACOM,
  1834. .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
  1835. .subvendor = PCI_ANY_ID,
  1836. .subdevice = PCI_ANY_ID,
  1837. .init = pci_plx9050_init,
  1838. .setup = pci_default_setup,
  1839. .exit = pci_plx9050_exit,
  1840. },
  1841. {
  1842. .vendor = PCI_VENDOR_ID_PANACOM,
  1843. .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
  1844. .subvendor = PCI_ANY_ID,
  1845. .subdevice = PCI_ANY_ID,
  1846. .init = pci_plx9050_init,
  1847. .setup = pci_default_setup,
  1848. .exit = pci_plx9050_exit,
  1849. },
  1850. /*
  1851. * Pericom (Only 7954 - It have a offset jump for port 4)
  1852. */
  1853. {
  1854. .vendor = PCI_VENDOR_ID_PERICOM,
  1855. .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
  1856. .subvendor = PCI_ANY_ID,
  1857. .subdevice = PCI_ANY_ID,
  1858. .setup = pci_pericom_setup,
  1859. },
  1860. /*
  1861. * PLX
  1862. */
  1863. {
  1864. .vendor = PCI_VENDOR_ID_PLX,
  1865. .device = PCI_DEVICE_ID_PLX_9050,
  1866. .subvendor = PCI_SUBVENDOR_ID_EXSYS,
  1867. .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
  1868. .init = pci_plx9050_init,
  1869. .setup = pci_default_setup,
  1870. .exit = pci_plx9050_exit,
  1871. },
  1872. {
  1873. .vendor = PCI_VENDOR_ID_PLX,
  1874. .device = PCI_DEVICE_ID_PLX_9050,
  1875. .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
  1876. .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
  1877. .init = pci_plx9050_init,
  1878. .setup = pci_default_setup,
  1879. .exit = pci_plx9050_exit,
  1880. },
  1881. {
  1882. .vendor = PCI_VENDOR_ID_PLX,
  1883. .device = PCI_DEVICE_ID_PLX_ROMULUS,
  1884. .subvendor = PCI_VENDOR_ID_PLX,
  1885. .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
  1886. .init = pci_plx9050_init,
  1887. .setup = pci_default_setup,
  1888. .exit = pci_plx9050_exit,
  1889. },
  1890. {
  1891. .vendor = PCI_VENDOR_ID_ACCESIO,
  1892. .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
  1893. .subvendor = PCI_ANY_ID,
  1894. .subdevice = PCI_ANY_ID,
  1895. .setup = pci_pericom_setup,
  1896. },
  1897. {
  1898. .vendor = PCI_VENDOR_ID_ACCESIO,
  1899. .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
  1900. .subvendor = PCI_ANY_ID,
  1901. .subdevice = PCI_ANY_ID,
  1902. .setup = pci_pericom_setup,
  1903. },
  1904. {
  1905. .vendor = PCI_VENDOR_ID_ACCESIO,
  1906. .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
  1907. .subvendor = PCI_ANY_ID,
  1908. .subdevice = PCI_ANY_ID,
  1909. .setup = pci_pericom_setup,
  1910. },
  1911. {
  1912. .vendor = PCI_VENDOR_ID_ACCESIO,
  1913. .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
  1914. .subvendor = PCI_ANY_ID,
  1915. .subdevice = PCI_ANY_ID,
  1916. .setup = pci_pericom_setup,
  1917. },
  1918. {
  1919. .vendor = PCI_VENDOR_ID_ACCESIO,
  1920. .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
  1921. .subvendor = PCI_ANY_ID,
  1922. .subdevice = PCI_ANY_ID,
  1923. .setup = pci_pericom_setup,
  1924. },
  1925. {
  1926. .vendor = PCI_VENDOR_ID_ACCESIO,
  1927. .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
  1928. .subvendor = PCI_ANY_ID,
  1929. .subdevice = PCI_ANY_ID,
  1930. .setup = pci_pericom_setup,
  1931. },
  1932. {
  1933. .vendor = PCI_VENDOR_ID_ACCESIO,
  1934. .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
  1935. .subvendor = PCI_ANY_ID,
  1936. .subdevice = PCI_ANY_ID,
  1937. .setup = pci_pericom_setup,
  1938. },
  1939. {
  1940. .vendor = PCI_VENDOR_ID_ACCESIO,
  1941. .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
  1942. .subvendor = PCI_ANY_ID,
  1943. .subdevice = PCI_ANY_ID,
  1944. .setup = pci_pericom_setup,
  1945. },
  1946. {
  1947. .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
  1948. .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
  1949. .subvendor = PCI_ANY_ID,
  1950. .subdevice = PCI_ANY_ID,
  1951. .setup = pci_pericom_setup,
  1952. },
  1953. {
  1954. .vendor = PCI_VENDOR_ID_ACCESIO,
  1955. .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
  1956. .subvendor = PCI_ANY_ID,
  1957. .subdevice = PCI_ANY_ID,
  1958. .setup = pci_pericom_setup,
  1959. },
  1960. {
  1961. .vendor = PCI_VENDOR_ID_ACCESIO,
  1962. .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
  1963. .subvendor = PCI_ANY_ID,
  1964. .subdevice = PCI_ANY_ID,
  1965. .setup = pci_pericom_setup,
  1966. },
  1967. {
  1968. .vendor = PCI_VENDOR_ID_ACCESIO,
  1969. .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
  1970. .subvendor = PCI_ANY_ID,
  1971. .subdevice = PCI_ANY_ID,
  1972. .setup = pci_pericom_setup,
  1973. },
  1974. {
  1975. .vendor = PCI_VENDOR_ID_ACCESIO,
  1976. .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
  1977. .subvendor = PCI_ANY_ID,
  1978. .subdevice = PCI_ANY_ID,
  1979. .setup = pci_pericom_setup,
  1980. },
  1981. {
  1982. .vendor = PCI_VENDOR_ID_ACCESIO,
  1983. .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
  1984. .subvendor = PCI_ANY_ID,
  1985. .subdevice = PCI_ANY_ID,
  1986. .setup = pci_pericom_setup,
  1987. },
  1988. {
  1989. .vendor = PCI_VENDOR_ID_ACCESIO,
  1990. .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
  1991. .subvendor = PCI_ANY_ID,
  1992. .subdevice = PCI_ANY_ID,
  1993. .setup = pci_pericom_setup,
  1994. },
  1995. /*
  1996. * SBS Technologies, Inc., PMC-OCTALPRO 232
  1997. */
  1998. {
  1999. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  2000. .device = PCI_DEVICE_ID_OCTPRO,
  2001. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  2002. .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
  2003. .init = sbs_init,
  2004. .setup = sbs_setup,
  2005. .exit = sbs_exit,
  2006. },
  2007. /*
  2008. * SBS Technologies, Inc., PMC-OCTALPRO 422
  2009. */
  2010. {
  2011. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  2012. .device = PCI_DEVICE_ID_OCTPRO,
  2013. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  2014. .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
  2015. .init = sbs_init,
  2016. .setup = sbs_setup,
  2017. .exit = sbs_exit,
  2018. },
  2019. /*
  2020. * SBS Technologies, Inc., P-Octal 232
  2021. */
  2022. {
  2023. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  2024. .device = PCI_DEVICE_ID_OCTPRO,
  2025. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  2026. .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
  2027. .init = sbs_init,
  2028. .setup = sbs_setup,
  2029. .exit = sbs_exit,
  2030. },
  2031. /*
  2032. * SBS Technologies, Inc., P-Octal 422
  2033. */
  2034. {
  2035. .vendor = PCI_VENDOR_ID_SBSMODULARIO,
  2036. .device = PCI_DEVICE_ID_OCTPRO,
  2037. .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
  2038. .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
  2039. .init = sbs_init,
  2040. .setup = sbs_setup,
  2041. .exit = sbs_exit,
  2042. },
  2043. /*
  2044. * SIIG cards - these may be called via parport_serial
  2045. */
  2046. {
  2047. .vendor = PCI_VENDOR_ID_SIIG,
  2048. .device = PCI_ANY_ID,
  2049. .subvendor = PCI_ANY_ID,
  2050. .subdevice = PCI_ANY_ID,
  2051. .init = pci_siig_init,
  2052. .setup = pci_siig_setup,
  2053. },
  2054. /*
  2055. * Titan cards
  2056. */
  2057. {
  2058. .vendor = PCI_VENDOR_ID_TITAN,
  2059. .device = PCI_DEVICE_ID_TITAN_400L,
  2060. .subvendor = PCI_ANY_ID,
  2061. .subdevice = PCI_ANY_ID,
  2062. .setup = titan_400l_800l_setup,
  2063. },
  2064. {
  2065. .vendor = PCI_VENDOR_ID_TITAN,
  2066. .device = PCI_DEVICE_ID_TITAN_800L,
  2067. .subvendor = PCI_ANY_ID,
  2068. .subdevice = PCI_ANY_ID,
  2069. .setup = titan_400l_800l_setup,
  2070. },
  2071. /*
  2072. * Timedia cards
  2073. */
  2074. {
  2075. .vendor = PCI_VENDOR_ID_TIMEDIA,
  2076. .device = PCI_DEVICE_ID_TIMEDIA_1889,
  2077. .subvendor = PCI_VENDOR_ID_TIMEDIA,
  2078. .subdevice = PCI_ANY_ID,
  2079. .probe = pci_timedia_probe,
  2080. .init = pci_timedia_init,
  2081. .setup = pci_timedia_setup,
  2082. },
  2083. {
  2084. .vendor = PCI_VENDOR_ID_TIMEDIA,
  2085. .device = PCI_ANY_ID,
  2086. .subvendor = PCI_ANY_ID,
  2087. .subdevice = PCI_ANY_ID,
  2088. .setup = pci_timedia_setup,
  2089. },
  2090. /*
  2091. * SUNIX (Timedia) cards
  2092. * Do not "probe" for these cards as there is at least one combination
  2093. * card that should be handled by parport_pc that doesn't match the
  2094. * rule in pci_timedia_probe.
  2095. * It is part number is MIO5079A but its subdevice ID is 0x0102.
  2096. * There are some boards with part number SER5037AL that report
  2097. * subdevice ID 0x0002.
  2098. */
  2099. {
  2100. .vendor = PCI_VENDOR_ID_SUNIX,
  2101. .device = PCI_DEVICE_ID_SUNIX_1999,
  2102. .subvendor = PCI_VENDOR_ID_SUNIX,
  2103. .subdevice = PCI_ANY_ID,
  2104. .init = pci_timedia_init,
  2105. .setup = pci_timedia_setup,
  2106. },
  2107. /*
  2108. * Exar cards
  2109. */
  2110. {
  2111. .vendor = PCI_VENDOR_ID_EXAR,
  2112. .device = PCI_DEVICE_ID_EXAR_XR17C152,
  2113. .subvendor = PCI_ANY_ID,
  2114. .subdevice = PCI_ANY_ID,
  2115. .setup = pci_xr17c154_setup,
  2116. },
  2117. {
  2118. .vendor = PCI_VENDOR_ID_EXAR,
  2119. .device = PCI_DEVICE_ID_EXAR_XR17C154,
  2120. .subvendor = PCI_ANY_ID,
  2121. .subdevice = PCI_ANY_ID,
  2122. .setup = pci_xr17c154_setup,
  2123. },
  2124. {
  2125. .vendor = PCI_VENDOR_ID_EXAR,
  2126. .device = PCI_DEVICE_ID_EXAR_XR17C158,
  2127. .subvendor = PCI_ANY_ID,
  2128. .subdevice = PCI_ANY_ID,
  2129. .setup = pci_xr17c154_setup,
  2130. },
  2131. {
  2132. .vendor = PCI_VENDOR_ID_EXAR,
  2133. .device = PCI_DEVICE_ID_EXAR_XR17V352,
  2134. .subvendor = PCI_ANY_ID,
  2135. .subdevice = PCI_ANY_ID,
  2136. .setup = pci_xr17v35x_setup,
  2137. },
  2138. {
  2139. .vendor = PCI_VENDOR_ID_EXAR,
  2140. .device = PCI_DEVICE_ID_EXAR_XR17V354,
  2141. .subvendor = PCI_ANY_ID,
  2142. .subdevice = PCI_ANY_ID,
  2143. .setup = pci_xr17v35x_setup,
  2144. },
  2145. {
  2146. .vendor = PCI_VENDOR_ID_EXAR,
  2147. .device = PCI_DEVICE_ID_EXAR_XR17V358,
  2148. .subvendor = PCI_ANY_ID,
  2149. .subdevice = PCI_ANY_ID,
  2150. .setup = pci_xr17v35x_setup,
  2151. },
  2152. {
  2153. .vendor = PCI_VENDOR_ID_EXAR,
  2154. .device = PCI_DEVICE_ID_EXAR_XR17V4358,
  2155. .subvendor = PCI_ANY_ID,
  2156. .subdevice = PCI_ANY_ID,
  2157. .setup = pci_xr17v35x_setup,
  2158. },
  2159. {
  2160. .vendor = PCI_VENDOR_ID_EXAR,
  2161. .device = PCI_DEVICE_ID_EXAR_XR17V8358,
  2162. .subvendor = PCI_ANY_ID,
  2163. .subdevice = PCI_ANY_ID,
  2164. .setup = pci_xr17v35x_setup,
  2165. },
  2166. /*
  2167. * Xircom cards
  2168. */
  2169. {
  2170. .vendor = PCI_VENDOR_ID_XIRCOM,
  2171. .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
  2172. .subvendor = PCI_ANY_ID,
  2173. .subdevice = PCI_ANY_ID,
  2174. .init = pci_xircom_init,
  2175. .setup = pci_default_setup,
  2176. },
  2177. /*
  2178. * Netmos cards - these may be called via parport_serial
  2179. */
  2180. {
  2181. .vendor = PCI_VENDOR_ID_NETMOS,
  2182. .device = PCI_ANY_ID,
  2183. .subvendor = PCI_ANY_ID,
  2184. .subdevice = PCI_ANY_ID,
  2185. .init = pci_netmos_init,
  2186. .setup = pci_netmos_9900_setup,
  2187. },
  2188. /*
  2189. * EndRun Technologies
  2190. */
  2191. {
  2192. .vendor = PCI_VENDOR_ID_ENDRUN,
  2193. .device = PCI_ANY_ID,
  2194. .subvendor = PCI_ANY_ID,
  2195. .subdevice = PCI_ANY_ID,
  2196. .init = pci_endrun_init,
  2197. .setup = pci_default_setup,
  2198. },
  2199. /*
  2200. * For Oxford Semiconductor Tornado based devices
  2201. */
  2202. {
  2203. .vendor = PCI_VENDOR_ID_OXSEMI,
  2204. .device = PCI_ANY_ID,
  2205. .subvendor = PCI_ANY_ID,
  2206. .subdevice = PCI_ANY_ID,
  2207. .init = pci_oxsemi_tornado_init,
  2208. .setup = pci_default_setup,
  2209. },
  2210. {
  2211. .vendor = PCI_VENDOR_ID_MAINPINE,
  2212. .device = PCI_ANY_ID,
  2213. .subvendor = PCI_ANY_ID,
  2214. .subdevice = PCI_ANY_ID,
  2215. .init = pci_oxsemi_tornado_init,
  2216. .setup = pci_default_setup,
  2217. },
  2218. {
  2219. .vendor = PCI_VENDOR_ID_DIGI,
  2220. .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
  2221. .subvendor = PCI_SUBVENDOR_ID_IBM,
  2222. .subdevice = PCI_ANY_ID,
  2223. .init = pci_oxsemi_tornado_init,
  2224. .setup = pci_default_setup,
  2225. },
  2226. {
  2227. .vendor = PCI_VENDOR_ID_INTEL,
  2228. .device = 0x8811,
  2229. .subvendor = PCI_ANY_ID,
  2230. .subdevice = PCI_ANY_ID,
  2231. .init = pci_eg20t_init,
  2232. .setup = pci_default_setup,
  2233. },
  2234. {
  2235. .vendor = PCI_VENDOR_ID_INTEL,
  2236. .device = 0x8812,
  2237. .subvendor = PCI_ANY_ID,
  2238. .subdevice = PCI_ANY_ID,
  2239. .init = pci_eg20t_init,
  2240. .setup = pci_default_setup,
  2241. },
  2242. {
  2243. .vendor = PCI_VENDOR_ID_INTEL,
  2244. .device = 0x8813,
  2245. .subvendor = PCI_ANY_ID,
  2246. .subdevice = PCI_ANY_ID,
  2247. .init = pci_eg20t_init,
  2248. .setup = pci_default_setup,
  2249. },
  2250. {
  2251. .vendor = PCI_VENDOR_ID_INTEL,
  2252. .device = 0x8814,
  2253. .subvendor = PCI_ANY_ID,
  2254. .subdevice = PCI_ANY_ID,
  2255. .init = pci_eg20t_init,
  2256. .setup = pci_default_setup,
  2257. },
  2258. {
  2259. .vendor = 0x10DB,
  2260. .device = 0x8027,
  2261. .subvendor = PCI_ANY_ID,
  2262. .subdevice = PCI_ANY_ID,
  2263. .init = pci_eg20t_init,
  2264. .setup = pci_default_setup,
  2265. },
  2266. {
  2267. .vendor = 0x10DB,
  2268. .device = 0x8028,
  2269. .subvendor = PCI_ANY_ID,
  2270. .subdevice = PCI_ANY_ID,
  2271. .init = pci_eg20t_init,
  2272. .setup = pci_default_setup,
  2273. },
  2274. {
  2275. .vendor = 0x10DB,
  2276. .device = 0x8029,
  2277. .subvendor = PCI_ANY_ID,
  2278. .subdevice = PCI_ANY_ID,
  2279. .init = pci_eg20t_init,
  2280. .setup = pci_default_setup,
  2281. },
  2282. {
  2283. .vendor = 0x10DB,
  2284. .device = 0x800C,
  2285. .subvendor = PCI_ANY_ID,
  2286. .subdevice = PCI_ANY_ID,
  2287. .init = pci_eg20t_init,
  2288. .setup = pci_default_setup,
  2289. },
  2290. {
  2291. .vendor = 0x10DB,
  2292. .device = 0x800D,
  2293. .subvendor = PCI_ANY_ID,
  2294. .subdevice = PCI_ANY_ID,
  2295. .init = pci_eg20t_init,
  2296. .setup = pci_default_setup,
  2297. },
  2298. /*
  2299. * Cronyx Omega PCI (PLX-chip based)
  2300. */
  2301. {
  2302. .vendor = PCI_VENDOR_ID_PLX,
  2303. .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
  2304. .subvendor = PCI_ANY_ID,
  2305. .subdevice = PCI_ANY_ID,
  2306. .setup = pci_omegapci_setup,
  2307. },
  2308. /* WCH CH353 1S1P card (16550 clone) */
  2309. {
  2310. .vendor = PCI_VENDOR_ID_WCH,
  2311. .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
  2312. .subvendor = PCI_ANY_ID,
  2313. .subdevice = PCI_ANY_ID,
  2314. .setup = pci_wch_ch353_setup,
  2315. },
  2316. /* WCH CH353 2S1P card (16550 clone) */
  2317. {
  2318. .vendor = PCI_VENDOR_ID_WCH,
  2319. .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
  2320. .subvendor = PCI_ANY_ID,
  2321. .subdevice = PCI_ANY_ID,
  2322. .setup = pci_wch_ch353_setup,
  2323. },
  2324. /* WCH CH353 4S card (16550 clone) */
  2325. {
  2326. .vendor = PCI_VENDOR_ID_WCH,
  2327. .device = PCI_DEVICE_ID_WCH_CH353_4S,
  2328. .subvendor = PCI_ANY_ID,
  2329. .subdevice = PCI_ANY_ID,
  2330. .setup = pci_wch_ch353_setup,
  2331. },
  2332. /* WCH CH353 2S1PF card (16550 clone) */
  2333. {
  2334. .vendor = PCI_VENDOR_ID_WCH,
  2335. .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
  2336. .subvendor = PCI_ANY_ID,
  2337. .subdevice = PCI_ANY_ID,
  2338. .setup = pci_wch_ch353_setup,
  2339. },
  2340. /* WCH CH352 2S card (16550 clone) */
  2341. {
  2342. .vendor = PCI_VENDOR_ID_WCH,
  2343. .device = PCI_DEVICE_ID_WCH_CH352_2S,
  2344. .subvendor = PCI_ANY_ID,
  2345. .subdevice = PCI_ANY_ID,
  2346. .setup = pci_wch_ch353_setup,
  2347. },
  2348. /* WCH CH355 4S card (16550 clone) */
  2349. {
  2350. .vendor = PCI_VENDOR_ID_WCH,
  2351. .device = PCI_DEVICE_ID_WCH_CH355_4S,
  2352. .subvendor = PCI_ANY_ID,
  2353. .subdevice = PCI_ANY_ID,
  2354. .setup = pci_wch_ch355_setup,
  2355. },
  2356. /* WCH CH382 2S card (16850 clone) */
  2357. {
  2358. .vendor = PCIE_VENDOR_ID_WCH,
  2359. .device = PCIE_DEVICE_ID_WCH_CH382_2S,
  2360. .subvendor = PCI_ANY_ID,
  2361. .subdevice = PCI_ANY_ID,
  2362. .setup = pci_wch_ch38x_setup,
  2363. },
  2364. /* WCH CH382 2S1P card (16850 clone) */
  2365. {
  2366. .vendor = PCIE_VENDOR_ID_WCH,
  2367. .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
  2368. .subvendor = PCI_ANY_ID,
  2369. .subdevice = PCI_ANY_ID,
  2370. .setup = pci_wch_ch38x_setup,
  2371. },
  2372. /* WCH CH384 4S card (16850 clone) */
  2373. {
  2374. .vendor = PCIE_VENDOR_ID_WCH,
  2375. .device = PCIE_DEVICE_ID_WCH_CH384_4S,
  2376. .subvendor = PCI_ANY_ID,
  2377. .subdevice = PCI_ANY_ID,
  2378. .setup = pci_wch_ch38x_setup,
  2379. },
  2380. /*
  2381. * ASIX devices with FIFO bug
  2382. */
  2383. {
  2384. .vendor = PCI_VENDOR_ID_ASIX,
  2385. .device = PCI_ANY_ID,
  2386. .subvendor = PCI_ANY_ID,
  2387. .subdevice = PCI_ANY_ID,
  2388. .setup = pci_asix_setup,
  2389. },
  2390. /*
  2391. * Commtech, Inc. Fastcom adapters
  2392. *
  2393. */
  2394. {
  2395. .vendor = PCI_VENDOR_ID_COMMTECH,
  2396. .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
  2397. .subvendor = PCI_ANY_ID,
  2398. .subdevice = PCI_ANY_ID,
  2399. .setup = pci_fastcom335_setup,
  2400. },
  2401. {
  2402. .vendor = PCI_VENDOR_ID_COMMTECH,
  2403. .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
  2404. .subvendor = PCI_ANY_ID,
  2405. .subdevice = PCI_ANY_ID,
  2406. .setup = pci_fastcom335_setup,
  2407. },
  2408. {
  2409. .vendor = PCI_VENDOR_ID_COMMTECH,
  2410. .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
  2411. .subvendor = PCI_ANY_ID,
  2412. .subdevice = PCI_ANY_ID,
  2413. .setup = pci_fastcom335_setup,
  2414. },
  2415. {
  2416. .vendor = PCI_VENDOR_ID_COMMTECH,
  2417. .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
  2418. .subvendor = PCI_ANY_ID,
  2419. .subdevice = PCI_ANY_ID,
  2420. .setup = pci_fastcom335_setup,
  2421. },
  2422. {
  2423. .vendor = PCI_VENDOR_ID_COMMTECH,
  2424. .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
  2425. .subvendor = PCI_ANY_ID,
  2426. .subdevice = PCI_ANY_ID,
  2427. .setup = pci_xr17v35x_setup,
  2428. },
  2429. {
  2430. .vendor = PCI_VENDOR_ID_COMMTECH,
  2431. .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
  2432. .subvendor = PCI_ANY_ID,
  2433. .subdevice = PCI_ANY_ID,
  2434. .setup = pci_xr17v35x_setup,
  2435. },
  2436. {
  2437. .vendor = PCI_VENDOR_ID_COMMTECH,
  2438. .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
  2439. .subvendor = PCI_ANY_ID,
  2440. .subdevice = PCI_ANY_ID,
  2441. .setup = pci_xr17v35x_setup,
  2442. },
  2443. /*
  2444. * Broadcom TruManage (NetXtreme)
  2445. */
  2446. {
  2447. .vendor = PCI_VENDOR_ID_BROADCOM,
  2448. .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
  2449. .subvendor = PCI_ANY_ID,
  2450. .subdevice = PCI_ANY_ID,
  2451. .setup = pci_brcm_trumanage_setup,
  2452. },
  2453. {
  2454. .vendor = 0x1c29,
  2455. .device = 0x1104,
  2456. .subvendor = PCI_ANY_ID,
  2457. .subdevice = PCI_ANY_ID,
  2458. .setup = pci_fintek_setup,
  2459. .init = pci_fintek_init,
  2460. },
  2461. {
  2462. .vendor = 0x1c29,
  2463. .device = 0x1108,
  2464. .subvendor = PCI_ANY_ID,
  2465. .subdevice = PCI_ANY_ID,
  2466. .setup = pci_fintek_setup,
  2467. .init = pci_fintek_init,
  2468. },
  2469. {
  2470. .vendor = 0x1c29,
  2471. .device = 0x1112,
  2472. .subvendor = PCI_ANY_ID,
  2473. .subdevice = PCI_ANY_ID,
  2474. .setup = pci_fintek_setup,
  2475. .init = pci_fintek_init,
  2476. },
  2477. /*
  2478. * Default "match everything" terminator entry
  2479. */
  2480. {
  2481. .vendor = PCI_ANY_ID,
  2482. .device = PCI_ANY_ID,
  2483. .subvendor = PCI_ANY_ID,
  2484. .subdevice = PCI_ANY_ID,
  2485. .setup = pci_default_setup,
  2486. }
  2487. };
  2488. static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
  2489. {
  2490. return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
  2491. }
  2492. static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
  2493. {
  2494. struct pci_serial_quirk *quirk;
  2495. for (quirk = pci_serial_quirks; ; quirk++)
  2496. if (quirk_id_matches(quirk->vendor, dev->vendor) &&
  2497. quirk_id_matches(quirk->device, dev->device) &&
  2498. quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
  2499. quirk_id_matches(quirk->subdevice, dev->subsystem_device))
  2500. break;
  2501. return quirk;
  2502. }
  2503. static inline int get_pci_irq(struct pci_dev *dev,
  2504. const struct pciserial_board *board)
  2505. {
  2506. if (board->flags & FL_NOIRQ)
  2507. return 0;
  2508. else
  2509. return dev->irq;
  2510. }
  2511. /*
  2512. * This is the configuration table for all of the PCI serial boards
  2513. * which we support. It is directly indexed by the pci_board_num_t enum
  2514. * value, which is encoded in the pci_device_id PCI probe table's
  2515. * driver_data member.
  2516. *
  2517. * The makeup of these names are:
  2518. * pbn_bn{_bt}_n_baud{_offsetinhex}
  2519. *
  2520. * bn = PCI BAR number
  2521. * bt = Index using PCI BARs
  2522. * n = number of serial ports
  2523. * baud = baud rate
  2524. * offsetinhex = offset for each sequential port (in hex)
  2525. *
  2526. * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
  2527. *
  2528. * Please note: in theory if n = 1, _bt infix should make no difference.
  2529. * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
  2530. */
  2531. enum pci_board_num_t {
  2532. pbn_default = 0,
  2533. pbn_b0_1_115200,
  2534. pbn_b0_2_115200,
  2535. pbn_b0_4_115200,
  2536. pbn_b0_5_115200,
  2537. pbn_b0_8_115200,
  2538. pbn_b0_1_921600,
  2539. pbn_b0_2_921600,
  2540. pbn_b0_4_921600,
  2541. pbn_b0_2_1130000,
  2542. pbn_b0_4_1152000,
  2543. pbn_b0_2_1152000_200,
  2544. pbn_b0_4_1152000_200,
  2545. pbn_b0_8_1152000_200,
  2546. pbn_b0_4_1250000,
  2547. pbn_b0_2_1843200,
  2548. pbn_b0_4_1843200,
  2549. pbn_b0_2_1843200_200,
  2550. pbn_b0_4_1843200_200,
  2551. pbn_b0_8_1843200_200,
  2552. pbn_b0_1_4000000,
  2553. pbn_b0_bt_1_115200,
  2554. pbn_b0_bt_2_115200,
  2555. pbn_b0_bt_4_115200,
  2556. pbn_b0_bt_8_115200,
  2557. pbn_b0_bt_1_460800,
  2558. pbn_b0_bt_2_460800,
  2559. pbn_b0_bt_4_460800,
  2560. pbn_b0_bt_1_921600,
  2561. pbn_b0_bt_2_921600,
  2562. pbn_b0_bt_4_921600,
  2563. pbn_b0_bt_8_921600,
  2564. pbn_b1_1_115200,
  2565. pbn_b1_2_115200,
  2566. pbn_b1_4_115200,
  2567. pbn_b1_8_115200,
  2568. pbn_b1_16_115200,
  2569. pbn_b1_1_921600,
  2570. pbn_b1_2_921600,
  2571. pbn_b1_4_921600,
  2572. pbn_b1_8_921600,
  2573. pbn_b1_2_1250000,
  2574. pbn_b1_bt_1_115200,
  2575. pbn_b1_bt_2_115200,
  2576. pbn_b1_bt_4_115200,
  2577. pbn_b1_bt_2_921600,
  2578. pbn_b1_1_1382400,
  2579. pbn_b1_2_1382400,
  2580. pbn_b1_4_1382400,
  2581. pbn_b1_8_1382400,
  2582. pbn_b2_1_115200,
  2583. pbn_b2_2_115200,
  2584. pbn_b2_4_115200,
  2585. pbn_b2_8_115200,
  2586. pbn_b2_1_460800,
  2587. pbn_b2_4_460800,
  2588. pbn_b2_8_460800,
  2589. pbn_b2_16_460800,
  2590. pbn_b2_1_921600,
  2591. pbn_b2_4_921600,
  2592. pbn_b2_8_921600,
  2593. pbn_b2_8_1152000,
  2594. pbn_b2_bt_1_115200,
  2595. pbn_b2_bt_2_115200,
  2596. pbn_b2_bt_4_115200,
  2597. pbn_b2_bt_2_921600,
  2598. pbn_b2_bt_4_921600,
  2599. pbn_b3_2_115200,
  2600. pbn_b3_4_115200,
  2601. pbn_b3_8_115200,
  2602. pbn_b4_bt_2_921600,
  2603. pbn_b4_bt_4_921600,
  2604. pbn_b4_bt_8_921600,
  2605. /*
  2606. * Board-specific versions.
  2607. */
  2608. pbn_panacom,
  2609. pbn_panacom2,
  2610. pbn_panacom4,
  2611. pbn_plx_romulus,
  2612. pbn_endrun_2_4000000,
  2613. pbn_oxsemi,
  2614. pbn_oxsemi_1_4000000,
  2615. pbn_oxsemi_2_4000000,
  2616. pbn_oxsemi_4_4000000,
  2617. pbn_oxsemi_8_4000000,
  2618. pbn_intel_i960,
  2619. pbn_sgi_ioc3,
  2620. pbn_computone_4,
  2621. pbn_computone_6,
  2622. pbn_computone_8,
  2623. pbn_sbsxrsio,
  2624. pbn_exar_XR17C152,
  2625. pbn_exar_XR17C154,
  2626. pbn_exar_XR17C158,
  2627. pbn_exar_XR17V352,
  2628. pbn_exar_XR17V354,
  2629. pbn_exar_XR17V358,
  2630. pbn_exar_XR17V4358,
  2631. pbn_exar_XR17V8358,
  2632. pbn_exar_ibm_saturn,
  2633. pbn_pasemi_1682M,
  2634. pbn_ni8430_2,
  2635. pbn_ni8430_4,
  2636. pbn_ni8430_8,
  2637. pbn_ni8430_16,
  2638. pbn_ADDIDATA_PCIe_1_3906250,
  2639. pbn_ADDIDATA_PCIe_2_3906250,
  2640. pbn_ADDIDATA_PCIe_4_3906250,
  2641. pbn_ADDIDATA_PCIe_8_3906250,
  2642. pbn_ce4100_1_115200,
  2643. pbn_omegapci,
  2644. pbn_NETMOS9900_2s_115200,
  2645. pbn_brcm_trumanage,
  2646. pbn_fintek_4,
  2647. pbn_fintek_8,
  2648. pbn_fintek_12,
  2649. pbn_wch382_2,
  2650. pbn_wch384_4,
  2651. pbn_pericom_PI7C9X7951,
  2652. pbn_pericom_PI7C9X7952,
  2653. pbn_pericom_PI7C9X7954,
  2654. pbn_pericom_PI7C9X7958,
  2655. };
  2656. /*
  2657. * uart_offset - the space between channels
  2658. * reg_shift - describes how the UART registers are mapped
  2659. * to PCI memory by the card.
  2660. * For example IER register on SBS, Inc. PMC-OctPro is located at
  2661. * offset 0x10 from the UART base, while UART_IER is defined as 1
  2662. * in include/linux/serial_reg.h,
  2663. * see first lines of serial_in() and serial_out() in 8250.c
  2664. */
  2665. static struct pciserial_board pci_boards[] = {
  2666. [pbn_default] = {
  2667. .flags = FL_BASE0,
  2668. .num_ports = 1,
  2669. .base_baud = 115200,
  2670. .uart_offset = 8,
  2671. },
  2672. [pbn_b0_1_115200] = {
  2673. .flags = FL_BASE0,
  2674. .num_ports = 1,
  2675. .base_baud = 115200,
  2676. .uart_offset = 8,
  2677. },
  2678. [pbn_b0_2_115200] = {
  2679. .flags = FL_BASE0,
  2680. .num_ports = 2,
  2681. .base_baud = 115200,
  2682. .uart_offset = 8,
  2683. },
  2684. [pbn_b0_4_115200] = {
  2685. .flags = FL_BASE0,
  2686. .num_ports = 4,
  2687. .base_baud = 115200,
  2688. .uart_offset = 8,
  2689. },
  2690. [pbn_b0_5_115200] = {
  2691. .flags = FL_BASE0,
  2692. .num_ports = 5,
  2693. .base_baud = 115200,
  2694. .uart_offset = 8,
  2695. },
  2696. [pbn_b0_8_115200] = {
  2697. .flags = FL_BASE0,
  2698. .num_ports = 8,
  2699. .base_baud = 115200,
  2700. .uart_offset = 8,
  2701. },
  2702. [pbn_b0_1_921600] = {
  2703. .flags = FL_BASE0,
  2704. .num_ports = 1,
  2705. .base_baud = 921600,
  2706. .uart_offset = 8,
  2707. },
  2708. [pbn_b0_2_921600] = {
  2709. .flags = FL_BASE0,
  2710. .num_ports = 2,
  2711. .base_baud = 921600,
  2712. .uart_offset = 8,
  2713. },
  2714. [pbn_b0_4_921600] = {
  2715. .flags = FL_BASE0,
  2716. .num_ports = 4,
  2717. .base_baud = 921600,
  2718. .uart_offset = 8,
  2719. },
  2720. [pbn_b0_2_1130000] = {
  2721. .flags = FL_BASE0,
  2722. .num_ports = 2,
  2723. .base_baud = 1130000,
  2724. .uart_offset = 8,
  2725. },
  2726. [pbn_b0_4_1152000] = {
  2727. .flags = FL_BASE0,
  2728. .num_ports = 4,
  2729. .base_baud = 1152000,
  2730. .uart_offset = 8,
  2731. },
  2732. [pbn_b0_2_1152000_200] = {
  2733. .flags = FL_BASE0,
  2734. .num_ports = 2,
  2735. .base_baud = 1152000,
  2736. .uart_offset = 0x200,
  2737. },
  2738. [pbn_b0_4_1152000_200] = {
  2739. .flags = FL_BASE0,
  2740. .num_ports = 4,
  2741. .base_baud = 1152000,
  2742. .uart_offset = 0x200,
  2743. },
  2744. [pbn_b0_8_1152000_200] = {
  2745. .flags = FL_BASE0,
  2746. .num_ports = 8,
  2747. .base_baud = 1152000,
  2748. .uart_offset = 0x200,
  2749. },
  2750. [pbn_b0_4_1250000] = {
  2751. .flags = FL_BASE0,
  2752. .num_ports = 4,
  2753. .base_baud = 1250000,
  2754. .uart_offset = 8,
  2755. },
  2756. [pbn_b0_2_1843200] = {
  2757. .flags = FL_BASE0,
  2758. .num_ports = 2,
  2759. .base_baud = 1843200,
  2760. .uart_offset = 8,
  2761. },
  2762. [pbn_b0_4_1843200] = {
  2763. .flags = FL_BASE0,
  2764. .num_ports = 4,
  2765. .base_baud = 1843200,
  2766. .uart_offset = 8,
  2767. },
  2768. [pbn_b0_2_1843200_200] = {
  2769. .flags = FL_BASE0,
  2770. .num_ports = 2,
  2771. .base_baud = 1843200,
  2772. .uart_offset = 0x200,
  2773. },
  2774. [pbn_b0_4_1843200_200] = {
  2775. .flags = FL_BASE0,
  2776. .num_ports = 4,
  2777. .base_baud = 1843200,
  2778. .uart_offset = 0x200,
  2779. },
  2780. [pbn_b0_8_1843200_200] = {
  2781. .flags = FL_BASE0,
  2782. .num_ports = 8,
  2783. .base_baud = 1843200,
  2784. .uart_offset = 0x200,
  2785. },
  2786. [pbn_b0_1_4000000] = {
  2787. .flags = FL_BASE0,
  2788. .num_ports = 1,
  2789. .base_baud = 4000000,
  2790. .uart_offset = 8,
  2791. },
  2792. [pbn_b0_bt_1_115200] = {
  2793. .flags = FL_BASE0|FL_BASE_BARS,
  2794. .num_ports = 1,
  2795. .base_baud = 115200,
  2796. .uart_offset = 8,
  2797. },
  2798. [pbn_b0_bt_2_115200] = {
  2799. .flags = FL_BASE0|FL_BASE_BARS,
  2800. .num_ports = 2,
  2801. .base_baud = 115200,
  2802. .uart_offset = 8,
  2803. },
  2804. [pbn_b0_bt_4_115200] = {
  2805. .flags = FL_BASE0|FL_BASE_BARS,
  2806. .num_ports = 4,
  2807. .base_baud = 115200,
  2808. .uart_offset = 8,
  2809. },
  2810. [pbn_b0_bt_8_115200] = {
  2811. .flags = FL_BASE0|FL_BASE_BARS,
  2812. .num_ports = 8,
  2813. .base_baud = 115200,
  2814. .uart_offset = 8,
  2815. },
  2816. [pbn_b0_bt_1_460800] = {
  2817. .flags = FL_BASE0|FL_BASE_BARS,
  2818. .num_ports = 1,
  2819. .base_baud = 460800,
  2820. .uart_offset = 8,
  2821. },
  2822. [pbn_b0_bt_2_460800] = {
  2823. .flags = FL_BASE0|FL_BASE_BARS,
  2824. .num_ports = 2,
  2825. .base_baud = 460800,
  2826. .uart_offset = 8,
  2827. },
  2828. [pbn_b0_bt_4_460800] = {
  2829. .flags = FL_BASE0|FL_BASE_BARS,
  2830. .num_ports = 4,
  2831. .base_baud = 460800,
  2832. .uart_offset = 8,
  2833. },
  2834. [pbn_b0_bt_1_921600] = {
  2835. .flags = FL_BASE0|FL_BASE_BARS,
  2836. .num_ports = 1,
  2837. .base_baud = 921600,
  2838. .uart_offset = 8,
  2839. },
  2840. [pbn_b0_bt_2_921600] = {
  2841. .flags = FL_BASE0|FL_BASE_BARS,
  2842. .num_ports = 2,
  2843. .base_baud = 921600,
  2844. .uart_offset = 8,
  2845. },
  2846. [pbn_b0_bt_4_921600] = {
  2847. .flags = FL_BASE0|FL_BASE_BARS,
  2848. .num_ports = 4,
  2849. .base_baud = 921600,
  2850. .uart_offset = 8,
  2851. },
  2852. [pbn_b0_bt_8_921600] = {
  2853. .flags = FL_BASE0|FL_BASE_BARS,
  2854. .num_ports = 8,
  2855. .base_baud = 921600,
  2856. .uart_offset = 8,
  2857. },
  2858. [pbn_b1_1_115200] = {
  2859. .flags = FL_BASE1,
  2860. .num_ports = 1,
  2861. .base_baud = 115200,
  2862. .uart_offset = 8,
  2863. },
  2864. [pbn_b1_2_115200] = {
  2865. .flags = FL_BASE1,
  2866. .num_ports = 2,
  2867. .base_baud = 115200,
  2868. .uart_offset = 8,
  2869. },
  2870. [pbn_b1_4_115200] = {
  2871. .flags = FL_BASE1,
  2872. .num_ports = 4,
  2873. .base_baud = 115200,
  2874. .uart_offset = 8,
  2875. },
  2876. [pbn_b1_8_115200] = {
  2877. .flags = FL_BASE1,
  2878. .num_ports = 8,
  2879. .base_baud = 115200,
  2880. .uart_offset = 8,
  2881. },
  2882. [pbn_b1_16_115200] = {
  2883. .flags = FL_BASE1,
  2884. .num_ports = 16,
  2885. .base_baud = 115200,
  2886. .uart_offset = 8,
  2887. },
  2888. [pbn_b1_1_921600] = {
  2889. .flags = FL_BASE1,
  2890. .num_ports = 1,
  2891. .base_baud = 921600,
  2892. .uart_offset = 8,
  2893. },
  2894. [pbn_b1_2_921600] = {
  2895. .flags = FL_BASE1,
  2896. .num_ports = 2,
  2897. .base_baud = 921600,
  2898. .uart_offset = 8,
  2899. },
  2900. [pbn_b1_4_921600] = {
  2901. .flags = FL_BASE1,
  2902. .num_ports = 4,
  2903. .base_baud = 921600,
  2904. .uart_offset = 8,
  2905. },
  2906. [pbn_b1_8_921600] = {
  2907. .flags = FL_BASE1,
  2908. .num_ports = 8,
  2909. .base_baud = 921600,
  2910. .uart_offset = 8,
  2911. },
  2912. [pbn_b1_2_1250000] = {
  2913. .flags = FL_BASE1,
  2914. .num_ports = 2,
  2915. .base_baud = 1250000,
  2916. .uart_offset = 8,
  2917. },
  2918. [pbn_b1_bt_1_115200] = {
  2919. .flags = FL_BASE1|FL_BASE_BARS,
  2920. .num_ports = 1,
  2921. .base_baud = 115200,
  2922. .uart_offset = 8,
  2923. },
  2924. [pbn_b1_bt_2_115200] = {
  2925. .flags = FL_BASE1|FL_BASE_BARS,
  2926. .num_ports = 2,
  2927. .base_baud = 115200,
  2928. .uart_offset = 8,
  2929. },
  2930. [pbn_b1_bt_4_115200] = {
  2931. .flags = FL_BASE1|FL_BASE_BARS,
  2932. .num_ports = 4,
  2933. .base_baud = 115200,
  2934. .uart_offset = 8,
  2935. },
  2936. [pbn_b1_bt_2_921600] = {
  2937. .flags = FL_BASE1|FL_BASE_BARS,
  2938. .num_ports = 2,
  2939. .base_baud = 921600,
  2940. .uart_offset = 8,
  2941. },
  2942. [pbn_b1_1_1382400] = {
  2943. .flags = FL_BASE1,
  2944. .num_ports = 1,
  2945. .base_baud = 1382400,
  2946. .uart_offset = 8,
  2947. },
  2948. [pbn_b1_2_1382400] = {
  2949. .flags = FL_BASE1,
  2950. .num_ports = 2,
  2951. .base_baud = 1382400,
  2952. .uart_offset = 8,
  2953. },
  2954. [pbn_b1_4_1382400] = {
  2955. .flags = FL_BASE1,
  2956. .num_ports = 4,
  2957. .base_baud = 1382400,
  2958. .uart_offset = 8,
  2959. },
  2960. [pbn_b1_8_1382400] = {
  2961. .flags = FL_BASE1,
  2962. .num_ports = 8,
  2963. .base_baud = 1382400,
  2964. .uart_offset = 8,
  2965. },
  2966. [pbn_b2_1_115200] = {
  2967. .flags = FL_BASE2,
  2968. .num_ports = 1,
  2969. .base_baud = 115200,
  2970. .uart_offset = 8,
  2971. },
  2972. [pbn_b2_2_115200] = {
  2973. .flags = FL_BASE2,
  2974. .num_ports = 2,
  2975. .base_baud = 115200,
  2976. .uart_offset = 8,
  2977. },
  2978. [pbn_b2_4_115200] = {
  2979. .flags = FL_BASE2,
  2980. .num_ports = 4,
  2981. .base_baud = 115200,
  2982. .uart_offset = 8,
  2983. },
  2984. [pbn_b2_8_115200] = {
  2985. .flags = FL_BASE2,
  2986. .num_ports = 8,
  2987. .base_baud = 115200,
  2988. .uart_offset = 8,
  2989. },
  2990. [pbn_b2_1_460800] = {
  2991. .flags = FL_BASE2,
  2992. .num_ports = 1,
  2993. .base_baud = 460800,
  2994. .uart_offset = 8,
  2995. },
  2996. [pbn_b2_4_460800] = {
  2997. .flags = FL_BASE2,
  2998. .num_ports = 4,
  2999. .base_baud = 460800,
  3000. .uart_offset = 8,
  3001. },
  3002. [pbn_b2_8_460800] = {
  3003. .flags = FL_BASE2,
  3004. .num_ports = 8,
  3005. .base_baud = 460800,
  3006. .uart_offset = 8,
  3007. },
  3008. [pbn_b2_16_460800] = {
  3009. .flags = FL_BASE2,
  3010. .num_ports = 16,
  3011. .base_baud = 460800,
  3012. .uart_offset = 8,
  3013. },
  3014. [pbn_b2_1_921600] = {
  3015. .flags = FL_BASE2,
  3016. .num_ports = 1,
  3017. .base_baud = 921600,
  3018. .uart_offset = 8,
  3019. },
  3020. [pbn_b2_4_921600] = {
  3021. .flags = FL_BASE2,
  3022. .num_ports = 4,
  3023. .base_baud = 921600,
  3024. .uart_offset = 8,
  3025. },
  3026. [pbn_b2_8_921600] = {
  3027. .flags = FL_BASE2,
  3028. .num_ports = 8,
  3029. .base_baud = 921600,
  3030. .uart_offset = 8,
  3031. },
  3032. [pbn_b2_8_1152000] = {
  3033. .flags = FL_BASE2,
  3034. .num_ports = 8,
  3035. .base_baud = 1152000,
  3036. .uart_offset = 8,
  3037. },
  3038. [pbn_b2_bt_1_115200] = {
  3039. .flags = FL_BASE2|FL_BASE_BARS,
  3040. .num_ports = 1,
  3041. .base_baud = 115200,
  3042. .uart_offset = 8,
  3043. },
  3044. [pbn_b2_bt_2_115200] = {
  3045. .flags = FL_BASE2|FL_BASE_BARS,
  3046. .num_ports = 2,
  3047. .base_baud = 115200,
  3048. .uart_offset = 8,
  3049. },
  3050. [pbn_b2_bt_4_115200] = {
  3051. .flags = FL_BASE2|FL_BASE_BARS,
  3052. .num_ports = 4,
  3053. .base_baud = 115200,
  3054. .uart_offset = 8,
  3055. },
  3056. [pbn_b2_bt_2_921600] = {
  3057. .flags = FL_BASE2|FL_BASE_BARS,
  3058. .num_ports = 2,
  3059. .base_baud = 921600,
  3060. .uart_offset = 8,
  3061. },
  3062. [pbn_b2_bt_4_921600] = {
  3063. .flags = FL_BASE2|FL_BASE_BARS,
  3064. .num_ports = 4,
  3065. .base_baud = 921600,
  3066. .uart_offset = 8,
  3067. },
  3068. [pbn_b3_2_115200] = {
  3069. .flags = FL_BASE3,
  3070. .num_ports = 2,
  3071. .base_baud = 115200,
  3072. .uart_offset = 8,
  3073. },
  3074. [pbn_b3_4_115200] = {
  3075. .flags = FL_BASE3,
  3076. .num_ports = 4,
  3077. .base_baud = 115200,
  3078. .uart_offset = 8,
  3079. },
  3080. [pbn_b3_8_115200] = {
  3081. .flags = FL_BASE3,
  3082. .num_ports = 8,
  3083. .base_baud = 115200,
  3084. .uart_offset = 8,
  3085. },
  3086. [pbn_b4_bt_2_921600] = {
  3087. .flags = FL_BASE4,
  3088. .num_ports = 2,
  3089. .base_baud = 921600,
  3090. .uart_offset = 8,
  3091. },
  3092. [pbn_b4_bt_4_921600] = {
  3093. .flags = FL_BASE4,
  3094. .num_ports = 4,
  3095. .base_baud = 921600,
  3096. .uart_offset = 8,
  3097. },
  3098. [pbn_b4_bt_8_921600] = {
  3099. .flags = FL_BASE4,
  3100. .num_ports = 8,
  3101. .base_baud = 921600,
  3102. .uart_offset = 8,
  3103. },
  3104. /*
  3105. * Entries following this are board-specific.
  3106. */
  3107. /*
  3108. * Panacom - IOMEM
  3109. */
  3110. [pbn_panacom] = {
  3111. .flags = FL_BASE2,
  3112. .num_ports = 2,
  3113. .base_baud = 921600,
  3114. .uart_offset = 0x400,
  3115. .reg_shift = 7,
  3116. },
  3117. [pbn_panacom2] = {
  3118. .flags = FL_BASE2|FL_BASE_BARS,
  3119. .num_ports = 2,
  3120. .base_baud = 921600,
  3121. .uart_offset = 0x400,
  3122. .reg_shift = 7,
  3123. },
  3124. [pbn_panacom4] = {
  3125. .flags = FL_BASE2|FL_BASE_BARS,
  3126. .num_ports = 4,
  3127. .base_baud = 921600,
  3128. .uart_offset = 0x400,
  3129. .reg_shift = 7,
  3130. },
  3131. /* I think this entry is broken - the first_offset looks wrong --rmk */
  3132. [pbn_plx_romulus] = {
  3133. .flags = FL_BASE2,
  3134. .num_ports = 4,
  3135. .base_baud = 921600,
  3136. .uart_offset = 8 << 2,
  3137. .reg_shift = 2,
  3138. .first_offset = 0x03,
  3139. },
  3140. /*
  3141. * EndRun Technologies
  3142. * Uses the size of PCI Base region 0 to
  3143. * signal now many ports are available
  3144. * 2 port 952 Uart support
  3145. */
  3146. [pbn_endrun_2_4000000] = {
  3147. .flags = FL_BASE0,
  3148. .num_ports = 2,
  3149. .base_baud = 4000000,
  3150. .uart_offset = 0x200,
  3151. .first_offset = 0x1000,
  3152. },
  3153. /*
  3154. * This board uses the size of PCI Base region 0 to
  3155. * signal now many ports are available
  3156. */
  3157. [pbn_oxsemi] = {
  3158. .flags = FL_BASE0|FL_REGION_SZ_CAP,
  3159. .num_ports = 32,
  3160. .base_baud = 115200,
  3161. .uart_offset = 8,
  3162. },
  3163. [pbn_oxsemi_1_4000000] = {
  3164. .flags = FL_BASE0,
  3165. .num_ports = 1,
  3166. .base_baud = 4000000,
  3167. .uart_offset = 0x200,
  3168. .first_offset = 0x1000,
  3169. },
  3170. [pbn_oxsemi_2_4000000] = {
  3171. .flags = FL_BASE0,
  3172. .num_ports = 2,
  3173. .base_baud = 4000000,
  3174. .uart_offset = 0x200,
  3175. .first_offset = 0x1000,
  3176. },
  3177. [pbn_oxsemi_4_4000000] = {
  3178. .flags = FL_BASE0,
  3179. .num_ports = 4,
  3180. .base_baud = 4000000,
  3181. .uart_offset = 0x200,
  3182. .first_offset = 0x1000,
  3183. },
  3184. [pbn_oxsemi_8_4000000] = {
  3185. .flags = FL_BASE0,
  3186. .num_ports = 8,
  3187. .base_baud = 4000000,
  3188. .uart_offset = 0x200,
  3189. .first_offset = 0x1000,
  3190. },
  3191. /*
  3192. * EKF addition for i960 Boards form EKF with serial port.
  3193. * Max 256 ports.
  3194. */
  3195. [pbn_intel_i960] = {
  3196. .flags = FL_BASE0,
  3197. .num_ports = 32,
  3198. .base_baud = 921600,
  3199. .uart_offset = 8 << 2,
  3200. .reg_shift = 2,
  3201. .first_offset = 0x10000,
  3202. },
  3203. [pbn_sgi_ioc3] = {
  3204. .flags = FL_BASE0|FL_NOIRQ,
  3205. .num_ports = 1,
  3206. .base_baud = 458333,
  3207. .uart_offset = 8,
  3208. .reg_shift = 0,
  3209. .first_offset = 0x20178,
  3210. },
  3211. /*
  3212. * Computone - uses IOMEM.
  3213. */
  3214. [pbn_computone_4] = {
  3215. .flags = FL_BASE0,
  3216. .num_ports = 4,
  3217. .base_baud = 921600,
  3218. .uart_offset = 0x40,
  3219. .reg_shift = 2,
  3220. .first_offset = 0x200,
  3221. },
  3222. [pbn_computone_6] = {
  3223. .flags = FL_BASE0,
  3224. .num_ports = 6,
  3225. .base_baud = 921600,
  3226. .uart_offset = 0x40,
  3227. .reg_shift = 2,
  3228. .first_offset = 0x200,
  3229. },
  3230. [pbn_computone_8] = {
  3231. .flags = FL_BASE0,
  3232. .num_ports = 8,
  3233. .base_baud = 921600,
  3234. .uart_offset = 0x40,
  3235. .reg_shift = 2,
  3236. .first_offset = 0x200,
  3237. },
  3238. [pbn_sbsxrsio] = {
  3239. .flags = FL_BASE0,
  3240. .num_ports = 8,
  3241. .base_baud = 460800,
  3242. .uart_offset = 256,
  3243. .reg_shift = 4,
  3244. },
  3245. /*
  3246. * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
  3247. * Only basic 16550A support.
  3248. * XR17C15[24] are not tested, but they should work.
  3249. */
  3250. [pbn_exar_XR17C152] = {
  3251. .flags = FL_BASE0,
  3252. .num_ports = 2,
  3253. .base_baud = 921600,
  3254. .uart_offset = 0x200,
  3255. },
  3256. [pbn_exar_XR17C154] = {
  3257. .flags = FL_BASE0,
  3258. .num_ports = 4,
  3259. .base_baud = 921600,
  3260. .uart_offset = 0x200,
  3261. },
  3262. [pbn_exar_XR17C158] = {
  3263. .flags = FL_BASE0,
  3264. .num_ports = 8,
  3265. .base_baud = 921600,
  3266. .uart_offset = 0x200,
  3267. },
  3268. [pbn_exar_XR17V352] = {
  3269. .flags = FL_BASE0,
  3270. .num_ports = 2,
  3271. .base_baud = 7812500,
  3272. .uart_offset = 0x400,
  3273. .reg_shift = 0,
  3274. .first_offset = 0,
  3275. },
  3276. [pbn_exar_XR17V354] = {
  3277. .flags = FL_BASE0,
  3278. .num_ports = 4,
  3279. .base_baud = 7812500,
  3280. .uart_offset = 0x400,
  3281. .reg_shift = 0,
  3282. .first_offset = 0,
  3283. },
  3284. [pbn_exar_XR17V358] = {
  3285. .flags = FL_BASE0,
  3286. .num_ports = 8,
  3287. .base_baud = 7812500,
  3288. .uart_offset = 0x400,
  3289. .reg_shift = 0,
  3290. .first_offset = 0,
  3291. },
  3292. [pbn_exar_XR17V4358] = {
  3293. .flags = FL_BASE0,
  3294. .num_ports = 12,
  3295. .base_baud = 7812500,
  3296. .uart_offset = 0x400,
  3297. .reg_shift = 0,
  3298. .first_offset = 0,
  3299. },
  3300. [pbn_exar_XR17V8358] = {
  3301. .flags = FL_BASE0,
  3302. .num_ports = 16,
  3303. .base_baud = 7812500,
  3304. .uart_offset = 0x400,
  3305. .reg_shift = 0,
  3306. .first_offset = 0,
  3307. },
  3308. [pbn_exar_ibm_saturn] = {
  3309. .flags = FL_BASE0,
  3310. .num_ports = 1,
  3311. .base_baud = 921600,
  3312. .uart_offset = 0x200,
  3313. },
  3314. /*
  3315. * PA Semi PWRficient PA6T-1682M on-chip UART
  3316. */
  3317. [pbn_pasemi_1682M] = {
  3318. .flags = FL_BASE0,
  3319. .num_ports = 1,
  3320. .base_baud = 8333333,
  3321. },
  3322. /*
  3323. * National Instruments 843x
  3324. */
  3325. [pbn_ni8430_16] = {
  3326. .flags = FL_BASE0,
  3327. .num_ports = 16,
  3328. .base_baud = 3686400,
  3329. .uart_offset = 0x10,
  3330. .first_offset = 0x800,
  3331. },
  3332. [pbn_ni8430_8] = {
  3333. .flags = FL_BASE0,
  3334. .num_ports = 8,
  3335. .base_baud = 3686400,
  3336. .uart_offset = 0x10,
  3337. .first_offset = 0x800,
  3338. },
  3339. [pbn_ni8430_4] = {
  3340. .flags = FL_BASE0,
  3341. .num_ports = 4,
  3342. .base_baud = 3686400,
  3343. .uart_offset = 0x10,
  3344. .first_offset = 0x800,
  3345. },
  3346. [pbn_ni8430_2] = {
  3347. .flags = FL_BASE0,
  3348. .num_ports = 2,
  3349. .base_baud = 3686400,
  3350. .uart_offset = 0x10,
  3351. .first_offset = 0x800,
  3352. },
  3353. /*
  3354. * ADDI-DATA GmbH PCI-Express communication cards <[email protected]>
  3355. */
  3356. [pbn_ADDIDATA_PCIe_1_3906250] = {
  3357. .flags = FL_BASE0,
  3358. .num_ports = 1,
  3359. .base_baud = 3906250,
  3360. .uart_offset = 0x200,
  3361. .first_offset = 0x1000,
  3362. },
  3363. [pbn_ADDIDATA_PCIe_2_3906250] = {
  3364. .flags = FL_BASE0,
  3365. .num_ports = 2,
  3366. .base_baud = 3906250,
  3367. .uart_offset = 0x200,
  3368. .first_offset = 0x1000,
  3369. },
  3370. [pbn_ADDIDATA_PCIe_4_3906250] = {
  3371. .flags = FL_BASE0,
  3372. .num_ports = 4,
  3373. .base_baud = 3906250,
  3374. .uart_offset = 0x200,
  3375. .first_offset = 0x1000,
  3376. },
  3377. [pbn_ADDIDATA_PCIe_8_3906250] = {
  3378. .flags = FL_BASE0,
  3379. .num_ports = 8,
  3380. .base_baud = 3906250,
  3381. .uart_offset = 0x200,
  3382. .first_offset = 0x1000,
  3383. },
  3384. [pbn_ce4100_1_115200] = {
  3385. .flags = FL_BASE_BARS,
  3386. .num_ports = 2,
  3387. .base_baud = 921600,
  3388. .reg_shift = 2,
  3389. },
  3390. [pbn_omegapci] = {
  3391. .flags = FL_BASE0,
  3392. .num_ports = 8,
  3393. .base_baud = 115200,
  3394. .uart_offset = 0x200,
  3395. },
  3396. [pbn_NETMOS9900_2s_115200] = {
  3397. .flags = FL_BASE0,
  3398. .num_ports = 2,
  3399. .base_baud = 115200,
  3400. },
  3401. [pbn_brcm_trumanage] = {
  3402. .flags = FL_BASE0,
  3403. .num_ports = 1,
  3404. .reg_shift = 2,
  3405. .base_baud = 115200,
  3406. },
  3407. [pbn_fintek_4] = {
  3408. .num_ports = 4,
  3409. .uart_offset = 8,
  3410. .base_baud = 115200,
  3411. .first_offset = 0x40,
  3412. },
  3413. [pbn_fintek_8] = {
  3414. .num_ports = 8,
  3415. .uart_offset = 8,
  3416. .base_baud = 115200,
  3417. .first_offset = 0x40,
  3418. },
  3419. [pbn_fintek_12] = {
  3420. .num_ports = 12,
  3421. .uart_offset = 8,
  3422. .base_baud = 115200,
  3423. .first_offset = 0x40,
  3424. },
  3425. [pbn_wch382_2] = {
  3426. .flags = FL_BASE0,
  3427. .num_ports = 2,
  3428. .base_baud = 115200,
  3429. .uart_offset = 8,
  3430. .first_offset = 0xC0,
  3431. },
  3432. [pbn_wch384_4] = {
  3433. .flags = FL_BASE0,
  3434. .num_ports = 4,
  3435. .base_baud = 115200,
  3436. .uart_offset = 8,
  3437. .first_offset = 0xC0,
  3438. },
  3439. /*
  3440. * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
  3441. */
  3442. [pbn_pericom_PI7C9X7951] = {
  3443. .flags = FL_BASE0,
  3444. .num_ports = 1,
  3445. .base_baud = 921600,
  3446. .uart_offset = 0x8,
  3447. },
  3448. [pbn_pericom_PI7C9X7952] = {
  3449. .flags = FL_BASE0,
  3450. .num_ports = 2,
  3451. .base_baud = 921600,
  3452. .uart_offset = 0x8,
  3453. },
  3454. [pbn_pericom_PI7C9X7954] = {
  3455. .flags = FL_BASE0,
  3456. .num_ports = 4,
  3457. .base_baud = 921600,
  3458. .uart_offset = 0x8,
  3459. },
  3460. [pbn_pericom_PI7C9X7958] = {
  3461. .flags = FL_BASE0,
  3462. .num_ports = 8,
  3463. .base_baud = 921600,
  3464. .uart_offset = 0x8,
  3465. },
  3466. };
  3467. static const struct pci_device_id blacklist[] = {
  3468. /* softmodems */
  3469. { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
  3470. { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
  3471. { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
  3472. /* multi-io cards handled by parport_serial */
  3473. { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
  3474. { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
  3475. { PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */
  3476. { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
  3477. { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
  3478. /* Moxa Smartio MUE boards handled by 8250_moxa */
  3479. { PCI_VDEVICE(MOXA, 0x1024), },
  3480. { PCI_VDEVICE(MOXA, 0x1025), },
  3481. { PCI_VDEVICE(MOXA, 0x1045), },
  3482. { PCI_VDEVICE(MOXA, 0x1144), },
  3483. { PCI_VDEVICE(MOXA, 0x1160), },
  3484. { PCI_VDEVICE(MOXA, 0x1161), },
  3485. { PCI_VDEVICE(MOXA, 0x1182), },
  3486. { PCI_VDEVICE(MOXA, 0x1183), },
  3487. { PCI_VDEVICE(MOXA, 0x1322), },
  3488. { PCI_VDEVICE(MOXA, 0x1342), },
  3489. { PCI_VDEVICE(MOXA, 0x1381), },
  3490. { PCI_VDEVICE(MOXA, 0x1683), },
  3491. /* Intel platforms with MID UART */
  3492. { PCI_VDEVICE(INTEL, 0x081b), },
  3493. { PCI_VDEVICE(INTEL, 0x081c), },
  3494. { PCI_VDEVICE(INTEL, 0x081d), },
  3495. { PCI_VDEVICE(INTEL, 0x1191), },
  3496. { PCI_VDEVICE(INTEL, 0x19d8), },
  3497. /* Intel platforms with DesignWare UART */
  3498. { PCI_VDEVICE(INTEL, 0x0936), },
  3499. { PCI_VDEVICE(INTEL, 0x0f0a), },
  3500. { PCI_VDEVICE(INTEL, 0x0f0c), },
  3501. { PCI_VDEVICE(INTEL, 0x228a), },
  3502. { PCI_VDEVICE(INTEL, 0x228c), },
  3503. { PCI_VDEVICE(INTEL, 0x9ce3), },
  3504. { PCI_VDEVICE(INTEL, 0x9ce4), },
  3505. };
  3506. /*
  3507. * Given a complete unknown PCI device, try to use some heuristics to
  3508. * guess what the configuration might be, based on the pitiful PCI
  3509. * serial specs. Returns 0 on success, 1 on failure.
  3510. */
  3511. static int
  3512. serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
  3513. {
  3514. const struct pci_device_id *bldev;
  3515. int num_iomem, num_port, first_port = -1, i;
  3516. /*
  3517. * If it is not a communications device or the programming
  3518. * interface is greater than 6, give up.
  3519. *
  3520. * (Should we try to make guesses for multiport serial devices
  3521. * later?)
  3522. */
  3523. if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
  3524. ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
  3525. (dev->class & 0xff) > 6)
  3526. return -ENODEV;
  3527. /*
  3528. * Do not access blacklisted devices that are known not to
  3529. * feature serial ports or are handled by other modules.
  3530. */
  3531. for (bldev = blacklist;
  3532. bldev < blacklist + ARRAY_SIZE(blacklist);
  3533. bldev++) {
  3534. if (dev->vendor == bldev->vendor &&
  3535. dev->device == bldev->device)
  3536. return -ENODEV;
  3537. }
  3538. num_iomem = num_port = 0;
  3539. for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
  3540. if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
  3541. num_port++;
  3542. if (first_port == -1)
  3543. first_port = i;
  3544. }
  3545. if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
  3546. num_iomem++;
  3547. }
  3548. /*
  3549. * If there is 1 or 0 iomem regions, and exactly one port,
  3550. * use it. We guess the number of ports based on the IO
  3551. * region size.
  3552. */
  3553. if (num_iomem <= 1 && num_port == 1) {
  3554. board->flags = first_port;
  3555. board->num_ports = pci_resource_len(dev, first_port) / 8;
  3556. return 0;
  3557. }
  3558. /*
  3559. * Now guess if we've got a board which indexes by BARs.
  3560. * Each IO BAR should be 8 bytes, and they should follow
  3561. * consecutively.
  3562. */
  3563. first_port = -1;
  3564. num_port = 0;
  3565. for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
  3566. if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
  3567. pci_resource_len(dev, i) == 8 &&
  3568. (first_port == -1 || (first_port + num_port) == i)) {
  3569. num_port++;
  3570. if (first_port == -1)
  3571. first_port = i;
  3572. }
  3573. }
  3574. if (num_port > 1) {
  3575. board->flags = first_port | FL_BASE_BARS;
  3576. board->num_ports = num_port;
  3577. return 0;
  3578. }
  3579. return -ENODEV;
  3580. }
  3581. static inline int
  3582. serial_pci_matches(const struct pciserial_board *board,
  3583. const struct pciserial_board *guessed)
  3584. {
  3585. return
  3586. board->num_ports == guessed->num_ports &&
  3587. board->base_baud == guessed->base_baud &&
  3588. board->uart_offset == guessed->uart_offset &&
  3589. board->reg_shift == guessed->reg_shift &&
  3590. board->first_offset == guessed->first_offset;
  3591. }
  3592. struct serial_private *
  3593. pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
  3594. {
  3595. struct uart_8250_port uart;
  3596. struct serial_private *priv;
  3597. struct pci_serial_quirk *quirk;
  3598. int rc, nr_ports, i;
  3599. nr_ports = board->num_ports;
  3600. /*
  3601. * Find an init and setup quirks.
  3602. */
  3603. quirk = find_quirk(dev);
  3604. /*
  3605. * Run the new-style initialization function.
  3606. * The initialization function returns:
  3607. * <0 - error
  3608. * 0 - use board->num_ports
  3609. * >0 - number of ports
  3610. */
  3611. if (quirk->init) {
  3612. rc = quirk->init(dev);
  3613. if (rc < 0) {
  3614. priv = ERR_PTR(rc);
  3615. goto err_out;
  3616. }
  3617. if (rc)
  3618. nr_ports = rc;
  3619. }
  3620. priv = kzalloc(sizeof(struct serial_private) +
  3621. sizeof(unsigned int) * nr_ports,
  3622. GFP_KERNEL);
  3623. if (!priv) {
  3624. priv = ERR_PTR(-ENOMEM);
  3625. goto err_deinit;
  3626. }
  3627. priv->dev = dev;
  3628. priv->quirk = quirk;
  3629. memset(&uart, 0, sizeof(uart));
  3630. uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
  3631. uart.port.uartclk = board->base_baud * 16;
  3632. uart.port.irq = get_pci_irq(dev, board);
  3633. uart.port.dev = &dev->dev;
  3634. for (i = 0; i < nr_ports; i++) {
  3635. if (quirk->setup(priv, board, &uart, i))
  3636. break;
  3637. dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
  3638. uart.port.iobase, uart.port.irq, uart.port.iotype);
  3639. priv->line[i] = serial8250_register_8250_port(&uart);
  3640. if (priv->line[i] < 0) {
  3641. dev_err(&dev->dev,
  3642. "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
  3643. uart.port.iobase, uart.port.irq,
  3644. uart.port.iotype, priv->line[i]);
  3645. break;
  3646. }
  3647. }
  3648. priv->nr = i;
  3649. priv->board = board;
  3650. return priv;
  3651. err_deinit:
  3652. if (quirk->exit)
  3653. quirk->exit(dev);
  3654. err_out:
  3655. return priv;
  3656. }
  3657. EXPORT_SYMBOL_GPL(pciserial_init_ports);
  3658. void pciserial_detach_ports(struct serial_private *priv)
  3659. {
  3660. struct pci_serial_quirk *quirk;
  3661. int i;
  3662. for (i = 0; i < priv->nr; i++)
  3663. serial8250_unregister_port(priv->line[i]);
  3664. /*
  3665. * Find the exit quirks.
  3666. */
  3667. quirk = find_quirk(priv->dev);
  3668. if (quirk->exit)
  3669. quirk->exit(priv->dev);
  3670. }
  3671. void pciserial_remove_ports(struct serial_private *priv)
  3672. {
  3673. pciserial_detach_ports(priv);
  3674. kfree(priv);
  3675. }
  3676. EXPORT_SYMBOL_GPL(pciserial_remove_ports);
  3677. void pciserial_suspend_ports(struct serial_private *priv)
  3678. {
  3679. int i;
  3680. for (i = 0; i < priv->nr; i++)
  3681. if (priv->line[i] >= 0)
  3682. serial8250_suspend_port(priv->line[i]);
  3683. /*
  3684. * Ensure that every init quirk is properly torn down
  3685. */
  3686. if (priv->quirk->exit)
  3687. priv->quirk->exit(priv->dev);
  3688. }
  3689. EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
  3690. void pciserial_resume_ports(struct serial_private *priv)
  3691. {
  3692. int i;
  3693. /*
  3694. * Ensure that the board is correctly configured.
  3695. */
  3696. if (priv->quirk->init)
  3697. priv->quirk->init(priv->dev);
  3698. for (i = 0; i < priv->nr; i++)
  3699. if (priv->line[i] >= 0)
  3700. serial8250_resume_port(priv->line[i]);
  3701. }
  3702. EXPORT_SYMBOL_GPL(pciserial_resume_ports);
  3703. /*
  3704. * Probe one serial board. Unfortunately, there is no rhyme nor reason
  3705. * to the arrangement of serial ports on a PCI card.
  3706. */
  3707. static int
  3708. pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
  3709. {
  3710. struct pci_serial_quirk *quirk;
  3711. struct serial_private *priv;
  3712. const struct pciserial_board *board;
  3713. struct pciserial_board tmp;
  3714. int rc;
  3715. quirk = find_quirk(dev);
  3716. if (quirk->probe) {
  3717. rc = quirk->probe(dev);
  3718. if (rc)
  3719. return rc;
  3720. }
  3721. if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
  3722. dev_err(&dev->dev, "invalid driver_data: %ld\n",
  3723. ent->driver_data);
  3724. return -EINVAL;
  3725. }
  3726. board = &pci_boards[ent->driver_data];
  3727. rc = pcim_enable_device(dev);
  3728. pci_save_state(dev);
  3729. if (rc)
  3730. return rc;
  3731. if (ent->driver_data == pbn_default) {
  3732. /*
  3733. * Use a copy of the pci_board entry for this;
  3734. * avoid changing entries in the table.
  3735. */
  3736. memcpy(&tmp, board, sizeof(struct pciserial_board));
  3737. board = &tmp;
  3738. /*
  3739. * We matched one of our class entries. Try to
  3740. * determine the parameters of this board.
  3741. */
  3742. rc = serial_pci_guess_board(dev, &tmp);
  3743. if (rc)
  3744. return rc;
  3745. } else {
  3746. /*
  3747. * We matched an explicit entry. If we are able to
  3748. * detect this boards settings with our heuristic,
  3749. * then we no longer need this entry.
  3750. */
  3751. memcpy(&tmp, &pci_boards[pbn_default],
  3752. sizeof(struct pciserial_board));
  3753. rc = serial_pci_guess_board(dev, &tmp);
  3754. if (rc == 0 && serial_pci_matches(board, &tmp))
  3755. moan_device("Redundant entry in serial pci_table.",
  3756. dev);
  3757. }
  3758. priv = pciserial_init_ports(dev, board);
  3759. if (IS_ERR(priv))
  3760. return PTR_ERR(priv);
  3761. pci_set_drvdata(dev, priv);
  3762. return 0;
  3763. }
  3764. static void pciserial_remove_one(struct pci_dev *dev)
  3765. {
  3766. struct serial_private *priv = pci_get_drvdata(dev);
  3767. pciserial_remove_ports(priv);
  3768. }
  3769. #ifdef CONFIG_PM_SLEEP
  3770. static int pciserial_suspend_one(struct device *dev)
  3771. {
  3772. struct pci_dev *pdev = to_pci_dev(dev);
  3773. struct serial_private *priv = pci_get_drvdata(pdev);
  3774. if (priv)
  3775. pciserial_suspend_ports(priv);
  3776. return 0;
  3777. }
  3778. static int pciserial_resume_one(struct device *dev)
  3779. {
  3780. struct pci_dev *pdev = to_pci_dev(dev);
  3781. struct serial_private *priv = pci_get_drvdata(pdev);
  3782. int err;
  3783. if (priv) {
  3784. /*
  3785. * The device may have been disabled. Re-enable it.
  3786. */
  3787. err = pci_enable_device(pdev);
  3788. /* FIXME: We cannot simply error out here */
  3789. if (err)
  3790. dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
  3791. pciserial_resume_ports(priv);
  3792. }
  3793. return 0;
  3794. }
  3795. #endif
  3796. static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
  3797. pciserial_resume_one);
  3798. static struct pci_device_id serial_pci_tbl[] = {
  3799. /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
  3800. { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
  3801. PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
  3802. pbn_b2_8_921600 },
  3803. /* Advantech also use 0x3618 and 0xf618 */
  3804. { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
  3805. PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
  3806. pbn_b0_4_921600 },
  3807. { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
  3808. PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
  3809. pbn_b0_4_921600 },
  3810. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
  3811. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3812. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
  3813. pbn_b1_8_1382400 },
  3814. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
  3815. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3816. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
  3817. pbn_b1_4_1382400 },
  3818. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
  3819. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3820. PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
  3821. pbn_b1_2_1382400 },
  3822. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3823. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3824. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
  3825. pbn_b1_8_1382400 },
  3826. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3827. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3828. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
  3829. pbn_b1_4_1382400 },
  3830. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3831. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3832. PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
  3833. pbn_b1_2_1382400 },
  3834. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3835. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3836. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
  3837. pbn_b1_8_921600 },
  3838. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3839. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3840. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
  3841. pbn_b1_8_921600 },
  3842. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3843. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3844. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
  3845. pbn_b1_4_921600 },
  3846. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3847. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3848. PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
  3849. pbn_b1_4_921600 },
  3850. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3851. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3852. PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
  3853. pbn_b1_2_921600 },
  3854. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3855. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3856. PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
  3857. pbn_b1_8_921600 },
  3858. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3859. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3860. PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
  3861. pbn_b1_8_921600 },
  3862. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3863. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3864. PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
  3865. pbn_b1_4_921600 },
  3866. { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
  3867. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3868. PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
  3869. pbn_b1_2_1250000 },
  3870. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  3871. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3872. PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
  3873. pbn_b0_2_1843200 },
  3874. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  3875. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3876. PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
  3877. pbn_b0_4_1843200 },
  3878. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  3879. PCI_VENDOR_ID_AFAVLAB,
  3880. PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
  3881. pbn_b0_4_1152000 },
  3882. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  3883. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3884. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
  3885. pbn_b0_2_1843200_200 },
  3886. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
  3887. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3888. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
  3889. pbn_b0_4_1843200_200 },
  3890. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
  3891. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3892. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
  3893. pbn_b0_8_1843200_200 },
  3894. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  3895. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3896. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
  3897. pbn_b0_2_1843200_200 },
  3898. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
  3899. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3900. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
  3901. pbn_b0_4_1843200_200 },
  3902. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
  3903. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3904. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
  3905. pbn_b0_8_1843200_200 },
  3906. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  3907. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3908. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
  3909. pbn_b0_2_1843200_200 },
  3910. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
  3911. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3912. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
  3913. pbn_b0_4_1843200_200 },
  3914. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
  3915. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3916. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
  3917. pbn_b0_8_1843200_200 },
  3918. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  3919. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3920. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
  3921. pbn_b0_2_1843200_200 },
  3922. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
  3923. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3924. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
  3925. pbn_b0_4_1843200_200 },
  3926. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
  3927. PCI_SUBVENDOR_ID_CONNECT_TECH,
  3928. PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
  3929. pbn_b0_8_1843200_200 },
  3930. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  3931. PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
  3932. 0, 0, pbn_exar_ibm_saturn },
  3933. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
  3934. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3935. pbn_b2_bt_1_115200 },
  3936. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
  3937. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3938. pbn_b2_bt_2_115200 },
  3939. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
  3940. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3941. pbn_b2_bt_4_115200 },
  3942. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
  3943. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3944. pbn_b2_bt_2_115200 },
  3945. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
  3946. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3947. pbn_b2_bt_4_115200 },
  3948. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
  3949. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3950. pbn_b2_8_115200 },
  3951. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
  3952. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3953. pbn_b2_8_460800 },
  3954. { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
  3955. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3956. pbn_b2_8_115200 },
  3957. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
  3958. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3959. pbn_b2_bt_2_115200 },
  3960. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
  3961. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3962. pbn_b2_bt_2_921600 },
  3963. /*
  3964. * VScom SPCOM800, from [email protected]
  3965. */
  3966. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
  3967. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3968. pbn_b2_8_921600 },
  3969. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
  3970. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3971. pbn_b2_4_921600 },
  3972. /* Unknown card - subdevice 0x1584 */
  3973. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  3974. PCI_VENDOR_ID_PLX,
  3975. PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
  3976. pbn_b2_4_115200 },
  3977. /* Unknown card - subdevice 0x1588 */
  3978. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  3979. PCI_VENDOR_ID_PLX,
  3980. PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
  3981. pbn_b2_8_115200 },
  3982. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  3983. PCI_SUBVENDOR_ID_KEYSPAN,
  3984. PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
  3985. pbn_panacom },
  3986. { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
  3987. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3988. pbn_panacom4 },
  3989. { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
  3990. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  3991. pbn_panacom2 },
  3992. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
  3993. PCI_VENDOR_ID_ESDGMBH,
  3994. PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
  3995. pbn_b2_4_115200 },
  3996. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  3997. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  3998. PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
  3999. pbn_b2_4_460800 },
  4000. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  4001. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  4002. PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
  4003. pbn_b2_8_460800 },
  4004. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  4005. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  4006. PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
  4007. pbn_b2_16_460800 },
  4008. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  4009. PCI_SUBVENDOR_ID_CHASE_PCIFAST,
  4010. PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
  4011. pbn_b2_16_460800 },
  4012. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  4013. PCI_SUBVENDOR_ID_CHASE_PCIRAS,
  4014. PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
  4015. pbn_b2_4_460800 },
  4016. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  4017. PCI_SUBVENDOR_ID_CHASE_PCIRAS,
  4018. PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
  4019. pbn_b2_8_460800 },
  4020. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
  4021. PCI_SUBVENDOR_ID_EXSYS,
  4022. PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
  4023. pbn_b2_4_115200 },
  4024. /*
  4025. * Megawolf Romulus PCI Serial Card, from Mike Hudson
  4026. * ([email protected])
  4027. */
  4028. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
  4029. 0x10b5, 0x106a, 0, 0,
  4030. pbn_plx_romulus },
  4031. /*
  4032. * EndRun Technologies. PCI express device range.
  4033. * EndRun PTP/1588 has 2 Native UARTs.
  4034. */
  4035. { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
  4036. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4037. pbn_endrun_2_4000000 },
  4038. /*
  4039. * Quatech cards. These actually have configurable clocks but for
  4040. * now we just use the default.
  4041. *
  4042. * 100 series are RS232, 200 series RS422,
  4043. */
  4044. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
  4045. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4046. pbn_b1_4_115200 },
  4047. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
  4048. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4049. pbn_b1_2_115200 },
  4050. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
  4051. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4052. pbn_b2_2_115200 },
  4053. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
  4054. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4055. pbn_b1_2_115200 },
  4056. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
  4057. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4058. pbn_b2_2_115200 },
  4059. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
  4060. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4061. pbn_b1_4_115200 },
  4062. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
  4063. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4064. pbn_b1_8_115200 },
  4065. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
  4066. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4067. pbn_b1_8_115200 },
  4068. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
  4069. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4070. pbn_b1_4_115200 },
  4071. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
  4072. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4073. pbn_b1_2_115200 },
  4074. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
  4075. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4076. pbn_b1_4_115200 },
  4077. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
  4078. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4079. pbn_b1_2_115200 },
  4080. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
  4081. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4082. pbn_b2_4_115200 },
  4083. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
  4084. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4085. pbn_b2_2_115200 },
  4086. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
  4087. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4088. pbn_b2_1_115200 },
  4089. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
  4090. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4091. pbn_b2_4_115200 },
  4092. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
  4093. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4094. pbn_b2_2_115200 },
  4095. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
  4096. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4097. pbn_b2_1_115200 },
  4098. { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
  4099. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4100. pbn_b0_8_115200 },
  4101. { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
  4102. PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
  4103. 0, 0,
  4104. pbn_b0_4_921600 },
  4105. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  4106. PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
  4107. 0, 0,
  4108. pbn_b0_4_1152000 },
  4109. { PCI_VENDOR_ID_OXSEMI, 0x9505,
  4110. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4111. pbn_b0_bt_2_921600 },
  4112. /*
  4113. * The below card is a little controversial since it is the
  4114. * subject of a PCI vendor/device ID clash. (See
  4115. * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
  4116. * For now just used the hex ID 0x950a.
  4117. */
  4118. { PCI_VENDOR_ID_OXSEMI, 0x950a,
  4119. PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
  4120. 0, 0, pbn_b0_2_115200 },
  4121. { PCI_VENDOR_ID_OXSEMI, 0x950a,
  4122. PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
  4123. 0, 0, pbn_b0_2_115200 },
  4124. { PCI_VENDOR_ID_OXSEMI, 0x950a,
  4125. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4126. pbn_b0_2_1130000 },
  4127. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
  4128. PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
  4129. pbn_b0_1_921600 },
  4130. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
  4131. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4132. pbn_b0_4_115200 },
  4133. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
  4134. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4135. pbn_b0_bt_2_921600 },
  4136. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
  4137. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4138. pbn_b2_8_1152000 },
  4139. /*
  4140. * Oxford Semiconductor Inc. Tornado PCI express device range.
  4141. */
  4142. { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
  4143. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4144. pbn_b0_1_4000000 },
  4145. { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
  4146. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4147. pbn_b0_1_4000000 },
  4148. { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
  4149. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4150. pbn_oxsemi_1_4000000 },
  4151. { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
  4152. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4153. pbn_oxsemi_1_4000000 },
  4154. { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
  4155. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4156. pbn_b0_1_4000000 },
  4157. { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
  4158. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4159. pbn_b0_1_4000000 },
  4160. { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
  4161. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4162. pbn_oxsemi_1_4000000 },
  4163. { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
  4164. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4165. pbn_oxsemi_1_4000000 },
  4166. { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
  4167. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4168. pbn_b0_1_4000000 },
  4169. { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
  4170. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4171. pbn_b0_1_4000000 },
  4172. { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
  4173. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4174. pbn_b0_1_4000000 },
  4175. { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
  4176. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4177. pbn_b0_1_4000000 },
  4178. { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
  4179. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4180. pbn_oxsemi_2_4000000 },
  4181. { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
  4182. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4183. pbn_oxsemi_2_4000000 },
  4184. { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
  4185. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4186. pbn_oxsemi_4_4000000 },
  4187. { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
  4188. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4189. pbn_oxsemi_4_4000000 },
  4190. { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
  4191. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4192. pbn_oxsemi_8_4000000 },
  4193. { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
  4194. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4195. pbn_oxsemi_8_4000000 },
  4196. { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
  4197. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4198. pbn_oxsemi_1_4000000 },
  4199. { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
  4200. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4201. pbn_oxsemi_1_4000000 },
  4202. { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
  4203. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4204. pbn_oxsemi_1_4000000 },
  4205. { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
  4206. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4207. pbn_oxsemi_1_4000000 },
  4208. { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
  4209. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4210. pbn_oxsemi_1_4000000 },
  4211. { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
  4212. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4213. pbn_oxsemi_1_4000000 },
  4214. { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
  4215. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4216. pbn_oxsemi_1_4000000 },
  4217. { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
  4218. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4219. pbn_oxsemi_1_4000000 },
  4220. { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
  4221. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4222. pbn_oxsemi_1_4000000 },
  4223. { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
  4224. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4225. pbn_oxsemi_1_4000000 },
  4226. { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
  4227. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4228. pbn_oxsemi_1_4000000 },
  4229. { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
  4230. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4231. pbn_oxsemi_1_4000000 },
  4232. { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
  4233. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4234. pbn_oxsemi_1_4000000 },
  4235. { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
  4236. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4237. pbn_oxsemi_1_4000000 },
  4238. { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
  4239. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4240. pbn_oxsemi_1_4000000 },
  4241. { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
  4242. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4243. pbn_oxsemi_1_4000000 },
  4244. { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
  4245. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4246. pbn_oxsemi_1_4000000 },
  4247. { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
  4248. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4249. pbn_oxsemi_1_4000000 },
  4250. { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
  4251. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4252. pbn_oxsemi_1_4000000 },
  4253. { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
  4254. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4255. pbn_oxsemi_1_4000000 },
  4256. { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
  4257. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4258. pbn_oxsemi_1_4000000 },
  4259. { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
  4260. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4261. pbn_oxsemi_1_4000000 },
  4262. { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
  4263. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4264. pbn_oxsemi_1_4000000 },
  4265. { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
  4266. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4267. pbn_oxsemi_1_4000000 },
  4268. { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
  4269. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4270. pbn_oxsemi_1_4000000 },
  4271. { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
  4272. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4273. pbn_oxsemi_1_4000000 },
  4274. /*
  4275. * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
  4276. */
  4277. { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
  4278. PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
  4279. pbn_oxsemi_1_4000000 },
  4280. { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
  4281. PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
  4282. pbn_oxsemi_2_4000000 },
  4283. { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
  4284. PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
  4285. pbn_oxsemi_4_4000000 },
  4286. { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
  4287. PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
  4288. pbn_oxsemi_8_4000000 },
  4289. /*
  4290. * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
  4291. */
  4292. { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
  4293. PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
  4294. pbn_oxsemi_2_4000000 },
  4295. /*
  4296. * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
  4297. * from [email protected]
  4298. */
  4299. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  4300. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
  4301. pbn_sbsxrsio },
  4302. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  4303. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
  4304. pbn_sbsxrsio },
  4305. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  4306. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
  4307. pbn_sbsxrsio },
  4308. { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
  4309. PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
  4310. pbn_sbsxrsio },
  4311. /*
  4312. * Digitan DS560-558, from [email protected]
  4313. */
  4314. { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
  4315. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4316. pbn_b1_1_115200 },
  4317. /*
  4318. * Titan Electronic cards
  4319. * The 400L and 800L have a custom setup quirk.
  4320. */
  4321. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
  4322. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4323. pbn_b0_1_921600 },
  4324. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
  4325. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4326. pbn_b0_2_921600 },
  4327. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
  4328. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4329. pbn_b0_4_921600 },
  4330. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
  4331. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4332. pbn_b0_4_921600 },
  4333. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
  4334. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4335. pbn_b1_1_921600 },
  4336. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
  4337. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4338. pbn_b1_bt_2_921600 },
  4339. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
  4340. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4341. pbn_b0_bt_4_921600 },
  4342. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
  4343. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4344. pbn_b0_bt_8_921600 },
  4345. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
  4346. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4347. pbn_b4_bt_2_921600 },
  4348. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
  4349. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4350. pbn_b4_bt_4_921600 },
  4351. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
  4352. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4353. pbn_b4_bt_8_921600 },
  4354. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
  4355. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4356. pbn_b0_4_921600 },
  4357. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
  4358. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4359. pbn_b0_4_921600 },
  4360. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
  4361. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4362. pbn_b0_4_921600 },
  4363. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
  4364. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4365. pbn_oxsemi_1_4000000 },
  4366. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
  4367. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4368. pbn_oxsemi_2_4000000 },
  4369. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
  4370. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4371. pbn_oxsemi_4_4000000 },
  4372. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
  4373. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4374. pbn_oxsemi_8_4000000 },
  4375. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
  4376. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4377. pbn_oxsemi_2_4000000 },
  4378. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
  4379. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4380. pbn_oxsemi_2_4000000 },
  4381. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
  4382. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4383. pbn_b0_bt_2_921600 },
  4384. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
  4385. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4386. pbn_b0_4_921600 },
  4387. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
  4388. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4389. pbn_b0_4_921600 },
  4390. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
  4391. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4392. pbn_b0_4_921600 },
  4393. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
  4394. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4395. pbn_b0_4_921600 },
  4396. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
  4397. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4398. pbn_b2_1_460800 },
  4399. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
  4400. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4401. pbn_b2_1_460800 },
  4402. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
  4403. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4404. pbn_b2_1_460800 },
  4405. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
  4406. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4407. pbn_b2_bt_2_921600 },
  4408. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
  4409. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4410. pbn_b2_bt_2_921600 },
  4411. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
  4412. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4413. pbn_b2_bt_2_921600 },
  4414. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
  4415. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4416. pbn_b2_bt_4_921600 },
  4417. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
  4418. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4419. pbn_b2_bt_4_921600 },
  4420. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
  4421. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4422. pbn_b2_bt_4_921600 },
  4423. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
  4424. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4425. pbn_b0_1_921600 },
  4426. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
  4427. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4428. pbn_b0_1_921600 },
  4429. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
  4430. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4431. pbn_b0_1_921600 },
  4432. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
  4433. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4434. pbn_b0_bt_2_921600 },
  4435. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
  4436. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4437. pbn_b0_bt_2_921600 },
  4438. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
  4439. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4440. pbn_b0_bt_2_921600 },
  4441. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
  4442. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4443. pbn_b0_bt_4_921600 },
  4444. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
  4445. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4446. pbn_b0_bt_4_921600 },
  4447. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
  4448. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4449. pbn_b0_bt_4_921600 },
  4450. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
  4451. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4452. pbn_b0_bt_8_921600 },
  4453. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
  4454. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4455. pbn_b0_bt_8_921600 },
  4456. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
  4457. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4458. pbn_b0_bt_8_921600 },
  4459. /*
  4460. * Computone devices submitted by Doug McNash [email protected]
  4461. */
  4462. { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
  4463. PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
  4464. 0, 0, pbn_computone_4 },
  4465. { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
  4466. PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
  4467. 0, 0, pbn_computone_8 },
  4468. { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
  4469. PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
  4470. 0, 0, pbn_computone_6 },
  4471. { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
  4472. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4473. pbn_oxsemi },
  4474. { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
  4475. PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
  4476. pbn_b0_bt_1_921600 },
  4477. /*
  4478. * SUNIX (TIMEDIA)
  4479. */
  4480. { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
  4481. PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
  4482. PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
  4483. pbn_b0_bt_1_921600 },
  4484. { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
  4485. PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
  4486. PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
  4487. pbn_b0_bt_1_921600 },
  4488. /*
  4489. * AFAVLAB serial card, from Harald Welte <[email protected]>
  4490. */
  4491. { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
  4492. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4493. pbn_b0_bt_8_115200 },
  4494. { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
  4495. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4496. pbn_b0_bt_8_115200 },
  4497. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
  4498. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4499. pbn_b0_bt_2_115200 },
  4500. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
  4501. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4502. pbn_b0_bt_2_115200 },
  4503. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
  4504. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4505. pbn_b0_bt_2_115200 },
  4506. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
  4507. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4508. pbn_b0_bt_2_115200 },
  4509. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
  4510. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4511. pbn_b0_bt_2_115200 },
  4512. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
  4513. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4514. pbn_b0_bt_4_460800 },
  4515. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
  4516. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4517. pbn_b0_bt_4_460800 },
  4518. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
  4519. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4520. pbn_b0_bt_2_460800 },
  4521. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
  4522. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4523. pbn_b0_bt_2_460800 },
  4524. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
  4525. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4526. pbn_b0_bt_2_460800 },
  4527. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
  4528. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4529. pbn_b0_bt_1_115200 },
  4530. { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
  4531. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4532. pbn_b0_bt_1_460800 },
  4533. /*
  4534. * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
  4535. * Cards are identified by their subsystem vendor IDs, which
  4536. * (in hex) match the model number.
  4537. *
  4538. * Note that JC140x are RS422/485 cards which require ox950
  4539. * ACR = 0x10, and as such are not currently fully supported.
  4540. */
  4541. { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
  4542. 0x1204, 0x0004, 0, 0,
  4543. pbn_b0_4_921600 },
  4544. { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
  4545. 0x1208, 0x0004, 0, 0,
  4546. pbn_b0_4_921600 },
  4547. /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
  4548. 0x1402, 0x0002, 0, 0,
  4549. pbn_b0_2_921600 }, */
  4550. /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
  4551. 0x1404, 0x0004, 0, 0,
  4552. pbn_b0_4_921600 }, */
  4553. { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
  4554. 0x1208, 0x0004, 0, 0,
  4555. pbn_b0_4_921600 },
  4556. { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
  4557. 0x1204, 0x0004, 0, 0,
  4558. pbn_b0_4_921600 },
  4559. { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
  4560. 0x1208, 0x0004, 0, 0,
  4561. pbn_b0_4_921600 },
  4562. { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
  4563. 0x1208, 0x0004, 0, 0,
  4564. pbn_b0_4_921600 },
  4565. /*
  4566. * Dell Remote Access Card 4 - [email protected]
  4567. */
  4568. { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
  4569. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4570. pbn_b1_1_1382400 },
  4571. /*
  4572. * Dell Remote Access Card III - [email protected]
  4573. */
  4574. { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
  4575. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4576. pbn_b1_1_1382400 },
  4577. /*
  4578. * RAStel 2 port modem, [email protected]
  4579. */
  4580. { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
  4581. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4582. pbn_b2_bt_2_115200 },
  4583. /*
  4584. * EKF addition for i960 Boards form EKF with serial port
  4585. */
  4586. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
  4587. 0xE4BF, PCI_ANY_ID, 0, 0,
  4588. pbn_intel_i960 },
  4589. /*
  4590. * Xircom Cardbus/Ethernet combos
  4591. */
  4592. { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
  4593. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4594. pbn_b0_1_115200 },
  4595. /*
  4596. * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
  4597. */
  4598. { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
  4599. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4600. pbn_b0_1_115200 },
  4601. /*
  4602. * Untested PCI modems, sent in from various folks...
  4603. */
  4604. /*
  4605. * Elsa Model 56K PCI Modem, from Andreas Rath <[email protected]>
  4606. */
  4607. { PCI_VENDOR_ID_ROCKWELL, 0x1004,
  4608. 0x1048, 0x1500, 0, 0,
  4609. pbn_b1_1_115200 },
  4610. { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
  4611. 0xFF00, 0, 0, 0,
  4612. pbn_sgi_ioc3 },
  4613. /*
  4614. * HP Diva card
  4615. */
  4616. { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
  4617. PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
  4618. pbn_b1_1_115200 },
  4619. { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
  4620. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4621. pbn_b0_5_115200 },
  4622. { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
  4623. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4624. pbn_b2_1_115200 },
  4625. { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
  4626. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4627. pbn_b3_2_115200 },
  4628. { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
  4629. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4630. pbn_b3_4_115200 },
  4631. { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
  4632. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4633. pbn_b3_8_115200 },
  4634. /*
  4635. * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
  4636. */
  4637. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
  4638. PCI_ANY_ID, PCI_ANY_ID,
  4639. 0,
  4640. 0, pbn_exar_XR17C152 },
  4641. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
  4642. PCI_ANY_ID, PCI_ANY_ID,
  4643. 0,
  4644. 0, pbn_exar_XR17C154 },
  4645. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
  4646. PCI_ANY_ID, PCI_ANY_ID,
  4647. 0,
  4648. 0, pbn_exar_XR17C158 },
  4649. /*
  4650. * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
  4651. */
  4652. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
  4653. PCI_ANY_ID, PCI_ANY_ID,
  4654. 0,
  4655. 0, pbn_exar_XR17V352 },
  4656. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
  4657. PCI_ANY_ID, PCI_ANY_ID,
  4658. 0,
  4659. 0, pbn_exar_XR17V354 },
  4660. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
  4661. PCI_ANY_ID, PCI_ANY_ID,
  4662. 0,
  4663. 0, pbn_exar_XR17V358 },
  4664. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
  4665. PCI_ANY_ID, PCI_ANY_ID,
  4666. 0,
  4667. 0, pbn_exar_XR17V4358 },
  4668. { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
  4669. PCI_ANY_ID, PCI_ANY_ID,
  4670. 0,
  4671. 0, pbn_exar_XR17V8358 },
  4672. /*
  4673. * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
  4674. */
  4675. { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
  4676. PCI_ANY_ID, PCI_ANY_ID,
  4677. 0,
  4678. 0, pbn_pericom_PI7C9X7951 },
  4679. { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
  4680. PCI_ANY_ID, PCI_ANY_ID,
  4681. 0,
  4682. 0, pbn_pericom_PI7C9X7952 },
  4683. { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
  4684. PCI_ANY_ID, PCI_ANY_ID,
  4685. 0,
  4686. 0, pbn_pericom_PI7C9X7954 },
  4687. { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
  4688. PCI_ANY_ID, PCI_ANY_ID,
  4689. 0,
  4690. 0, pbn_pericom_PI7C9X7958 },
  4691. /*
  4692. * ACCES I/O Products quad
  4693. */
  4694. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
  4695. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4696. pbn_pericom_PI7C9X7952 },
  4697. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
  4698. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4699. pbn_pericom_PI7C9X7952 },
  4700. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
  4701. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4702. pbn_pericom_PI7C9X7954 },
  4703. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
  4704. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4705. pbn_pericom_PI7C9X7954 },
  4706. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
  4707. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4708. pbn_pericom_PI7C9X7952 },
  4709. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
  4710. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4711. pbn_pericom_PI7C9X7952 },
  4712. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
  4713. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4714. pbn_pericom_PI7C9X7954 },
  4715. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
  4716. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4717. pbn_pericom_PI7C9X7954 },
  4718. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
  4719. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4720. pbn_pericom_PI7C9X7952 },
  4721. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
  4722. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4723. pbn_pericom_PI7C9X7952 },
  4724. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
  4725. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4726. pbn_pericom_PI7C9X7954 },
  4727. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
  4728. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4729. pbn_pericom_PI7C9X7954 },
  4730. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
  4731. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4732. pbn_pericom_PI7C9X7951 },
  4733. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
  4734. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4735. pbn_pericom_PI7C9X7952 },
  4736. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
  4737. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4738. pbn_pericom_PI7C9X7952 },
  4739. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
  4740. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4741. pbn_pericom_PI7C9X7954 },
  4742. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
  4743. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4744. pbn_pericom_PI7C9X7954 },
  4745. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
  4746. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4747. pbn_pericom_PI7C9X7952 },
  4748. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
  4749. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4750. pbn_pericom_PI7C9X7954 },
  4751. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
  4752. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4753. pbn_pericom_PI7C9X7952 },
  4754. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
  4755. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4756. pbn_pericom_PI7C9X7952 },
  4757. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
  4758. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4759. pbn_pericom_PI7C9X7954 },
  4760. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
  4761. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4762. pbn_pericom_PI7C9X7954 },
  4763. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
  4764. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4765. pbn_pericom_PI7C9X7952 },
  4766. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
  4767. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4768. pbn_pericom_PI7C9X7954 },
  4769. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
  4770. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4771. pbn_pericom_PI7C9X7954 },
  4772. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
  4773. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4774. pbn_pericom_PI7C9X7958 },
  4775. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
  4776. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4777. pbn_pericom_PI7C9X7958 },
  4778. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
  4779. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4780. pbn_pericom_PI7C9X7954 },
  4781. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
  4782. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4783. pbn_pericom_PI7C9X7958 },
  4784. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
  4785. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4786. pbn_pericom_PI7C9X7954 },
  4787. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
  4788. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4789. pbn_pericom_PI7C9X7958 },
  4790. { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
  4791. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4792. pbn_pericom_PI7C9X7954 },
  4793. /*
  4794. * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
  4795. */
  4796. { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
  4797. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4798. pbn_b0_1_115200 },
  4799. /*
  4800. * ITE
  4801. */
  4802. { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
  4803. PCI_ANY_ID, PCI_ANY_ID,
  4804. 0, 0,
  4805. pbn_b1_bt_1_115200 },
  4806. /*
  4807. * IntaShield IS-200
  4808. */
  4809. { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
  4810. PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
  4811. pbn_b2_2_115200 },
  4812. /*
  4813. * IntaShield IS-400
  4814. */
  4815. { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
  4816. PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
  4817. pbn_b2_4_115200 },
  4818. /*
  4819. * BrainBoxes UC-260
  4820. */
  4821. { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
  4822. PCI_ANY_ID, PCI_ANY_ID,
  4823. PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
  4824. pbn_b2_4_115200 },
  4825. { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
  4826. PCI_ANY_ID, PCI_ANY_ID,
  4827. PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
  4828. pbn_b2_4_115200 },
  4829. /*
  4830. * Perle PCI-RAS cards
  4831. */
  4832. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
  4833. PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
  4834. 0, 0, pbn_b2_4_921600 },
  4835. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
  4836. PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
  4837. 0, 0, pbn_b2_8_921600 },
  4838. /*
  4839. * Mainpine series cards: Fairly standard layout but fools
  4840. * parts of the autodetect in some cases and uses otherwise
  4841. * unmatched communications subclasses in the PCI Express case
  4842. */
  4843. { /* RockForceDUO */
  4844. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4845. PCI_VENDOR_ID_MAINPINE, 0x0200,
  4846. 0, 0, pbn_b0_2_115200 },
  4847. { /* RockForceQUATRO */
  4848. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4849. PCI_VENDOR_ID_MAINPINE, 0x0300,
  4850. 0, 0, pbn_b0_4_115200 },
  4851. { /* RockForceDUO+ */
  4852. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4853. PCI_VENDOR_ID_MAINPINE, 0x0400,
  4854. 0, 0, pbn_b0_2_115200 },
  4855. { /* RockForceQUATRO+ */
  4856. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4857. PCI_VENDOR_ID_MAINPINE, 0x0500,
  4858. 0, 0, pbn_b0_4_115200 },
  4859. { /* RockForce+ */
  4860. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4861. PCI_VENDOR_ID_MAINPINE, 0x0600,
  4862. 0, 0, pbn_b0_2_115200 },
  4863. { /* RockForce+ */
  4864. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4865. PCI_VENDOR_ID_MAINPINE, 0x0700,
  4866. 0, 0, pbn_b0_4_115200 },
  4867. { /* RockForceOCTO+ */
  4868. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4869. PCI_VENDOR_ID_MAINPINE, 0x0800,
  4870. 0, 0, pbn_b0_8_115200 },
  4871. { /* RockForceDUO+ */
  4872. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4873. PCI_VENDOR_ID_MAINPINE, 0x0C00,
  4874. 0, 0, pbn_b0_2_115200 },
  4875. { /* RockForceQUARTRO+ */
  4876. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4877. PCI_VENDOR_ID_MAINPINE, 0x0D00,
  4878. 0, 0, pbn_b0_4_115200 },
  4879. { /* RockForceOCTO+ */
  4880. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4881. PCI_VENDOR_ID_MAINPINE, 0x1D00,
  4882. 0, 0, pbn_b0_8_115200 },
  4883. { /* RockForceD1 */
  4884. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4885. PCI_VENDOR_ID_MAINPINE, 0x2000,
  4886. 0, 0, pbn_b0_1_115200 },
  4887. { /* RockForceF1 */
  4888. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4889. PCI_VENDOR_ID_MAINPINE, 0x2100,
  4890. 0, 0, pbn_b0_1_115200 },
  4891. { /* RockForceD2 */
  4892. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4893. PCI_VENDOR_ID_MAINPINE, 0x2200,
  4894. 0, 0, pbn_b0_2_115200 },
  4895. { /* RockForceF2 */
  4896. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4897. PCI_VENDOR_ID_MAINPINE, 0x2300,
  4898. 0, 0, pbn_b0_2_115200 },
  4899. { /* RockForceD4 */
  4900. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4901. PCI_VENDOR_ID_MAINPINE, 0x2400,
  4902. 0, 0, pbn_b0_4_115200 },
  4903. { /* RockForceF4 */
  4904. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4905. PCI_VENDOR_ID_MAINPINE, 0x2500,
  4906. 0, 0, pbn_b0_4_115200 },
  4907. { /* RockForceD8 */
  4908. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4909. PCI_VENDOR_ID_MAINPINE, 0x2600,
  4910. 0, 0, pbn_b0_8_115200 },
  4911. { /* RockForceF8 */
  4912. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4913. PCI_VENDOR_ID_MAINPINE, 0x2700,
  4914. 0, 0, pbn_b0_8_115200 },
  4915. { /* IQ Express D1 */
  4916. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4917. PCI_VENDOR_ID_MAINPINE, 0x3000,
  4918. 0, 0, pbn_b0_1_115200 },
  4919. { /* IQ Express F1 */
  4920. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4921. PCI_VENDOR_ID_MAINPINE, 0x3100,
  4922. 0, 0, pbn_b0_1_115200 },
  4923. { /* IQ Express D2 */
  4924. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4925. PCI_VENDOR_ID_MAINPINE, 0x3200,
  4926. 0, 0, pbn_b0_2_115200 },
  4927. { /* IQ Express F2 */
  4928. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4929. PCI_VENDOR_ID_MAINPINE, 0x3300,
  4930. 0, 0, pbn_b0_2_115200 },
  4931. { /* IQ Express D4 */
  4932. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4933. PCI_VENDOR_ID_MAINPINE, 0x3400,
  4934. 0, 0, pbn_b0_4_115200 },
  4935. { /* IQ Express F4 */
  4936. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4937. PCI_VENDOR_ID_MAINPINE, 0x3500,
  4938. 0, 0, pbn_b0_4_115200 },
  4939. { /* IQ Express D8 */
  4940. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4941. PCI_VENDOR_ID_MAINPINE, 0x3C00,
  4942. 0, 0, pbn_b0_8_115200 },
  4943. { /* IQ Express F8 */
  4944. PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
  4945. PCI_VENDOR_ID_MAINPINE, 0x3D00,
  4946. 0, 0, pbn_b0_8_115200 },
  4947. /*
  4948. * PA Semi PA6T-1682M on-chip UART
  4949. */
  4950. { PCI_VENDOR_ID_PASEMI, 0xa004,
  4951. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4952. pbn_pasemi_1682M },
  4953. /*
  4954. * National Instruments
  4955. */
  4956. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
  4957. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4958. pbn_b1_16_115200 },
  4959. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
  4960. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4961. pbn_b1_8_115200 },
  4962. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
  4963. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4964. pbn_b1_bt_4_115200 },
  4965. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
  4966. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4967. pbn_b1_bt_2_115200 },
  4968. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
  4969. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4970. pbn_b1_bt_4_115200 },
  4971. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
  4972. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4973. pbn_b1_bt_2_115200 },
  4974. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
  4975. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4976. pbn_b1_16_115200 },
  4977. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
  4978. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4979. pbn_b1_8_115200 },
  4980. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
  4981. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4982. pbn_b1_bt_4_115200 },
  4983. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
  4984. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4985. pbn_b1_bt_2_115200 },
  4986. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
  4987. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4988. pbn_b1_bt_4_115200 },
  4989. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
  4990. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4991. pbn_b1_bt_2_115200 },
  4992. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
  4993. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4994. pbn_ni8430_2 },
  4995. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
  4996. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  4997. pbn_ni8430_2 },
  4998. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
  4999. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5000. pbn_ni8430_4 },
  5001. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
  5002. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5003. pbn_ni8430_4 },
  5004. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
  5005. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5006. pbn_ni8430_8 },
  5007. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
  5008. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5009. pbn_ni8430_8 },
  5010. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
  5011. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5012. pbn_ni8430_16 },
  5013. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
  5014. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5015. pbn_ni8430_16 },
  5016. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
  5017. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5018. pbn_ni8430_2 },
  5019. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
  5020. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5021. pbn_ni8430_2 },
  5022. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
  5023. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5024. pbn_ni8430_4 },
  5025. { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
  5026. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5027. pbn_ni8430_4 },
  5028. /*
  5029. * ADDI-DATA GmbH communication cards <[email protected]>
  5030. */
  5031. { PCI_VENDOR_ID_ADDIDATA,
  5032. PCI_DEVICE_ID_ADDIDATA_APCI7500,
  5033. PCI_ANY_ID,
  5034. PCI_ANY_ID,
  5035. 0,
  5036. 0,
  5037. pbn_b0_4_115200 },
  5038. { PCI_VENDOR_ID_ADDIDATA,
  5039. PCI_DEVICE_ID_ADDIDATA_APCI7420,
  5040. PCI_ANY_ID,
  5041. PCI_ANY_ID,
  5042. 0,
  5043. 0,
  5044. pbn_b0_2_115200 },
  5045. { PCI_VENDOR_ID_ADDIDATA,
  5046. PCI_DEVICE_ID_ADDIDATA_APCI7300,
  5047. PCI_ANY_ID,
  5048. PCI_ANY_ID,
  5049. 0,
  5050. 0,
  5051. pbn_b0_1_115200 },
  5052. { PCI_VENDOR_ID_AMCC,
  5053. PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
  5054. PCI_ANY_ID,
  5055. PCI_ANY_ID,
  5056. 0,
  5057. 0,
  5058. pbn_b1_8_115200 },
  5059. { PCI_VENDOR_ID_ADDIDATA,
  5060. PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
  5061. PCI_ANY_ID,
  5062. PCI_ANY_ID,
  5063. 0,
  5064. 0,
  5065. pbn_b0_4_115200 },
  5066. { PCI_VENDOR_ID_ADDIDATA,
  5067. PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
  5068. PCI_ANY_ID,
  5069. PCI_ANY_ID,
  5070. 0,
  5071. 0,
  5072. pbn_b0_2_115200 },
  5073. { PCI_VENDOR_ID_ADDIDATA,
  5074. PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
  5075. PCI_ANY_ID,
  5076. PCI_ANY_ID,
  5077. 0,
  5078. 0,
  5079. pbn_b0_1_115200 },
  5080. { PCI_VENDOR_ID_ADDIDATA,
  5081. PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
  5082. PCI_ANY_ID,
  5083. PCI_ANY_ID,
  5084. 0,
  5085. 0,
  5086. pbn_b0_4_115200 },
  5087. { PCI_VENDOR_ID_ADDIDATA,
  5088. PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
  5089. PCI_ANY_ID,
  5090. PCI_ANY_ID,
  5091. 0,
  5092. 0,
  5093. pbn_b0_2_115200 },
  5094. { PCI_VENDOR_ID_ADDIDATA,
  5095. PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
  5096. PCI_ANY_ID,
  5097. PCI_ANY_ID,
  5098. 0,
  5099. 0,
  5100. pbn_b0_1_115200 },
  5101. { PCI_VENDOR_ID_ADDIDATA,
  5102. PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
  5103. PCI_ANY_ID,
  5104. PCI_ANY_ID,
  5105. 0,
  5106. 0,
  5107. pbn_b0_8_115200 },
  5108. { PCI_VENDOR_ID_ADDIDATA,
  5109. PCI_DEVICE_ID_ADDIDATA_APCIe7500,
  5110. PCI_ANY_ID,
  5111. PCI_ANY_ID,
  5112. 0,
  5113. 0,
  5114. pbn_ADDIDATA_PCIe_4_3906250 },
  5115. { PCI_VENDOR_ID_ADDIDATA,
  5116. PCI_DEVICE_ID_ADDIDATA_APCIe7420,
  5117. PCI_ANY_ID,
  5118. PCI_ANY_ID,
  5119. 0,
  5120. 0,
  5121. pbn_ADDIDATA_PCIe_2_3906250 },
  5122. { PCI_VENDOR_ID_ADDIDATA,
  5123. PCI_DEVICE_ID_ADDIDATA_APCIe7300,
  5124. PCI_ANY_ID,
  5125. PCI_ANY_ID,
  5126. 0,
  5127. 0,
  5128. pbn_ADDIDATA_PCIe_1_3906250 },
  5129. { PCI_VENDOR_ID_ADDIDATA,
  5130. PCI_DEVICE_ID_ADDIDATA_APCIe7800,
  5131. PCI_ANY_ID,
  5132. PCI_ANY_ID,
  5133. 0,
  5134. 0,
  5135. pbn_ADDIDATA_PCIe_8_3906250 },
  5136. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
  5137. PCI_VENDOR_ID_IBM, 0x0299,
  5138. 0, 0, pbn_b0_bt_2_115200 },
  5139. /*
  5140. * other NetMos 9835 devices are most likely handled by the
  5141. * parport_serial driver, check drivers/parport/parport_serial.c
  5142. * before adding them here.
  5143. */
  5144. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
  5145. 0xA000, 0x1000,
  5146. 0, 0, pbn_b0_1_115200 },
  5147. /* the 9901 is a rebranded 9912 */
  5148. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
  5149. 0xA000, 0x1000,
  5150. 0, 0, pbn_b0_1_115200 },
  5151. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
  5152. 0xA000, 0x1000,
  5153. 0, 0, pbn_b0_1_115200 },
  5154. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
  5155. 0xA000, 0x1000,
  5156. 0, 0, pbn_b0_1_115200 },
  5157. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  5158. 0xA000, 0x1000,
  5159. 0, 0, pbn_b0_1_115200 },
  5160. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  5161. 0xA000, 0x3002,
  5162. 0, 0, pbn_NETMOS9900_2s_115200 },
  5163. /*
  5164. * Best Connectivity and Rosewill PCI Multi I/O cards
  5165. */
  5166. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
  5167. 0xA000, 0x1000,
  5168. 0, 0, pbn_b0_1_115200 },
  5169. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
  5170. 0xA000, 0x3002,
  5171. 0, 0, pbn_b0_bt_2_115200 },
  5172. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
  5173. 0xA000, 0x3004,
  5174. 0, 0, pbn_b0_bt_4_115200 },
  5175. /* Intel CE4100 */
  5176. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
  5177. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5178. pbn_ce4100_1_115200 },
  5179. /*
  5180. * Cronyx Omega PCI
  5181. */
  5182. { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
  5183. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5184. pbn_omegapci },
  5185. /*
  5186. * Broadcom TruManage
  5187. */
  5188. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
  5189. PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  5190. pbn_brcm_trumanage },
  5191. /*
  5192. * AgeStar as-prs2-009
  5193. */
  5194. { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
  5195. PCI_ANY_ID, PCI_ANY_ID,
  5196. 0, 0, pbn_b0_bt_2_115200 },
  5197. /*
  5198. * WCH CH353 series devices: The 2S1P is handled by parport_serial
  5199. * so not listed here.
  5200. */
  5201. { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
  5202. PCI_ANY_ID, PCI_ANY_ID,
  5203. 0, 0, pbn_b0_bt_4_115200 },
  5204. { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
  5205. PCI_ANY_ID, PCI_ANY_ID,
  5206. 0, 0, pbn_b0_bt_2_115200 },
  5207. { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
  5208. PCI_ANY_ID, PCI_ANY_ID,
  5209. 0, 0, pbn_b0_bt_4_115200 },
  5210. { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
  5211. PCI_ANY_ID, PCI_ANY_ID,
  5212. 0, 0, pbn_wch382_2 },
  5213. { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
  5214. PCI_ANY_ID, PCI_ANY_ID,
  5215. 0, 0, pbn_wch384_4 },
  5216. /*
  5217. * Commtech, Inc. Fastcom adapters
  5218. */
  5219. { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
  5220. PCI_ANY_ID, PCI_ANY_ID,
  5221. 0,
  5222. 0, pbn_b0_2_1152000_200 },
  5223. { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
  5224. PCI_ANY_ID, PCI_ANY_ID,
  5225. 0,
  5226. 0, pbn_b0_4_1152000_200 },
  5227. { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
  5228. PCI_ANY_ID, PCI_ANY_ID,
  5229. 0,
  5230. 0, pbn_b0_4_1152000_200 },
  5231. { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
  5232. PCI_ANY_ID, PCI_ANY_ID,
  5233. 0,
  5234. 0, pbn_b0_8_1152000_200 },
  5235. { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
  5236. PCI_ANY_ID, PCI_ANY_ID,
  5237. 0,
  5238. 0, pbn_exar_XR17V352 },
  5239. { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
  5240. PCI_ANY_ID, PCI_ANY_ID,
  5241. 0,
  5242. 0, pbn_exar_XR17V354 },
  5243. { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
  5244. PCI_ANY_ID, PCI_ANY_ID,
  5245. 0,
  5246. 0, pbn_exar_XR17V358 },
  5247. /* Fintek PCI serial cards */
  5248. { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
  5249. { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
  5250. { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
  5251. /* MKS Tenta SCOM-080x serial cards */
  5252. { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
  5253. { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
  5254. /* Amazon PCI serial device */
  5255. { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
  5256. /*
  5257. * These entries match devices with class COMMUNICATION_SERIAL,
  5258. * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
  5259. */
  5260. { PCI_ANY_ID, PCI_ANY_ID,
  5261. PCI_ANY_ID, PCI_ANY_ID,
  5262. PCI_CLASS_COMMUNICATION_SERIAL << 8,
  5263. 0xffff00, pbn_default },
  5264. { PCI_ANY_ID, PCI_ANY_ID,
  5265. PCI_ANY_ID, PCI_ANY_ID,
  5266. PCI_CLASS_COMMUNICATION_MODEM << 8,
  5267. 0xffff00, pbn_default },
  5268. { PCI_ANY_ID, PCI_ANY_ID,
  5269. PCI_ANY_ID, PCI_ANY_ID,
  5270. PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
  5271. 0xffff00, pbn_default },
  5272. { 0, }
  5273. };
  5274. static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
  5275. pci_channel_state_t state)
  5276. {
  5277. struct serial_private *priv = pci_get_drvdata(dev);
  5278. if (state == pci_channel_io_perm_failure)
  5279. return PCI_ERS_RESULT_DISCONNECT;
  5280. if (priv)
  5281. pciserial_detach_ports(priv);
  5282. pci_disable_device(dev);
  5283. return PCI_ERS_RESULT_NEED_RESET;
  5284. }
  5285. static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
  5286. {
  5287. int rc;
  5288. rc = pci_enable_device(dev);
  5289. if (rc)
  5290. return PCI_ERS_RESULT_DISCONNECT;
  5291. pci_restore_state(dev);
  5292. pci_save_state(dev);
  5293. return PCI_ERS_RESULT_RECOVERED;
  5294. }
  5295. static void serial8250_io_resume(struct pci_dev *dev)
  5296. {
  5297. struct serial_private *priv = pci_get_drvdata(dev);
  5298. struct serial_private *new;
  5299. if (!priv)
  5300. return;
  5301. new = pciserial_init_ports(dev, priv->board);
  5302. if (!IS_ERR(new)) {
  5303. pci_set_drvdata(dev, new);
  5304. kfree(priv);
  5305. }
  5306. }
  5307. static const struct pci_error_handlers serial8250_err_handler = {
  5308. .error_detected = serial8250_io_error_detected,
  5309. .slot_reset = serial8250_io_slot_reset,
  5310. .resume = serial8250_io_resume,
  5311. };
  5312. static struct pci_driver serial_pci_driver = {
  5313. .name = "serial",
  5314. .probe = pciserial_init_one,
  5315. .remove = pciserial_remove_one,
  5316. .driver = {
  5317. .pm = &pciserial_pm_ops,
  5318. },
  5319. .id_table = serial_pci_tbl,
  5320. .err_handler = &serial8250_err_handler,
  5321. };
  5322. module_pci_driver(serial_pci_driver);
  5323. MODULE_LICENSE("GPL");
  5324. MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
  5325. MODULE_DEVICE_TABLE(pci, serial_pci_tbl);