dw_wdt.c 8.1 KB

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  1. /*
  2. * Copyright 2010-2011 Picochip Ltd., Jamie Iles
  3. * http://www.picochip.com
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version
  8. * 2 of the License, or (at your option) any later version.
  9. *
  10. * This file implements a driver for the Synopsys DesignWare watchdog device
  11. * in the many subsystems. The watchdog has 16 different timeout periods
  12. * and these are a function of the input clock frequency.
  13. *
  14. * The DesignWare watchdog cannot be stopped once it has been started so we
  15. * do not implement a stop function. The watchdog core will continue to send
  16. * heartbeat requests after the watchdog device has been closed.
  17. */
  18. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19. #include <linux/bitops.h>
  20. #include <linux/clk.h>
  21. #include <linux/delay.h>
  22. #include <linux/err.h>
  23. #include <linux/io.h>
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/notifier.h>
  28. #include <linux/of.h>
  29. #include <linux/pm.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/reboot.h>
  32. #include <linux/watchdog.h>
  33. #define WDOG_CONTROL_REG_OFFSET 0x00
  34. #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
  35. #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
  36. #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4
  37. #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
  38. #define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
  39. #define WDOG_COUNTER_RESTART_KICK_VALUE 0x76
  40. /* The maximum TOP (timeout period) value that can be set in the watchdog. */
  41. #define DW_WDT_MAX_TOP 15
  42. #define DW_WDT_DEFAULT_SECONDS 30
  43. static bool nowayout = WATCHDOG_NOWAYOUT;
  44. module_param(nowayout, bool, 0);
  45. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  46. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  47. struct dw_wdt {
  48. void __iomem *regs;
  49. struct clk *clk;
  50. unsigned long rate;
  51. struct notifier_block restart_handler;
  52. struct watchdog_device wdd;
  53. };
  54. #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
  55. static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
  56. {
  57. return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
  58. WDOG_CONTROL_REG_WDT_EN_MASK;
  59. }
  60. static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top)
  61. {
  62. /*
  63. * There are 16 possible timeout values in 0..15 where the number of
  64. * cycles is 2 ^ (16 + i) and the watchdog counts down.
  65. */
  66. return (1U << (16 + top)) / dw_wdt->rate;
  67. }
  68. static int dw_wdt_get_top(struct dw_wdt *dw_wdt)
  69. {
  70. int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
  71. return dw_wdt_top_in_seconds(dw_wdt, top);
  72. }
  73. static int dw_wdt_ping(struct watchdog_device *wdd)
  74. {
  75. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  76. writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
  77. WDOG_COUNTER_RESTART_REG_OFFSET);
  78. return 0;
  79. }
  80. static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
  81. {
  82. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  83. int i, top_val = DW_WDT_MAX_TOP;
  84. /*
  85. * Iterate over the timeout values until we find the closest match. We
  86. * always look for >=.
  87. */
  88. for (i = 0; i <= DW_WDT_MAX_TOP; ++i)
  89. if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) {
  90. top_val = i;
  91. break;
  92. }
  93. /*
  94. * Set the new value in the watchdog. Some versions of dw_wdt
  95. * have have TOPINIT in the TIMEOUT_RANGE register (as per
  96. * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we
  97. * effectively get a pat of the watchdog right here.
  98. */
  99. writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
  100. dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
  101. wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val);
  102. return 0;
  103. }
  104. static int dw_wdt_start(struct watchdog_device *wdd)
  105. {
  106. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  107. dw_wdt_set_timeout(wdd, wdd->timeout);
  108. set_bit(WDOG_HW_RUNNING, &wdd->status);
  109. writel(WDOG_CONTROL_REG_WDT_EN_MASK,
  110. dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
  111. return 0;
  112. }
  113. static int dw_wdt_restart_handle(struct notifier_block *this,
  114. unsigned long mode, void *cmd)
  115. {
  116. struct dw_wdt *dw_wdt;
  117. u32 val;
  118. dw_wdt = container_of(this, struct dw_wdt, restart_handler);
  119. writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
  120. val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
  121. if (val & WDOG_CONTROL_REG_WDT_EN_MASK)
  122. writel(WDOG_COUNTER_RESTART_KICK_VALUE,
  123. dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
  124. else
  125. writel(WDOG_CONTROL_REG_WDT_EN_MASK,
  126. dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
  127. /* wait for reset to assert... */
  128. mdelay(500);
  129. return NOTIFY_DONE;
  130. }
  131. static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
  132. {
  133. struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  134. return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) /
  135. dw_wdt->rate;
  136. }
  137. static const struct watchdog_info dw_wdt_ident = {
  138. .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
  139. WDIOF_MAGICCLOSE,
  140. .identity = "Synopsys DesignWare Watchdog",
  141. };
  142. static const struct watchdog_ops dw_wdt_ops = {
  143. .owner = THIS_MODULE,
  144. .start = dw_wdt_start,
  145. .ping = dw_wdt_ping,
  146. .set_timeout = dw_wdt_set_timeout,
  147. .get_timeleft = dw_wdt_get_timeleft,
  148. };
  149. #ifdef CONFIG_PM_SLEEP
  150. static int dw_wdt_suspend(struct device *dev)
  151. {
  152. struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
  153. clk_disable_unprepare(dw_wdt->clk);
  154. return 0;
  155. }
  156. static int dw_wdt_resume(struct device *dev)
  157. {
  158. struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
  159. int err = clk_prepare_enable(dw_wdt->clk);
  160. if (err)
  161. return err;
  162. dw_wdt_ping(&dw_wdt->wdd);
  163. return 0;
  164. }
  165. #endif /* CONFIG_PM_SLEEP */
  166. static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
  167. static int dw_wdt_drv_probe(struct platform_device *pdev)
  168. {
  169. struct device *dev = &pdev->dev;
  170. struct watchdog_device *wdd;
  171. struct dw_wdt *dw_wdt;
  172. struct resource *mem;
  173. int ret;
  174. dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
  175. if (!dw_wdt)
  176. return -ENOMEM;
  177. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  178. dw_wdt->regs = devm_ioremap_resource(dev, mem);
  179. if (IS_ERR(dw_wdt->regs))
  180. return PTR_ERR(dw_wdt->regs);
  181. dw_wdt->clk = devm_clk_get(dev, NULL);
  182. if (IS_ERR(dw_wdt->clk))
  183. return PTR_ERR(dw_wdt->clk);
  184. ret = clk_prepare_enable(dw_wdt->clk);
  185. if (ret)
  186. return ret;
  187. dw_wdt->rate = clk_get_rate(dw_wdt->clk);
  188. if (dw_wdt->rate == 0) {
  189. ret = -EINVAL;
  190. goto out_disable_clk;
  191. }
  192. wdd = &dw_wdt->wdd;
  193. wdd->info = &dw_wdt_ident;
  194. wdd->ops = &dw_wdt_ops;
  195. wdd->min_timeout = 1;
  196. wdd->max_hw_heartbeat_ms =
  197. dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000;
  198. wdd->parent = dev;
  199. watchdog_set_drvdata(wdd, dw_wdt);
  200. watchdog_set_nowayout(wdd, nowayout);
  201. watchdog_init_timeout(wdd, 0, dev);
  202. /*
  203. * If the watchdog is already running, use its already configured
  204. * timeout. Otherwise use the default or the value provided through
  205. * devicetree.
  206. */
  207. if (dw_wdt_is_enabled(dw_wdt)) {
  208. wdd->timeout = dw_wdt_get_top(dw_wdt);
  209. set_bit(WDOG_HW_RUNNING, &wdd->status);
  210. } else {
  211. wdd->timeout = DW_WDT_DEFAULT_SECONDS;
  212. watchdog_init_timeout(wdd, 0, dev);
  213. }
  214. platform_set_drvdata(pdev, dw_wdt);
  215. ret = watchdog_register_device(wdd);
  216. if (ret)
  217. goto out_disable_clk;
  218. dw_wdt->restart_handler.notifier_call = dw_wdt_restart_handle;
  219. dw_wdt->restart_handler.priority = 128;
  220. ret = register_restart_handler(&dw_wdt->restart_handler);
  221. if (ret)
  222. pr_warn("cannot register restart handler\n");
  223. return 0;
  224. out_disable_clk:
  225. clk_disable_unprepare(dw_wdt->clk);
  226. return ret;
  227. }
  228. static int dw_wdt_drv_remove(struct platform_device *pdev)
  229. {
  230. struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
  231. unregister_restart_handler(&dw_wdt->restart_handler);
  232. watchdog_unregister_device(&dw_wdt->wdd);
  233. clk_disable_unprepare(dw_wdt->clk);
  234. return 0;
  235. }
  236. #ifdef CONFIG_OF
  237. static const struct of_device_id dw_wdt_of_match[] = {
  238. { .compatible = "snps,dw-wdt", },
  239. { /* sentinel */ }
  240. };
  241. MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
  242. #endif
  243. static struct platform_driver dw_wdt_driver = {
  244. .probe = dw_wdt_drv_probe,
  245. .remove = dw_wdt_drv_remove,
  246. .driver = {
  247. .name = "dw_wdt",
  248. .of_match_table = of_match_ptr(dw_wdt_of_match),
  249. .pm = &dw_wdt_pm_ops,
  250. },
  251. };
  252. module_platform_driver(dw_wdt_driver);
  253. MODULE_AUTHOR("Jamie Iles");
  254. MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
  255. MODULE_LICENSE("GPL");