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qcom,gpucc-sdm845.h

qcom,gpucc-sdm845.h 2.0 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify
    5. 

  5.  * it under the terms of the GNU General Public License version 2 and
    6. 

  6.  * only version 2 as published by the Free Software Foundation.
    7. 

  7.  *
    8. 

  8.  * This program is distributed in the hope that it will be useful,
    9. 

  9.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    10. 

  10.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    11. 

  11.  * GNU General Public License for more details.
    12. 

  12.  */
    13. 

  13. 

  14. #ifndef _DT_BINDINGS_CLK_MSM_GPU_CC_SDM845_H
    15. 

  15. #define _DT_BINDINGS_CLK_MSM_GPU_CC_SDM845_H
    16. 

  16. 

  17. /* GPUCC clock registers */
    18. 

  18. #define GPU_CC_ACD_AHB_CLK					0
    19. 

  19. #define GPU_CC_ACD_CXO_CLK					1
    20. 

  20. #define GPU_CC_CRC_AHB_CLK					2
    21. 

  21. #define GPU_CC_CX_APB_CLK					3
    22. 

  22. #define GPU_CC_CX_GMU_CLK					4
    23. 

  23. #define GPU_CC_CX_QDSS_AT_CLK					5
    24. 

  24. #define GPU_CC_CX_QDSS_TRIG_CLK					6
    25. 

  25. #define GPU_CC_CX_QDSS_TSCTR_CLK				7
    26. 

  26. #define GPU_CC_CX_SNOC_DVM_CLK					8
    27. 

  27. #define GPU_CC_CXO_AON_CLK					9
    28. 

  28. #define GPU_CC_CXO_CLK						10
    29. 

  29. #define GPU_CC_GX_GMU_CLK					11
    30. 

  30. #define GPU_CC_GX_QDSS_TSCTR_CLK				12
    31. 

  31. #define GPU_CC_GX_VSENSE_CLK					13
    32. 

  32. #define GPU_CC_PLL0_OUT_MAIN					14
    33. 

  33. #define GPU_CC_PLL0_OUT_ODD					15
    34. 

  34. #define GPU_CC_PLL0_OUT_TEST					16
    35. 

  35. #define GPU_CC_PLL1						17
    36. 

  36. #define GPU_CC_PLL1_OUT_EVEN					18
    37. 

  37. #define GPU_CC_PLL1_OUT_MAIN					19
    38. 

  38. #define GPU_CC_PLL1_OUT_ODD					20
    39. 

  39. #define GPU_CC_PLL1_OUT_TEST					21
    40. 

  40. #define GPU_CC_PLL_TEST_CLK					22
    41. 

  41. #define GPU_CC_SLEEP_CLK					23
    42. 

  42. #define GPU_CC_GMU_CLK_SRC					24
    43. 

  43. #define GPU_CC_CX_GFX3D_CLK					25
    44. 

  44. #define GPU_CC_CX_GFX3D_SLV_CLK					26
    45. 

  45. #define GPU_CC_PLL0						27
    46. 

  46. 

  47. /* GPUCC reset clock registers */
    48. 

  48. #define GPUCC_GPU_CC_ACD_BCR					0
    49. 

  49. #define GPUCC_GPU_CC_CX_BCR					1
    50. 

  50. #define GPUCC_GPU_CC_GFX3D_AON_BCR				2
    51. 

  51. #define GPUCC_GPU_CC_GMU_BCR					3
    52. 

  52. #define GPUCC_GPU_CC_GX_BCR					4
    53. 

  53. #define GPUCC_GPU_CC_SPDM_BCR					5
    54. 

  54. #define GPUCC_GPU_CC_XO_BCR					6
    55. 

  55. 

  56. /* GFX3D clock registers */
    57. 

  57. #define GPU_CC_PLL0_OUT_EVEN					1
    58. 

  58. #define GPU_CC_GX_GFX3D_CLK_SRC					2
    59. 

  59. #define GPU_CC_GX_GFX3D_CLK					3
    60. 

  60. #endif
    61.