clk-divider.c 16 KB

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  1. /*
  2. * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  3. * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
  4. * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Adjustable divider clock implementation
  11. */
  12. #include <linux/clk-provider.h>
  13. #include <linux/module.h>
  14. #include <linux/slab.h>
  15. #include <linux/io.h>
  16. #include <linux/err.h>
  17. #include <linux/string.h>
  18. #include <linux/log2.h>
  19. /*
  20. * DOC: basic adjustable divider clock that cannot gate
  21. *
  22. * Traits of this clock:
  23. * prepare - clk_prepare only ensures that parents are prepared
  24. * enable - clk_enable only ensures that parents are enabled
  25. * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
  26. * parent - fixed parent. No clk_set_parent support
  27. */
  28. #define div_mask(width) ((1 << (width)) - 1)
  29. static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
  30. u8 width)
  31. {
  32. unsigned int maxdiv = 0, mask = div_mask(width);
  33. const struct clk_div_table *clkt;
  34. for (clkt = table; clkt->div; clkt++)
  35. if (clkt->div > maxdiv && clkt->val <= mask)
  36. maxdiv = clkt->div;
  37. return maxdiv;
  38. }
  39. static unsigned int _get_table_mindiv(const struct clk_div_table *table)
  40. {
  41. unsigned int mindiv = UINT_MAX;
  42. const struct clk_div_table *clkt;
  43. for (clkt = table; clkt->div; clkt++)
  44. if (clkt->div < mindiv)
  45. mindiv = clkt->div;
  46. return mindiv;
  47. }
  48. static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
  49. unsigned long flags)
  50. {
  51. if (flags & CLK_DIVIDER_ONE_BASED)
  52. return div_mask(width);
  53. if (flags & CLK_DIVIDER_POWER_OF_TWO)
  54. return 1 << div_mask(width);
  55. if (table)
  56. return _get_table_maxdiv(table, width);
  57. return div_mask(width) + 1;
  58. }
  59. static unsigned int _get_table_div(const struct clk_div_table *table,
  60. unsigned int val)
  61. {
  62. const struct clk_div_table *clkt;
  63. for (clkt = table; clkt->div; clkt++)
  64. if (clkt->val == val)
  65. return clkt->div;
  66. return 0;
  67. }
  68. static unsigned int _get_div(const struct clk_div_table *table,
  69. unsigned int val, unsigned long flags, u8 width)
  70. {
  71. if (flags & CLK_DIVIDER_ONE_BASED)
  72. return val;
  73. if (flags & CLK_DIVIDER_POWER_OF_TWO)
  74. return 1 << val;
  75. if (flags & CLK_DIVIDER_MAX_AT_ZERO)
  76. return val ? val : div_mask(width) + 1;
  77. if (table)
  78. return _get_table_div(table, val);
  79. return val + 1;
  80. }
  81. static unsigned int _get_table_val(const struct clk_div_table *table,
  82. unsigned int div)
  83. {
  84. const struct clk_div_table *clkt;
  85. for (clkt = table; clkt->div; clkt++)
  86. if (clkt->div == div)
  87. return clkt->val;
  88. return 0;
  89. }
  90. static unsigned int _get_val(const struct clk_div_table *table,
  91. unsigned int div, unsigned long flags, u8 width)
  92. {
  93. if (flags & CLK_DIVIDER_ONE_BASED)
  94. return div;
  95. if (flags & CLK_DIVIDER_POWER_OF_TWO)
  96. return __ffs(div);
  97. if (flags & CLK_DIVIDER_MAX_AT_ZERO)
  98. return (div == div_mask(width) + 1) ? 0 : div;
  99. if (table)
  100. return _get_table_val(table, div);
  101. return div - 1;
  102. }
  103. unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
  104. unsigned int val,
  105. const struct clk_div_table *table,
  106. unsigned long flags)
  107. {
  108. struct clk_divider *divider = to_clk_divider(hw);
  109. unsigned int div;
  110. div = _get_div(table, val, flags, divider->width);
  111. if (!div) {
  112. WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
  113. "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
  114. clk_hw_get_name(hw));
  115. return parent_rate;
  116. }
  117. return DIV_ROUND_UP_ULL((u64)parent_rate, div);
  118. }
  119. EXPORT_SYMBOL_GPL(divider_recalc_rate);
  120. static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
  121. unsigned long parent_rate)
  122. {
  123. struct clk_divider *divider = to_clk_divider(hw);
  124. unsigned int val;
  125. val = clk_readl(divider->reg) >> divider->shift;
  126. val &= div_mask(divider->width);
  127. return divider_recalc_rate(hw, parent_rate, val, divider->table,
  128. divider->flags);
  129. }
  130. static bool _is_valid_table_div(const struct clk_div_table *table,
  131. unsigned int div)
  132. {
  133. const struct clk_div_table *clkt;
  134. for (clkt = table; clkt->div; clkt++)
  135. if (clkt->div == div)
  136. return true;
  137. return false;
  138. }
  139. static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
  140. unsigned long flags)
  141. {
  142. if (flags & CLK_DIVIDER_POWER_OF_TWO)
  143. return is_power_of_2(div);
  144. if (table)
  145. return _is_valid_table_div(table, div);
  146. return true;
  147. }
  148. static int _round_up_table(const struct clk_div_table *table, int div)
  149. {
  150. const struct clk_div_table *clkt;
  151. int up = INT_MAX;
  152. for (clkt = table; clkt->div; clkt++) {
  153. if (clkt->div == div)
  154. return clkt->div;
  155. else if (clkt->div < div)
  156. continue;
  157. if ((clkt->div - div) < (up - div))
  158. up = clkt->div;
  159. }
  160. return up;
  161. }
  162. static int _round_down_table(const struct clk_div_table *table, int div)
  163. {
  164. const struct clk_div_table *clkt;
  165. int down = _get_table_mindiv(table);
  166. for (clkt = table; clkt->div; clkt++) {
  167. if (clkt->div == div)
  168. return clkt->div;
  169. else if (clkt->div > div)
  170. continue;
  171. if ((div - clkt->div) < (div - down))
  172. down = clkt->div;
  173. }
  174. return down;
  175. }
  176. static int _div_round_up(const struct clk_div_table *table,
  177. unsigned long parent_rate, unsigned long rate,
  178. unsigned long flags)
  179. {
  180. int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
  181. if (flags & CLK_DIVIDER_POWER_OF_TWO)
  182. div = __roundup_pow_of_two(div);
  183. if (table)
  184. div = _round_up_table(table, div);
  185. return div;
  186. }
  187. static int _div_round_closest(const struct clk_div_table *table,
  188. unsigned long parent_rate, unsigned long rate,
  189. unsigned long flags)
  190. {
  191. int up, down;
  192. unsigned long up_rate, down_rate;
  193. up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
  194. down = parent_rate / rate;
  195. if (flags & CLK_DIVIDER_POWER_OF_TWO) {
  196. up = __roundup_pow_of_two(up);
  197. down = __rounddown_pow_of_two(down);
  198. } else if (table) {
  199. up = _round_up_table(table, up);
  200. down = _round_down_table(table, down);
  201. }
  202. up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
  203. down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
  204. return (rate - up_rate) <= (down_rate - rate) ? up : down;
  205. }
  206. static int _div_round(const struct clk_div_table *table,
  207. unsigned long parent_rate, unsigned long rate,
  208. unsigned long flags)
  209. {
  210. if (flags & CLK_DIVIDER_ROUND_CLOSEST)
  211. return _div_round_closest(table, parent_rate, rate, flags);
  212. return _div_round_up(table, parent_rate, rate, flags);
  213. }
  214. static bool _is_best_div(unsigned long rate, unsigned long now,
  215. unsigned long best, unsigned long flags)
  216. {
  217. if (flags & CLK_DIVIDER_ROUND_CLOSEST)
  218. return abs(rate - now) < abs(rate - best);
  219. else if (flags & CLK_DIVIDER_ROUND_KHZ)
  220. return (DIV_ROUND_CLOSEST(abs(rate - now), 1000)
  221. < DIV_ROUND_CLOSEST(abs(rate - best), 1000));
  222. return now <= rate && now > best;
  223. }
  224. static int _next_div(const struct clk_div_table *table, int div,
  225. unsigned long flags)
  226. {
  227. div++;
  228. if (flags & CLK_DIVIDER_POWER_OF_TWO)
  229. return __roundup_pow_of_two(div);
  230. if (table)
  231. return _round_up_table(table, div);
  232. return div;
  233. }
  234. static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
  235. unsigned long *best_parent_rate,
  236. const struct clk_div_table *table, u8 width,
  237. unsigned long flags)
  238. {
  239. struct clk_hw *parent = clk_hw_get_parent(hw);
  240. int i, bestdiv = 0;
  241. unsigned long parent_rate, best = 0, now, maxdiv;
  242. unsigned long parent_rate_saved = *best_parent_rate;
  243. if (!parent)
  244. return -EINVAL;
  245. if (!rate)
  246. rate = 1;
  247. maxdiv = _get_maxdiv(table, width, flags);
  248. if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
  249. parent_rate = *best_parent_rate;
  250. bestdiv = _div_round(table, parent_rate, rate, flags);
  251. bestdiv = bestdiv == 0 ? 1 : bestdiv;
  252. bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
  253. return bestdiv;
  254. }
  255. /*
  256. * The maximum divider we can use without overflowing
  257. * unsigned long in rate * i below
  258. */
  259. maxdiv = min(ULONG_MAX / rate, maxdiv);
  260. for (i = _next_div(table, 0, flags); i <= maxdiv;
  261. i = _next_div(table, i, flags)) {
  262. if (rate * i == parent_rate_saved) {
  263. /*
  264. * It's the most ideal case if the requested rate can be
  265. * divided from parent clock without needing to change
  266. * parent rate, so return the divider immediately.
  267. */
  268. *best_parent_rate = parent_rate_saved;
  269. return i;
  270. }
  271. parent_rate = clk_hw_round_rate(parent, rate * i);
  272. now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
  273. if (_is_best_div(rate, now, best, flags)) {
  274. bestdiv = i;
  275. best = now;
  276. *best_parent_rate = parent_rate;
  277. }
  278. }
  279. if (!bestdiv) {
  280. bestdiv = _get_maxdiv(table, width, flags);
  281. *best_parent_rate = clk_hw_round_rate(parent, 1);
  282. }
  283. return bestdiv;
  284. }
  285. long divider_round_rate(struct clk_hw *hw, unsigned long rate,
  286. unsigned long *prate, const struct clk_div_table *table,
  287. u8 width, unsigned long flags)
  288. {
  289. int div;
  290. div = clk_divider_bestdiv(hw, rate, prate, table, width, flags);
  291. return DIV_ROUND_UP_ULL((u64)*prate, div);
  292. }
  293. EXPORT_SYMBOL_GPL(divider_round_rate);
  294. static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
  295. unsigned long *prate)
  296. {
  297. struct clk_divider *divider = to_clk_divider(hw);
  298. int bestdiv;
  299. /* if read only, just return current value */
  300. if (divider->flags & CLK_DIVIDER_READ_ONLY) {
  301. bestdiv = clk_readl(divider->reg) >> divider->shift;
  302. bestdiv &= div_mask(divider->width);
  303. bestdiv = _get_div(divider->table, bestdiv, divider->flags,
  304. divider->width);
  305. return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
  306. }
  307. return divider_round_rate(hw, rate, prate, divider->table,
  308. divider->width, divider->flags);
  309. }
  310. int divider_get_val(unsigned long rate, unsigned long parent_rate,
  311. const struct clk_div_table *table, u8 width,
  312. unsigned long flags)
  313. {
  314. unsigned int div, value;
  315. div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
  316. if (!_is_valid_div(table, div, flags))
  317. return -EINVAL;
  318. value = _get_val(table, div, flags, width);
  319. return min_t(unsigned int, value, div_mask(width));
  320. }
  321. EXPORT_SYMBOL_GPL(divider_get_val);
  322. static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
  323. unsigned long parent_rate)
  324. {
  325. struct clk_divider *divider = to_clk_divider(hw);
  326. unsigned int value;
  327. unsigned long flags = 0;
  328. u32 val;
  329. value = divider_get_val(rate, parent_rate, divider->table,
  330. divider->width, divider->flags);
  331. if (divider->lock)
  332. spin_lock_irqsave(divider->lock, flags);
  333. else
  334. __acquire(divider->lock);
  335. if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
  336. val = div_mask(divider->width) << (divider->shift + 16);
  337. } else {
  338. val = clk_readl(divider->reg);
  339. val &= ~(div_mask(divider->width) << divider->shift);
  340. }
  341. val |= value << divider->shift;
  342. clk_writel(val, divider->reg);
  343. if (divider->lock)
  344. spin_unlock_irqrestore(divider->lock, flags);
  345. else
  346. __release(divider->lock);
  347. return 0;
  348. }
  349. const struct clk_ops clk_divider_ops = {
  350. .recalc_rate = clk_divider_recalc_rate,
  351. .round_rate = clk_divider_round_rate,
  352. .set_rate = clk_divider_set_rate,
  353. };
  354. EXPORT_SYMBOL_GPL(clk_divider_ops);
  355. const struct clk_ops clk_divider_ro_ops = {
  356. .recalc_rate = clk_divider_recalc_rate,
  357. .round_rate = clk_divider_round_rate,
  358. };
  359. EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
  360. static struct clk_hw *_register_divider(struct device *dev, const char *name,
  361. const char *parent_name, unsigned long flags,
  362. void __iomem *reg, u8 shift, u8 width,
  363. u8 clk_divider_flags, const struct clk_div_table *table,
  364. spinlock_t *lock)
  365. {
  366. struct clk_divider *div;
  367. struct clk_hw *hw;
  368. struct clk_init_data init = {};
  369. int ret;
  370. if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
  371. if (width + shift > 16) {
  372. pr_warn("divider value exceeds LOWORD field\n");
  373. return ERR_PTR(-EINVAL);
  374. }
  375. }
  376. /* allocate the divider */
  377. div = kzalloc(sizeof(*div), GFP_KERNEL);
  378. if (!div)
  379. return ERR_PTR(-ENOMEM);
  380. init.name = name;
  381. if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
  382. init.ops = &clk_divider_ro_ops;
  383. else
  384. init.ops = &clk_divider_ops;
  385. init.flags = flags | CLK_IS_BASIC;
  386. init.parent_names = (parent_name ? &parent_name: NULL);
  387. init.num_parents = (parent_name ? 1 : 0);
  388. /* struct clk_divider assignments */
  389. div->reg = reg;
  390. div->shift = shift;
  391. div->width = width;
  392. div->flags = clk_divider_flags;
  393. div->lock = lock;
  394. div->hw.init = &init;
  395. div->table = table;
  396. /* register the clock */
  397. hw = &div->hw;
  398. ret = clk_hw_register(dev, hw);
  399. if (ret) {
  400. kfree(div);
  401. hw = ERR_PTR(ret);
  402. }
  403. return hw;
  404. }
  405. /**
  406. * clk_register_divider - register a divider clock with the clock framework
  407. * @dev: device registering this clock
  408. * @name: name of this clock
  409. * @parent_name: name of clock's parent
  410. * @flags: framework-specific flags
  411. * @reg: register address to adjust divider
  412. * @shift: number of bits to shift the bitfield
  413. * @width: width of the bitfield
  414. * @clk_divider_flags: divider-specific flags for this clock
  415. * @lock: shared register lock for this clock
  416. */
  417. struct clk *clk_register_divider(struct device *dev, const char *name,
  418. const char *parent_name, unsigned long flags,
  419. void __iomem *reg, u8 shift, u8 width,
  420. u8 clk_divider_flags, spinlock_t *lock)
  421. {
  422. struct clk_hw *hw;
  423. hw = _register_divider(dev, name, parent_name, flags, reg, shift,
  424. width, clk_divider_flags, NULL, lock);
  425. if (IS_ERR(hw))
  426. return ERR_CAST(hw);
  427. return hw->clk;
  428. }
  429. EXPORT_SYMBOL_GPL(clk_register_divider);
  430. /**
  431. * clk_hw_register_divider - register a divider clock with the clock framework
  432. * @dev: device registering this clock
  433. * @name: name of this clock
  434. * @parent_name: name of clock's parent
  435. * @flags: framework-specific flags
  436. * @reg: register address to adjust divider
  437. * @shift: number of bits to shift the bitfield
  438. * @width: width of the bitfield
  439. * @clk_divider_flags: divider-specific flags for this clock
  440. * @lock: shared register lock for this clock
  441. */
  442. struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
  443. const char *parent_name, unsigned long flags,
  444. void __iomem *reg, u8 shift, u8 width,
  445. u8 clk_divider_flags, spinlock_t *lock)
  446. {
  447. return _register_divider(dev, name, parent_name, flags, reg, shift,
  448. width, clk_divider_flags, NULL, lock);
  449. }
  450. EXPORT_SYMBOL_GPL(clk_hw_register_divider);
  451. /**
  452. * clk_register_divider_table - register a table based divider clock with
  453. * the clock framework
  454. * @dev: device registering this clock
  455. * @name: name of this clock
  456. * @parent_name: name of clock's parent
  457. * @flags: framework-specific flags
  458. * @reg: register address to adjust divider
  459. * @shift: number of bits to shift the bitfield
  460. * @width: width of the bitfield
  461. * @clk_divider_flags: divider-specific flags for this clock
  462. * @table: array of divider/value pairs ending with a div set to 0
  463. * @lock: shared register lock for this clock
  464. */
  465. struct clk *clk_register_divider_table(struct device *dev, const char *name,
  466. const char *parent_name, unsigned long flags,
  467. void __iomem *reg, u8 shift, u8 width,
  468. u8 clk_divider_flags, const struct clk_div_table *table,
  469. spinlock_t *lock)
  470. {
  471. struct clk_hw *hw;
  472. hw = _register_divider(dev, name, parent_name, flags, reg, shift,
  473. width, clk_divider_flags, table, lock);
  474. if (IS_ERR(hw))
  475. return ERR_CAST(hw);
  476. return hw->clk;
  477. }
  478. EXPORT_SYMBOL_GPL(clk_register_divider_table);
  479. /**
  480. * clk_hw_register_divider_table - register a table based divider clock with
  481. * the clock framework
  482. * @dev: device registering this clock
  483. * @name: name of this clock
  484. * @parent_name: name of clock's parent
  485. * @flags: framework-specific flags
  486. * @reg: register address to adjust divider
  487. * @shift: number of bits to shift the bitfield
  488. * @width: width of the bitfield
  489. * @clk_divider_flags: divider-specific flags for this clock
  490. * @table: array of divider/value pairs ending with a div set to 0
  491. * @lock: shared register lock for this clock
  492. */
  493. struct clk_hw *clk_hw_register_divider_table(struct device *dev,
  494. const char *name, const char *parent_name, unsigned long flags,
  495. void __iomem *reg, u8 shift, u8 width,
  496. u8 clk_divider_flags, const struct clk_div_table *table,
  497. spinlock_t *lock)
  498. {
  499. return _register_divider(dev, name, parent_name, flags, reg, shift,
  500. width, clk_divider_flags, table, lock);
  501. }
  502. EXPORT_SYMBOL_GPL(clk_hw_register_divider_table);
  503. void clk_unregister_divider(struct clk *clk)
  504. {
  505. struct clk_divider *div;
  506. struct clk_hw *hw;
  507. hw = __clk_get_hw(clk);
  508. if (!hw)
  509. return;
  510. div = to_clk_divider(hw);
  511. clk_unregister(clk);
  512. kfree(div);
  513. }
  514. EXPORT_SYMBOL_GPL(clk_unregister_divider);
  515. /**
  516. * clk_hw_unregister_divider - unregister a clk divider
  517. * @hw: hardware-specific clock data to unregister
  518. */
  519. void clk_hw_unregister_divider(struct clk_hw *hw)
  520. {
  521. struct clk_divider *div;
  522. div = to_clk_divider(hw);
  523. clk_hw_unregister(hw);
  524. kfree(div);
  525. }
  526. EXPORT_SYMBOL_GPL(clk_hw_unregister_divider);