ti-ads1015.c 18 KB

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  1. /*
  2. * ADS1015 - Texas Instruments Analog-to-Digital Converter
  3. *
  4. * Copyright (c) 2016, Intel Corporation.
  5. *
  6. * This file is subject to the terms and conditions of version 2 of
  7. * the GNU General Public License. See the file COPYING in the main
  8. * directory of this archive for more details.
  9. *
  10. * IIO driver for ADS1015 ADC 7-bit I2C slave address:
  11. * * 0x48 - ADDR connected to Ground
  12. * * 0x49 - ADDR connected to Vdd
  13. * * 0x4A - ADDR connected to SDA
  14. * * 0x4B - ADDR connected to SCL
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/i2c.h>
  19. #include <linux/regmap.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/mutex.h>
  22. #include <linux/delay.h>
  23. #include <linux/i2c/ads1015.h>
  24. #include <linux/iio/iio.h>
  25. #include <linux/iio/types.h>
  26. #include <linux/iio/sysfs.h>
  27. #include <linux/iio/buffer.h>
  28. #include <linux/iio/triggered_buffer.h>
  29. #include <linux/iio/trigger_consumer.h>
  30. #define ADS1015_DRV_NAME "ads1015"
  31. #define ADS1015_CONV_REG 0x00
  32. #define ADS1015_CFG_REG 0x01
  33. #define ADS1015_CFG_DR_SHIFT 5
  34. #define ADS1015_CFG_MOD_SHIFT 8
  35. #define ADS1015_CFG_PGA_SHIFT 9
  36. #define ADS1015_CFG_MUX_SHIFT 12
  37. #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
  38. #define ADS1015_CFG_MOD_MASK BIT(8)
  39. #define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
  40. #define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
  41. /* device operating modes */
  42. #define ADS1015_CONTINUOUS 0
  43. #define ADS1015_SINGLESHOT 1
  44. #define ADS1015_SLEEP_DELAY_MS 2000
  45. #define ADS1015_DEFAULT_PGA 2
  46. #define ADS1015_DEFAULT_DATA_RATE 4
  47. #define ADS1015_DEFAULT_CHAN 0
  48. enum {
  49. ADS1015,
  50. ADS1115,
  51. };
  52. enum ads1015_channels {
  53. ADS1015_AIN0_AIN1 = 0,
  54. ADS1015_AIN0_AIN3,
  55. ADS1015_AIN1_AIN3,
  56. ADS1015_AIN2_AIN3,
  57. ADS1015_AIN0,
  58. ADS1015_AIN1,
  59. ADS1015_AIN2,
  60. ADS1015_AIN3,
  61. ADS1015_TIMESTAMP,
  62. };
  63. static const unsigned int ads1015_data_rate[] = {
  64. 128, 250, 490, 920, 1600, 2400, 3300, 3300
  65. };
  66. static const unsigned int ads1115_data_rate[] = {
  67. 8, 16, 32, 64, 128, 250, 475, 860
  68. };
  69. /*
  70. * Translation from PGA bits to full-scale positive and negative input voltage
  71. * range in mV
  72. */
  73. static int ads1015_fullscale_range[] = {
  74. 6144, 4096, 2048, 1024, 512, 256, 256, 256
  75. };
  76. #define ADS1015_V_CHAN(_chan, _addr) { \
  77. .type = IIO_VOLTAGE, \
  78. .indexed = 1, \
  79. .address = _addr, \
  80. .channel = _chan, \
  81. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  82. BIT(IIO_CHAN_INFO_SCALE) | \
  83. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  84. .scan_index = _addr, \
  85. .scan_type = { \
  86. .sign = 's', \
  87. .realbits = 12, \
  88. .storagebits = 16, \
  89. .shift = 4, \
  90. .endianness = IIO_CPU, \
  91. }, \
  92. .datasheet_name = "AIN"#_chan, \
  93. }
  94. #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
  95. .type = IIO_VOLTAGE, \
  96. .differential = 1, \
  97. .indexed = 1, \
  98. .address = _addr, \
  99. .channel = _chan, \
  100. .channel2 = _chan2, \
  101. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  102. BIT(IIO_CHAN_INFO_SCALE) | \
  103. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  104. .scan_index = _addr, \
  105. .scan_type = { \
  106. .sign = 's', \
  107. .realbits = 12, \
  108. .storagebits = 16, \
  109. .shift = 4, \
  110. .endianness = IIO_CPU, \
  111. }, \
  112. .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
  113. }
  114. #define ADS1115_V_CHAN(_chan, _addr) { \
  115. .type = IIO_VOLTAGE, \
  116. .indexed = 1, \
  117. .address = _addr, \
  118. .channel = _chan, \
  119. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  120. BIT(IIO_CHAN_INFO_SCALE) | \
  121. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  122. .scan_index = _addr, \
  123. .scan_type = { \
  124. .sign = 's', \
  125. .realbits = 16, \
  126. .storagebits = 16, \
  127. .endianness = IIO_CPU, \
  128. }, \
  129. .datasheet_name = "AIN"#_chan, \
  130. }
  131. #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
  132. .type = IIO_VOLTAGE, \
  133. .differential = 1, \
  134. .indexed = 1, \
  135. .address = _addr, \
  136. .channel = _chan, \
  137. .channel2 = _chan2, \
  138. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  139. BIT(IIO_CHAN_INFO_SCALE) | \
  140. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  141. .scan_index = _addr, \
  142. .scan_type = { \
  143. .sign = 's', \
  144. .realbits = 16, \
  145. .storagebits = 16, \
  146. .endianness = IIO_CPU, \
  147. }, \
  148. .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
  149. }
  150. struct ads1015_data {
  151. struct regmap *regmap;
  152. /*
  153. * Protects ADC ops, e.g: concurrent sysfs/buffered
  154. * data reads, configuration updates
  155. */
  156. struct mutex lock;
  157. struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
  158. unsigned int *data_rate;
  159. /*
  160. * Set to true when the ADC is switched to the continuous-conversion
  161. * mode and exits from a power-down state. This flag is used to avoid
  162. * getting the stale result from the conversion register.
  163. */
  164. bool conv_invalid;
  165. };
  166. static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
  167. {
  168. return (reg == ADS1015_CFG_REG);
  169. }
  170. static const struct regmap_config ads1015_regmap_config = {
  171. .reg_bits = 8,
  172. .val_bits = 16,
  173. .max_register = ADS1015_CFG_REG,
  174. .writeable_reg = ads1015_is_writeable_reg,
  175. };
  176. static const struct iio_chan_spec ads1015_channels[] = {
  177. ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
  178. ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
  179. ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
  180. ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
  181. ADS1015_V_CHAN(0, ADS1015_AIN0),
  182. ADS1015_V_CHAN(1, ADS1015_AIN1),
  183. ADS1015_V_CHAN(2, ADS1015_AIN2),
  184. ADS1015_V_CHAN(3, ADS1015_AIN3),
  185. IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
  186. };
  187. static const struct iio_chan_spec ads1115_channels[] = {
  188. ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
  189. ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
  190. ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
  191. ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
  192. ADS1115_V_CHAN(0, ADS1015_AIN0),
  193. ADS1115_V_CHAN(1, ADS1015_AIN1),
  194. ADS1115_V_CHAN(2, ADS1015_AIN2),
  195. ADS1115_V_CHAN(3, ADS1015_AIN3),
  196. IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
  197. };
  198. static int ads1015_set_power_state(struct ads1015_data *data, bool on)
  199. {
  200. int ret;
  201. struct device *dev = regmap_get_device(data->regmap);
  202. if (on) {
  203. ret = pm_runtime_get_sync(dev);
  204. if (ret < 0)
  205. pm_runtime_put_noidle(dev);
  206. } else {
  207. pm_runtime_mark_last_busy(dev);
  208. ret = pm_runtime_put_autosuspend(dev);
  209. }
  210. return ret < 0 ? ret : 0;
  211. }
  212. static
  213. int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
  214. {
  215. int ret, pga, dr, conv_time;
  216. unsigned int old, mask, cfg;
  217. if (chan < 0 || chan >= ADS1015_CHANNELS)
  218. return -EINVAL;
  219. ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
  220. if (ret)
  221. return ret;
  222. pga = data->channel_data[chan].pga;
  223. dr = data->channel_data[chan].data_rate;
  224. mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
  225. ADS1015_CFG_DR_MASK;
  226. cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
  227. dr << ADS1015_CFG_DR_SHIFT;
  228. cfg = (old & ~mask) | (cfg & mask);
  229. ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
  230. if (ret)
  231. return ret;
  232. if (old != cfg || data->conv_invalid) {
  233. int dr_old = (old & ADS1015_CFG_DR_MASK) >>
  234. ADS1015_CFG_DR_SHIFT;
  235. conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]);
  236. conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
  237. conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
  238. usleep_range(conv_time, conv_time + 1);
  239. data->conv_invalid = false;
  240. }
  241. return regmap_read(data->regmap, ADS1015_CONV_REG, val);
  242. }
  243. static irqreturn_t ads1015_trigger_handler(int irq, void *p)
  244. {
  245. struct iio_poll_func *pf = p;
  246. struct iio_dev *indio_dev = pf->indio_dev;
  247. struct ads1015_data *data = iio_priv(indio_dev);
  248. s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding + 4x s16 timestamp */
  249. int chan, ret, res;
  250. memset(buf, 0, sizeof(buf));
  251. mutex_lock(&data->lock);
  252. chan = find_first_bit(indio_dev->active_scan_mask,
  253. indio_dev->masklength);
  254. ret = ads1015_get_adc_result(data, chan, &res);
  255. if (ret < 0) {
  256. mutex_unlock(&data->lock);
  257. goto err;
  258. }
  259. buf[0] = res;
  260. mutex_unlock(&data->lock);
  261. iio_push_to_buffers_with_timestamp(indio_dev, buf,
  262. iio_get_time_ns(indio_dev));
  263. err:
  264. iio_trigger_notify_done(indio_dev->trig);
  265. return IRQ_HANDLED;
  266. }
  267. static int ads1015_set_scale(struct ads1015_data *data,
  268. struct iio_chan_spec const *chan,
  269. int scale, int uscale)
  270. {
  271. int i, ret, rindex = -1;
  272. int fullscale = div_s64((scale * 1000000LL + uscale) <<
  273. (chan->scan_type.realbits - 1), 1000000);
  274. for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
  275. if (ads1015_fullscale_range[i] == fullscale) {
  276. rindex = i;
  277. break;
  278. }
  279. }
  280. if (rindex < 0)
  281. return -EINVAL;
  282. ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
  283. ADS1015_CFG_PGA_MASK,
  284. rindex << ADS1015_CFG_PGA_SHIFT);
  285. if (ret < 0)
  286. return ret;
  287. data->channel_data[chan->address].pga = rindex;
  288. return 0;
  289. }
  290. static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
  291. {
  292. int i;
  293. for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
  294. if (data->data_rate[i] == rate) {
  295. data->channel_data[chan].data_rate = i;
  296. return 0;
  297. }
  298. }
  299. return -EINVAL;
  300. }
  301. static int ads1015_read_raw(struct iio_dev *indio_dev,
  302. struct iio_chan_spec const *chan, int *val,
  303. int *val2, long mask)
  304. {
  305. int ret, idx;
  306. struct ads1015_data *data = iio_priv(indio_dev);
  307. mutex_lock(&indio_dev->mlock);
  308. mutex_lock(&data->lock);
  309. switch (mask) {
  310. case IIO_CHAN_INFO_RAW: {
  311. int shift = chan->scan_type.shift;
  312. if (iio_buffer_enabled(indio_dev)) {
  313. ret = -EBUSY;
  314. break;
  315. }
  316. ret = ads1015_set_power_state(data, true);
  317. if (ret < 0)
  318. break;
  319. ret = ads1015_get_adc_result(data, chan->address, val);
  320. if (ret < 0) {
  321. ads1015_set_power_state(data, false);
  322. break;
  323. }
  324. *val = sign_extend32(*val >> shift, 15 - shift);
  325. ret = ads1015_set_power_state(data, false);
  326. if (ret < 0)
  327. break;
  328. ret = IIO_VAL_INT;
  329. break;
  330. }
  331. case IIO_CHAN_INFO_SCALE:
  332. idx = data->channel_data[chan->address].pga;
  333. *val = ads1015_fullscale_range[idx];
  334. *val2 = chan->scan_type.realbits - 1;
  335. ret = IIO_VAL_FRACTIONAL_LOG2;
  336. break;
  337. case IIO_CHAN_INFO_SAMP_FREQ:
  338. idx = data->channel_data[chan->address].data_rate;
  339. *val = data->data_rate[idx];
  340. ret = IIO_VAL_INT;
  341. break;
  342. default:
  343. ret = -EINVAL;
  344. break;
  345. }
  346. mutex_unlock(&data->lock);
  347. mutex_unlock(&indio_dev->mlock);
  348. return ret;
  349. }
  350. static int ads1015_write_raw(struct iio_dev *indio_dev,
  351. struct iio_chan_spec const *chan, int val,
  352. int val2, long mask)
  353. {
  354. struct ads1015_data *data = iio_priv(indio_dev);
  355. int ret;
  356. mutex_lock(&data->lock);
  357. switch (mask) {
  358. case IIO_CHAN_INFO_SCALE:
  359. ret = ads1015_set_scale(data, chan, val, val2);
  360. break;
  361. case IIO_CHAN_INFO_SAMP_FREQ:
  362. ret = ads1015_set_data_rate(data, chan->address, val);
  363. break;
  364. default:
  365. ret = -EINVAL;
  366. break;
  367. }
  368. mutex_unlock(&data->lock);
  369. return ret;
  370. }
  371. static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
  372. {
  373. return ads1015_set_power_state(iio_priv(indio_dev), true);
  374. }
  375. static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
  376. {
  377. return ads1015_set_power_state(iio_priv(indio_dev), false);
  378. }
  379. static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
  380. .preenable = ads1015_buffer_preenable,
  381. .postenable = iio_triggered_buffer_postenable,
  382. .predisable = iio_triggered_buffer_predisable,
  383. .postdisable = ads1015_buffer_postdisable,
  384. .validate_scan_mask = &iio_validate_scan_mask_onehot,
  385. };
  386. static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
  387. "3 2 1 0.5 0.25 0.125");
  388. static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
  389. "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
  390. static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
  391. sampling_frequency_available, "128 250 490 920 1600 2400 3300");
  392. static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
  393. sampling_frequency_available, "8 16 32 64 128 250 475 860");
  394. static struct attribute *ads1015_attributes[] = {
  395. &iio_const_attr_ads1015_scale_available.dev_attr.attr,
  396. &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
  397. NULL,
  398. };
  399. static const struct attribute_group ads1015_attribute_group = {
  400. .attrs = ads1015_attributes,
  401. };
  402. static struct attribute *ads1115_attributes[] = {
  403. &iio_const_attr_ads1115_scale_available.dev_attr.attr,
  404. &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
  405. NULL,
  406. };
  407. static const struct attribute_group ads1115_attribute_group = {
  408. .attrs = ads1115_attributes,
  409. };
  410. static struct iio_info ads1015_info = {
  411. .driver_module = THIS_MODULE,
  412. .read_raw = ads1015_read_raw,
  413. .write_raw = ads1015_write_raw,
  414. .attrs = &ads1015_attribute_group,
  415. };
  416. static struct iio_info ads1115_info = {
  417. .driver_module = THIS_MODULE,
  418. .read_raw = ads1015_read_raw,
  419. .write_raw = ads1015_write_raw,
  420. .attrs = &ads1115_attribute_group,
  421. };
  422. #ifdef CONFIG_OF
  423. static int ads1015_get_channels_config_of(struct i2c_client *client)
  424. {
  425. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  426. struct ads1015_data *data = iio_priv(indio_dev);
  427. struct device_node *node;
  428. if (!client->dev.of_node ||
  429. !of_get_next_child(client->dev.of_node, NULL))
  430. return -EINVAL;
  431. for_each_child_of_node(client->dev.of_node, node) {
  432. u32 pval;
  433. unsigned int channel;
  434. unsigned int pga = ADS1015_DEFAULT_PGA;
  435. unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
  436. if (of_property_read_u32(node, "reg", &pval)) {
  437. dev_err(&client->dev, "invalid reg on %s\n",
  438. node->full_name);
  439. continue;
  440. }
  441. channel = pval;
  442. if (channel >= ADS1015_CHANNELS) {
  443. dev_err(&client->dev,
  444. "invalid channel index %d on %s\n",
  445. channel, node->full_name);
  446. continue;
  447. }
  448. if (!of_property_read_u32(node, "ti,gain", &pval)) {
  449. pga = pval;
  450. if (pga > 6) {
  451. dev_err(&client->dev, "invalid gain on %s\n",
  452. node->full_name);
  453. of_node_put(node);
  454. return -EINVAL;
  455. }
  456. }
  457. if (!of_property_read_u32(node, "ti,datarate", &pval)) {
  458. data_rate = pval;
  459. if (data_rate > 7) {
  460. dev_err(&client->dev,
  461. "invalid data_rate on %s\n",
  462. node->full_name);
  463. of_node_put(node);
  464. return -EINVAL;
  465. }
  466. }
  467. data->channel_data[channel].pga = pga;
  468. data->channel_data[channel].data_rate = data_rate;
  469. }
  470. return 0;
  471. }
  472. #endif
  473. static void ads1015_get_channels_config(struct i2c_client *client)
  474. {
  475. unsigned int k;
  476. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  477. struct ads1015_data *data = iio_priv(indio_dev);
  478. struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
  479. /* prefer platform data */
  480. if (pdata) {
  481. memcpy(data->channel_data, pdata->channel_data,
  482. sizeof(data->channel_data));
  483. return;
  484. }
  485. #ifdef CONFIG_OF
  486. if (!ads1015_get_channels_config_of(client))
  487. return;
  488. #endif
  489. /* fallback on default configuration */
  490. for (k = 0; k < ADS1015_CHANNELS; ++k) {
  491. data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
  492. data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
  493. }
  494. }
  495. static int ads1015_probe(struct i2c_client *client,
  496. const struct i2c_device_id *id)
  497. {
  498. struct iio_dev *indio_dev;
  499. struct ads1015_data *data;
  500. int ret;
  501. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
  502. if (!indio_dev)
  503. return -ENOMEM;
  504. data = iio_priv(indio_dev);
  505. i2c_set_clientdata(client, indio_dev);
  506. mutex_init(&data->lock);
  507. indio_dev->dev.parent = &client->dev;
  508. indio_dev->dev.of_node = client->dev.of_node;
  509. indio_dev->name = ADS1015_DRV_NAME;
  510. indio_dev->modes = INDIO_DIRECT_MODE;
  511. switch (id->driver_data) {
  512. case ADS1015:
  513. indio_dev->channels = ads1015_channels;
  514. indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
  515. indio_dev->info = &ads1015_info;
  516. data->data_rate = (unsigned int *) &ads1015_data_rate;
  517. break;
  518. case ADS1115:
  519. indio_dev->channels = ads1115_channels;
  520. indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
  521. indio_dev->info = &ads1115_info;
  522. data->data_rate = (unsigned int *) &ads1115_data_rate;
  523. break;
  524. }
  525. /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
  526. ads1015_get_channels_config(client);
  527. data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
  528. if (IS_ERR(data->regmap)) {
  529. dev_err(&client->dev, "Failed to allocate register map\n");
  530. return PTR_ERR(data->regmap);
  531. }
  532. ret = iio_triggered_buffer_setup(indio_dev, NULL,
  533. ads1015_trigger_handler,
  534. &ads1015_buffer_setup_ops);
  535. if (ret < 0) {
  536. dev_err(&client->dev, "iio triggered buffer setup failed\n");
  537. return ret;
  538. }
  539. ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
  540. ADS1015_CFG_MOD_MASK,
  541. ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
  542. if (ret)
  543. return ret;
  544. data->conv_invalid = true;
  545. ret = pm_runtime_set_active(&client->dev);
  546. if (ret)
  547. goto err_buffer_cleanup;
  548. pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
  549. pm_runtime_use_autosuspend(&client->dev);
  550. pm_runtime_enable(&client->dev);
  551. ret = iio_device_register(indio_dev);
  552. if (ret < 0) {
  553. dev_err(&client->dev, "Failed to register IIO device\n");
  554. goto err_buffer_cleanup;
  555. }
  556. return 0;
  557. err_buffer_cleanup:
  558. iio_triggered_buffer_cleanup(indio_dev);
  559. return ret;
  560. }
  561. static int ads1015_remove(struct i2c_client *client)
  562. {
  563. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  564. struct ads1015_data *data = iio_priv(indio_dev);
  565. iio_device_unregister(indio_dev);
  566. pm_runtime_disable(&client->dev);
  567. pm_runtime_set_suspended(&client->dev);
  568. pm_runtime_put_noidle(&client->dev);
  569. iio_triggered_buffer_cleanup(indio_dev);
  570. /* power down single shot mode */
  571. return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
  572. ADS1015_CFG_MOD_MASK,
  573. ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
  574. }
  575. #ifdef CONFIG_PM
  576. static int ads1015_runtime_suspend(struct device *dev)
  577. {
  578. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  579. struct ads1015_data *data = iio_priv(indio_dev);
  580. return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
  581. ADS1015_CFG_MOD_MASK,
  582. ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
  583. }
  584. static int ads1015_runtime_resume(struct device *dev)
  585. {
  586. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  587. struct ads1015_data *data = iio_priv(indio_dev);
  588. int ret;
  589. ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
  590. ADS1015_CFG_MOD_MASK,
  591. ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
  592. if (!ret)
  593. data->conv_invalid = true;
  594. return ret;
  595. }
  596. #endif
  597. static const struct dev_pm_ops ads1015_pm_ops = {
  598. SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
  599. ads1015_runtime_resume, NULL)
  600. };
  601. static const struct i2c_device_id ads1015_id[] = {
  602. {"ads1015", ADS1015},
  603. {"ads1115", ADS1115},
  604. {}
  605. };
  606. MODULE_DEVICE_TABLE(i2c, ads1015_id);
  607. static struct i2c_driver ads1015_driver = {
  608. .driver = {
  609. .name = ADS1015_DRV_NAME,
  610. .pm = &ads1015_pm_ops,
  611. },
  612. .probe = ads1015_probe,
  613. .remove = ads1015_remove,
  614. .id_table = ads1015_id,
  615. };
  616. module_i2c_driver(ads1015_driver);
  617. MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
  618. MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
  619. MODULE_LICENSE("GPL v2");