phy-exynos-mipi-video.c 11 KB

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  1. /*
  2. * Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
  3. *
  4. * Copyright (C) 2013,2016 Samsung Electronics Co., Ltd.
  5. * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/kernel.h>
  14. #include <linux/mfd/syscon/exynos4-pmu.h>
  15. #include <linux/mfd/syscon/exynos5-pmu.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_device.h>
  20. #include <linux/phy/phy.h>
  21. #include <linux/regmap.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/mfd/syscon.h>
  24. enum exynos_mipi_phy_id {
  25. EXYNOS_MIPI_PHY_ID_NONE = -1,
  26. EXYNOS_MIPI_PHY_ID_CSIS0,
  27. EXYNOS_MIPI_PHY_ID_DSIM0,
  28. EXYNOS_MIPI_PHY_ID_CSIS1,
  29. EXYNOS_MIPI_PHY_ID_DSIM1,
  30. EXYNOS_MIPI_PHY_ID_CSIS2,
  31. EXYNOS_MIPI_PHYS_NUM
  32. };
  33. enum exynos_mipi_phy_regmap_id {
  34. EXYNOS_MIPI_REGMAP_PMU,
  35. EXYNOS_MIPI_REGMAP_DISP,
  36. EXYNOS_MIPI_REGMAP_CAM0,
  37. EXYNOS_MIPI_REGMAP_CAM1,
  38. EXYNOS_MIPI_REGMAPS_NUM
  39. };
  40. struct mipi_phy_device_desc {
  41. int num_phys;
  42. int num_regmaps;
  43. const char *regmap_names[EXYNOS_MIPI_REGMAPS_NUM];
  44. struct exynos_mipi_phy_desc {
  45. enum exynos_mipi_phy_id coupled_phy_id;
  46. u32 enable_val;
  47. unsigned int enable_reg;
  48. enum exynos_mipi_phy_regmap_id enable_map;
  49. u32 resetn_val;
  50. unsigned int resetn_reg;
  51. enum exynos_mipi_phy_regmap_id resetn_map;
  52. } phys[EXYNOS_MIPI_PHYS_NUM];
  53. };
  54. static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
  55. .num_regmaps = 1,
  56. .regmap_names = {"syscon"},
  57. .num_phys = 4,
  58. .phys = {
  59. {
  60. /* EXYNOS_MIPI_PHY_ID_CSIS0 */
  61. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
  62. .enable_val = EXYNOS4_MIPI_PHY_ENABLE,
  63. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  64. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  65. .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
  66. .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  67. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  68. }, {
  69. /* EXYNOS_MIPI_PHY_ID_DSIM0 */
  70. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
  71. .enable_val = EXYNOS4_MIPI_PHY_ENABLE,
  72. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  73. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  74. .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
  75. .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
  76. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  77. }, {
  78. /* EXYNOS_MIPI_PHY_ID_CSIS1 */
  79. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
  80. .enable_val = EXYNOS4_MIPI_PHY_ENABLE,
  81. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  82. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  83. .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
  84. .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  85. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  86. }, {
  87. /* EXYNOS_MIPI_PHY_ID_DSIM1 */
  88. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
  89. .enable_val = EXYNOS4_MIPI_PHY_ENABLE,
  90. .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  91. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  92. .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
  93. .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
  94. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  95. },
  96. },
  97. };
  98. static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
  99. .num_regmaps = 1,
  100. .regmap_names = {"syscon"},
  101. .num_phys = 5,
  102. .phys = {
  103. {
  104. /* EXYNOS_MIPI_PHY_ID_CSIS0 */
  105. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
  106. .enable_val = EXYNOS5_PHY_ENABLE,
  107. .enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
  108. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  109. .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
  110. .resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
  111. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  112. }, {
  113. /* EXYNOS_MIPI_PHY_ID_DSIM0 */
  114. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
  115. .enable_val = EXYNOS5_PHY_ENABLE,
  116. .enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
  117. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  118. .resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
  119. .resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
  120. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  121. }, {
  122. /* EXYNOS_MIPI_PHY_ID_CSIS1 */
  123. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
  124. .enable_val = EXYNOS5_PHY_ENABLE,
  125. .enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
  126. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  127. .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
  128. .resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
  129. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  130. }, {
  131. /* EXYNOS_MIPI_PHY_ID_DSIM1 */
  132. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
  133. .enable_val = EXYNOS5_PHY_ENABLE,
  134. .enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
  135. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  136. .resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
  137. .resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
  138. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  139. }, {
  140. /* EXYNOS_MIPI_PHY_ID_CSIS2 */
  141. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
  142. .enable_val = EXYNOS5_PHY_ENABLE,
  143. .enable_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
  144. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  145. .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
  146. .resetn_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
  147. .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
  148. },
  149. },
  150. };
  151. #define EXYNOS5433_SYSREG_DISP_MIPI_PHY 0x100C
  152. #define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON 0x1014
  153. #define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON 0x1020
  154. static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
  155. .num_regmaps = 4,
  156. .regmap_names = {
  157. "samsung,pmu-syscon",
  158. "samsung,disp-sysreg",
  159. "samsung,cam0-sysreg",
  160. "samsung,cam1-sysreg"
  161. },
  162. .num_phys = 5,
  163. .phys = {
  164. {
  165. /* EXYNOS_MIPI_PHY_ID_CSIS0 */
  166. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
  167. .enable_val = EXYNOS5_PHY_ENABLE,
  168. .enable_reg = EXYNOS5433_MIPI_PHY0_CONTROL,
  169. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  170. .resetn_val = BIT(0),
  171. .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
  172. .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
  173. }, {
  174. /* EXYNOS_MIPI_PHY_ID_DSIM0 */
  175. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
  176. .enable_val = EXYNOS5_PHY_ENABLE,
  177. .enable_reg = EXYNOS5433_MIPI_PHY0_CONTROL,
  178. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  179. .resetn_val = BIT(0),
  180. .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
  181. .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
  182. }, {
  183. /* EXYNOS_MIPI_PHY_ID_CSIS1 */
  184. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
  185. .enable_val = EXYNOS5_PHY_ENABLE,
  186. .enable_reg = EXYNOS5433_MIPI_PHY1_CONTROL,
  187. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  188. .resetn_val = BIT(1),
  189. .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
  190. .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
  191. }, {
  192. /* EXYNOS_MIPI_PHY_ID_DSIM1 */
  193. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
  194. .enable_val = EXYNOS5_PHY_ENABLE,
  195. .enable_reg = EXYNOS5433_MIPI_PHY1_CONTROL,
  196. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  197. .resetn_val = BIT(1),
  198. .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
  199. .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
  200. }, {
  201. /* EXYNOS_MIPI_PHY_ID_CSIS2 */
  202. .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
  203. .enable_val = EXYNOS5_PHY_ENABLE,
  204. .enable_reg = EXYNOS5433_MIPI_PHY2_CONTROL,
  205. .enable_map = EXYNOS_MIPI_REGMAP_PMU,
  206. .resetn_val = BIT(0),
  207. .resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
  208. .resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
  209. },
  210. },
  211. };
  212. struct exynos_mipi_video_phy {
  213. struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
  214. int num_phys;
  215. struct video_phy_desc {
  216. struct phy *phy;
  217. unsigned int index;
  218. const struct exynos_mipi_phy_desc *data;
  219. } phys[EXYNOS_MIPI_PHYS_NUM];
  220. spinlock_t slock;
  221. };
  222. static inline int __is_running(const struct exynos_mipi_phy_desc *data,
  223. struct exynos_mipi_video_phy *state)
  224. {
  225. u32 val;
  226. int ret;
  227. ret = regmap_read(state->regmaps[data->resetn_map], data->resetn_reg, &val);
  228. if (ret)
  229. return 0;
  230. return val & data->resetn_val;
  231. }
  232. static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
  233. struct exynos_mipi_video_phy *state, unsigned int on)
  234. {
  235. u32 val;
  236. spin_lock(&state->slock);
  237. /* disable in PMU sysreg */
  238. if (!on && data->coupled_phy_id >= 0 &&
  239. !__is_running(state->phys[data->coupled_phy_id].data, state)) {
  240. regmap_read(state->regmaps[data->enable_map], data->enable_reg,
  241. &val);
  242. val &= ~data->enable_val;
  243. regmap_write(state->regmaps[data->enable_map], data->enable_reg,
  244. val);
  245. }
  246. /* PHY reset */
  247. regmap_read(state->regmaps[data->resetn_map], data->resetn_reg, &val);
  248. val = on ? (val | data->resetn_val) : (val & ~data->resetn_val);
  249. regmap_write(state->regmaps[data->resetn_map], data->resetn_reg, val);
  250. /* enable in PMU sysreg */
  251. if (on) {
  252. regmap_read(state->regmaps[data->enable_map], data->enable_reg,
  253. &val);
  254. val |= data->enable_val;
  255. regmap_write(state->regmaps[data->enable_map], data->enable_reg,
  256. val);
  257. }
  258. spin_unlock(&state->slock);
  259. return 0;
  260. }
  261. #define to_mipi_video_phy(desc) \
  262. container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index])
  263. static int exynos_mipi_video_phy_power_on(struct phy *phy)
  264. {
  265. struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
  266. struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
  267. return __set_phy_state(phy_desc->data, state, 1);
  268. }
  269. static int exynos_mipi_video_phy_power_off(struct phy *phy)
  270. {
  271. struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
  272. struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
  273. return __set_phy_state(phy_desc->data, state, 0);
  274. }
  275. static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
  276. struct of_phandle_args *args)
  277. {
  278. struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
  279. if (WARN_ON(args->args[0] >= state->num_phys))
  280. return ERR_PTR(-ENODEV);
  281. return state->phys[args->args[0]].phy;
  282. }
  283. static const struct phy_ops exynos_mipi_video_phy_ops = {
  284. .power_on = exynos_mipi_video_phy_power_on,
  285. .power_off = exynos_mipi_video_phy_power_off,
  286. .owner = THIS_MODULE,
  287. };
  288. static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
  289. {
  290. const struct mipi_phy_device_desc *phy_dev;
  291. struct exynos_mipi_video_phy *state;
  292. struct device *dev = &pdev->dev;
  293. struct device_node *np = dev->of_node;
  294. struct phy_provider *phy_provider;
  295. unsigned int i;
  296. phy_dev = of_device_get_match_data(dev);
  297. if (!phy_dev)
  298. return -ENODEV;
  299. state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
  300. if (!state)
  301. return -ENOMEM;
  302. for (i = 0; i < phy_dev->num_regmaps; i++) {
  303. state->regmaps[i] = syscon_regmap_lookup_by_phandle(np,
  304. phy_dev->regmap_names[i]);
  305. if (IS_ERR(state->regmaps[i]))
  306. return PTR_ERR(state->regmaps[i]);
  307. }
  308. state->num_phys = phy_dev->num_phys;
  309. spin_lock_init(&state->slock);
  310. dev_set_drvdata(dev, state);
  311. for (i = 0; i < state->num_phys; i++) {
  312. struct phy *phy = devm_phy_create(dev, NULL,
  313. &exynos_mipi_video_phy_ops);
  314. if (IS_ERR(phy)) {
  315. dev_err(dev, "failed to create PHY %d\n", i);
  316. return PTR_ERR(phy);
  317. }
  318. state->phys[i].phy = phy;
  319. state->phys[i].index = i;
  320. state->phys[i].data = &phy_dev->phys[i];
  321. phy_set_drvdata(phy, &state->phys[i]);
  322. }
  323. phy_provider = devm_of_phy_provider_register(dev,
  324. exynos_mipi_video_phy_xlate);
  325. return PTR_ERR_OR_ZERO(phy_provider);
  326. }
  327. static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
  328. {
  329. .compatible = "samsung,s5pv210-mipi-video-phy",
  330. .data = &s5pv210_mipi_phy,
  331. }, {
  332. .compatible = "samsung,exynos5420-mipi-video-phy",
  333. .data = &exynos5420_mipi_phy,
  334. }, {
  335. .compatible = "samsung,exynos5433-mipi-video-phy",
  336. .data = &exynos5433_mipi_phy,
  337. },
  338. { /* sentinel */ },
  339. };
  340. MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
  341. static struct platform_driver exynos_mipi_video_phy_driver = {
  342. .probe = exynos_mipi_video_phy_probe,
  343. .driver = {
  344. .of_match_table = exynos_mipi_video_phy_of_match,
  345. .name = "exynos-mipi-video-phy",
  346. }
  347. };
  348. module_platform_driver(exynos_mipi_video_phy_driver);
  349. MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver");
  350. MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
  351. MODULE_LICENSE("GPL v2");