intel_bxt_pmic_thermal.c 7.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300
  1. /*
  2. * Intel Broxton PMIC thermal driver
  3. *
  4. * Copyright (C) 2016 Intel Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License version
  8. * 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/slab.h>
  19. #include <linux/delay.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/device.h>
  22. #include <linux/thermal.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/sched.h>
  25. #include <linux/mfd/intel_soc_pmic.h>
  26. #define BXTWC_THRM0IRQ 0x4E04
  27. #define BXTWC_THRM1IRQ 0x4E05
  28. #define BXTWC_THRM2IRQ 0x4E06
  29. #define BXTWC_MTHRM0IRQ 0x4E12
  30. #define BXTWC_MTHRM1IRQ 0x4E13
  31. #define BXTWC_MTHRM2IRQ 0x4E14
  32. #define BXTWC_STHRM0IRQ 0x4F19
  33. #define BXTWC_STHRM1IRQ 0x4F1A
  34. #define BXTWC_STHRM2IRQ 0x4F1B
  35. struct trip_config_map {
  36. u16 irq_reg;
  37. u16 irq_en;
  38. u16 evt_stat;
  39. u8 irq_mask;
  40. u8 irq_en_mask;
  41. u8 evt_mask;
  42. u8 trip_num;
  43. };
  44. struct thermal_irq_map {
  45. char handle[20];
  46. int num_trips;
  47. const struct trip_config_map *trip_config;
  48. };
  49. struct pmic_thermal_data {
  50. const struct thermal_irq_map *maps;
  51. int num_maps;
  52. };
  53. static const struct trip_config_map bxtwc_str0_trip_config[] = {
  54. {
  55. .irq_reg = BXTWC_THRM0IRQ,
  56. .irq_mask = 0x01,
  57. .irq_en = BXTWC_MTHRM0IRQ,
  58. .irq_en_mask = 0x01,
  59. .evt_stat = BXTWC_STHRM0IRQ,
  60. .evt_mask = 0x01,
  61. .trip_num = 0
  62. },
  63. {
  64. .irq_reg = BXTWC_THRM0IRQ,
  65. .irq_mask = 0x10,
  66. .irq_en = BXTWC_MTHRM0IRQ,
  67. .irq_en_mask = 0x10,
  68. .evt_stat = BXTWC_STHRM0IRQ,
  69. .evt_mask = 0x10,
  70. .trip_num = 1
  71. }
  72. };
  73. static const struct trip_config_map bxtwc_str1_trip_config[] = {
  74. {
  75. .irq_reg = BXTWC_THRM0IRQ,
  76. .irq_mask = 0x02,
  77. .irq_en = BXTWC_MTHRM0IRQ,
  78. .irq_en_mask = 0x02,
  79. .evt_stat = BXTWC_STHRM0IRQ,
  80. .evt_mask = 0x02,
  81. .trip_num = 0
  82. },
  83. {
  84. .irq_reg = BXTWC_THRM0IRQ,
  85. .irq_mask = 0x20,
  86. .irq_en = BXTWC_MTHRM0IRQ,
  87. .irq_en_mask = 0x20,
  88. .evt_stat = BXTWC_STHRM0IRQ,
  89. .evt_mask = 0x20,
  90. .trip_num = 1
  91. },
  92. };
  93. static const struct trip_config_map bxtwc_str2_trip_config[] = {
  94. {
  95. .irq_reg = BXTWC_THRM0IRQ,
  96. .irq_mask = 0x04,
  97. .irq_en = BXTWC_MTHRM0IRQ,
  98. .irq_en_mask = 0x04,
  99. .evt_stat = BXTWC_STHRM0IRQ,
  100. .evt_mask = 0x04,
  101. .trip_num = 0
  102. },
  103. {
  104. .irq_reg = BXTWC_THRM0IRQ,
  105. .irq_mask = 0x40,
  106. .irq_en = BXTWC_MTHRM0IRQ,
  107. .irq_en_mask = 0x40,
  108. .evt_stat = BXTWC_STHRM0IRQ,
  109. .evt_mask = 0x40,
  110. .trip_num = 1
  111. },
  112. };
  113. static const struct trip_config_map bxtwc_str3_trip_config[] = {
  114. {
  115. .irq_reg = BXTWC_THRM2IRQ,
  116. .irq_mask = 0x10,
  117. .irq_en = BXTWC_MTHRM2IRQ,
  118. .irq_en_mask = 0x10,
  119. .evt_stat = BXTWC_STHRM2IRQ,
  120. .evt_mask = 0x10,
  121. .trip_num = 0
  122. },
  123. };
  124. static const struct thermal_irq_map bxtwc_thermal_irq_map[] = {
  125. {
  126. .handle = "STR0",
  127. .trip_config = bxtwc_str0_trip_config,
  128. .num_trips = ARRAY_SIZE(bxtwc_str0_trip_config),
  129. },
  130. {
  131. .handle = "STR1",
  132. .trip_config = bxtwc_str1_trip_config,
  133. .num_trips = ARRAY_SIZE(bxtwc_str1_trip_config),
  134. },
  135. {
  136. .handle = "STR2",
  137. .trip_config = bxtwc_str2_trip_config,
  138. .num_trips = ARRAY_SIZE(bxtwc_str2_trip_config),
  139. },
  140. {
  141. .handle = "STR3",
  142. .trip_config = bxtwc_str3_trip_config,
  143. .num_trips = ARRAY_SIZE(bxtwc_str3_trip_config),
  144. },
  145. };
  146. static const struct pmic_thermal_data bxtwc_thermal_data = {
  147. .maps = bxtwc_thermal_irq_map,
  148. .num_maps = ARRAY_SIZE(bxtwc_thermal_irq_map),
  149. };
  150. static irqreturn_t pmic_thermal_irq_handler(int irq, void *data)
  151. {
  152. struct platform_device *pdev = data;
  153. struct thermal_zone_device *tzd;
  154. struct pmic_thermal_data *td;
  155. struct intel_soc_pmic *pmic;
  156. struct regmap *regmap;
  157. u8 reg_val, mask, irq_stat, trip;
  158. u16 reg, evt_stat_reg;
  159. int i, j, ret;
  160. pmic = dev_get_drvdata(pdev->dev.parent);
  161. regmap = pmic->regmap;
  162. td = (struct pmic_thermal_data *)
  163. platform_get_device_id(pdev)->driver_data;
  164. /* Resolve thermal irqs */
  165. for (i = 0; i < td->num_maps; i++) {
  166. for (j = 0; j < td->maps[i].num_trips; j++) {
  167. reg = td->maps[i].trip_config[j].irq_reg;
  168. mask = td->maps[i].trip_config[j].irq_mask;
  169. /*
  170. * Read the irq register to resolve whether the
  171. * interrupt was triggered for this sensor
  172. */
  173. if (regmap_read(regmap, reg, &ret))
  174. return IRQ_HANDLED;
  175. reg_val = (u8)ret;
  176. irq_stat = ((u8)ret & mask);
  177. if (!irq_stat)
  178. continue;
  179. /*
  180. * Read the status register to find out what
  181. * event occurred i.e a high or a low
  182. */
  183. evt_stat_reg = td->maps[i].trip_config[j].evt_stat;
  184. if (regmap_read(regmap, evt_stat_reg, &ret))
  185. return IRQ_HANDLED;
  186. trip = td->maps[i].trip_config[j].trip_num;
  187. tzd = thermal_zone_get_zone_by_name(td->maps[i].handle);
  188. if (!IS_ERR(tzd))
  189. thermal_zone_device_update(tzd,
  190. THERMAL_EVENT_UNSPECIFIED);
  191. /* Clear the appropriate irq */
  192. regmap_write(regmap, reg, reg_val & mask);
  193. }
  194. }
  195. return IRQ_HANDLED;
  196. }
  197. static int pmic_thermal_probe(struct platform_device *pdev)
  198. {
  199. struct regmap_irq_chip_data *regmap_irq_chip;
  200. struct pmic_thermal_data *thermal_data;
  201. int ret, irq, virq, i, j, pmic_irq_count;
  202. struct intel_soc_pmic *pmic;
  203. struct regmap *regmap;
  204. struct device *dev;
  205. u16 reg;
  206. u8 mask;
  207. dev = &pdev->dev;
  208. pmic = dev_get_drvdata(pdev->dev.parent);
  209. if (!pmic) {
  210. dev_err(dev, "Failed to get struct intel_soc_pmic pointer\n");
  211. return -ENODEV;
  212. }
  213. thermal_data = (struct pmic_thermal_data *)
  214. platform_get_device_id(pdev)->driver_data;
  215. if (!thermal_data) {
  216. dev_err(dev, "No thermal data initialized!!\n");
  217. return -ENODEV;
  218. }
  219. regmap = pmic->regmap;
  220. regmap_irq_chip = pmic->irq_chip_data_level2;
  221. pmic_irq_count = 0;
  222. while ((irq = platform_get_irq(pdev, pmic_irq_count)) != -ENXIO) {
  223. virq = regmap_irq_get_virq(regmap_irq_chip, irq);
  224. if (virq < 0) {
  225. dev_err(dev, "failed to get virq by irq %d\n", irq);
  226. return virq;
  227. }
  228. ret = devm_request_threaded_irq(&pdev->dev, virq,
  229. NULL, pmic_thermal_irq_handler,
  230. IRQF_ONESHOT, "pmic_thermal", pdev);
  231. if (ret) {
  232. dev_err(dev, "request irq(%d) failed: %d\n", virq, ret);
  233. return ret;
  234. }
  235. pmic_irq_count++;
  236. }
  237. /* Enable thermal interrupts */
  238. for (i = 0; i < thermal_data->num_maps; i++) {
  239. for (j = 0; j < thermal_data->maps[i].num_trips; j++) {
  240. reg = thermal_data->maps[i].trip_config[j].irq_en;
  241. mask = thermal_data->maps[i].trip_config[j].irq_en_mask;
  242. ret = regmap_update_bits(regmap, reg, mask, 0x00);
  243. if (ret)
  244. return ret;
  245. }
  246. }
  247. return 0;
  248. }
  249. static const struct platform_device_id pmic_thermal_id_table[] = {
  250. {
  251. .name = "bxt_wcove_thermal",
  252. .driver_data = (kernel_ulong_t)&bxtwc_thermal_data,
  253. },
  254. {},
  255. };
  256. static struct platform_driver pmic_thermal_driver = {
  257. .probe = pmic_thermal_probe,
  258. .driver = {
  259. .name = "pmic_thermal",
  260. },
  261. .id_table = pmic_thermal_id_table,
  262. };
  263. MODULE_DEVICE_TABLE(platform, pmic_thermal_id_table);
  264. module_platform_driver(pmic_thermal_driver);
  265. MODULE_AUTHOR("Yegnesh S Iyer <[email protected]>");
  266. MODULE_DESCRIPTION("Intel Broxton PMIC Thermal Driver");
  267. MODULE_LICENSE("GPL v2");