intel_pch_thermal.c 10 KB

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  1. /* intel_pch_thermal.c - Intel PCH Thermal driver
  2. *
  3. * Copyright (c) 2015, Intel Corporation.
  4. *
  5. * Authors:
  6. * Tushar Dave <[email protected]>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms and conditions of the GNU General Public License,
  10. * version 2, as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. */
  18. #include <linux/module.h>
  19. #include <linux/types.h>
  20. #include <linux/init.h>
  21. #include <linux/pci.h>
  22. #include <linux/acpi.h>
  23. #include <linux/thermal.h>
  24. #include <linux/pm.h>
  25. /* Intel PCH thermal Device IDs */
  26. #define PCH_THERMAL_DID_HSW_1 0x9C24 /* Haswell PCH */
  27. #define PCH_THERMAL_DID_HSW_2 0x8C24 /* Haswell PCH */
  28. #define PCH_THERMAL_DID_WPT 0x9CA4 /* Wildcat Point */
  29. #define PCH_THERMAL_DID_SKL 0x9D31 /* Skylake PCH */
  30. /* Wildcat Point-LP PCH Thermal registers */
  31. #define WPT_TEMP 0x0000 /* Temperature */
  32. #define WPT_TSC 0x04 /* Thermal Sensor Control */
  33. #define WPT_TSS 0x06 /* Thermal Sensor Status */
  34. #define WPT_TSEL 0x08 /* Thermal Sensor Enable and Lock */
  35. #define WPT_TSREL 0x0A /* Thermal Sensor Report Enable and Lock */
  36. #define WPT_TSMIC 0x0C /* Thermal Sensor SMI Control */
  37. #define WPT_CTT 0x0010 /* Catastrophic Trip Point */
  38. #define WPT_TAHV 0x0014 /* Thermal Alert High Value */
  39. #define WPT_TALV 0x0018 /* Thermal Alert Low Value */
  40. #define WPT_TL 0x00000040 /* Throttle Value */
  41. #define WPT_PHL 0x0060 /* PCH Hot Level */
  42. #define WPT_PHLC 0x62 /* PHL Control */
  43. #define WPT_TAS 0x80 /* Thermal Alert Status */
  44. #define WPT_TSPIEN 0x82 /* PCI Interrupt Event Enables */
  45. #define WPT_TSGPEN 0x84 /* General Purpose Event Enables */
  46. /* Wildcat Point-LP PCH Thermal Register bit definitions */
  47. #define WPT_TEMP_TSR 0x00ff /* Temp TS Reading */
  48. #define WPT_TSC_CPDE 0x01 /* Catastrophic Power-Down Enable */
  49. #define WPT_TSS_TSDSS 0x10 /* Thermal Sensor Dynamic Shutdown Status */
  50. #define WPT_TSS_GPES 0x08 /* GPE status */
  51. #define WPT_TSEL_ETS 0x01 /* Enable TS */
  52. #define WPT_TSEL_PLDB 0x80 /* TSEL Policy Lock-Down Bit */
  53. #define WPT_TL_TOL 0x000001FF /* T0 Level */
  54. #define WPT_TL_T1L 0x1ff00000 /* T1 Level */
  55. #define WPT_TL_TTEN 0x20000000 /* TT Enable */
  56. static char driver_name[] = "Intel PCH thermal driver";
  57. struct pch_thermal_device {
  58. void __iomem *hw_base;
  59. const struct pch_dev_ops *ops;
  60. struct pci_dev *pdev;
  61. struct thermal_zone_device *tzd;
  62. int crt_trip_id;
  63. unsigned long crt_temp;
  64. int hot_trip_id;
  65. unsigned long hot_temp;
  66. int psv_trip_id;
  67. unsigned long psv_temp;
  68. bool bios_enabled;
  69. };
  70. #ifdef CONFIG_ACPI
  71. /*
  72. * On some platforms, there is a companion ACPI device, which adds
  73. * passive trip temperature using _PSV method. There is no specific
  74. * passive temperature setting in MMIO interface of this PCI device.
  75. */
  76. static void pch_wpt_add_acpi_psv_trip(struct pch_thermal_device *ptd,
  77. int *nr_trips)
  78. {
  79. struct acpi_device *adev;
  80. ptd->psv_trip_id = -1;
  81. adev = ACPI_COMPANION(&ptd->pdev->dev);
  82. if (adev) {
  83. unsigned long long r;
  84. acpi_status status;
  85. status = acpi_evaluate_integer(adev->handle, "_PSV", NULL,
  86. &r);
  87. if (ACPI_SUCCESS(status)) {
  88. unsigned long trip_temp;
  89. trip_temp = DECI_KELVIN_TO_MILLICELSIUS(r);
  90. if (trip_temp) {
  91. ptd->psv_temp = trip_temp;
  92. ptd->psv_trip_id = *nr_trips;
  93. ++(*nr_trips);
  94. }
  95. }
  96. }
  97. }
  98. #else
  99. static void pch_wpt_add_acpi_psv_trip(struct pch_thermal_device *ptd,
  100. int *nr_trips)
  101. {
  102. ptd->psv_trip_id = -1;
  103. }
  104. #endif
  105. static int pch_wpt_init(struct pch_thermal_device *ptd, int *nr_trips)
  106. {
  107. u8 tsel;
  108. u16 trip_temp;
  109. *nr_trips = 0;
  110. /* Check if BIOS has already enabled thermal sensor */
  111. if (WPT_TSS_TSDSS & readb(ptd->hw_base + WPT_TSS)) {
  112. ptd->bios_enabled = true;
  113. goto read_trips;
  114. }
  115. tsel = readb(ptd->hw_base + WPT_TSEL);
  116. /*
  117. * When TSEL's Policy Lock-Down bit is 1, TSEL become RO.
  118. * If so, thermal sensor cannot enable. Bail out.
  119. */
  120. if (tsel & WPT_TSEL_PLDB) {
  121. dev_err(&ptd->pdev->dev, "Sensor can't be enabled\n");
  122. return -ENODEV;
  123. }
  124. writeb(tsel|WPT_TSEL_ETS, ptd->hw_base + WPT_TSEL);
  125. if (!(WPT_TSS_TSDSS & readb(ptd->hw_base + WPT_TSS))) {
  126. dev_err(&ptd->pdev->dev, "Sensor can't be enabled\n");
  127. return -ENODEV;
  128. }
  129. read_trips:
  130. ptd->crt_trip_id = -1;
  131. trip_temp = readw(ptd->hw_base + WPT_CTT);
  132. trip_temp &= 0x1FF;
  133. if (trip_temp) {
  134. /* Resolution of 1/2 degree C and an offset of -50C */
  135. ptd->crt_temp = trip_temp * 1000 / 2 - 50000;
  136. ptd->crt_trip_id = 0;
  137. ++(*nr_trips);
  138. }
  139. ptd->hot_trip_id = -1;
  140. trip_temp = readw(ptd->hw_base + WPT_PHL);
  141. trip_temp &= 0x1FF;
  142. if (trip_temp) {
  143. /* Resolution of 1/2 degree C and an offset of -50C */
  144. ptd->hot_temp = trip_temp * 1000 / 2 - 50000;
  145. ptd->hot_trip_id = *nr_trips;
  146. ++(*nr_trips);
  147. }
  148. pch_wpt_add_acpi_psv_trip(ptd, nr_trips);
  149. return 0;
  150. }
  151. static int pch_wpt_get_temp(struct pch_thermal_device *ptd, int *temp)
  152. {
  153. u8 wpt_temp;
  154. wpt_temp = WPT_TEMP_TSR & readl(ptd->hw_base + WPT_TEMP);
  155. /* Resolution of 1/2 degree C and an offset of -50C */
  156. *temp = (wpt_temp * 1000 / 2 - 50000);
  157. return 0;
  158. }
  159. static int pch_wpt_suspend(struct pch_thermal_device *ptd)
  160. {
  161. u8 tsel;
  162. if (ptd->bios_enabled)
  163. return 0;
  164. tsel = readb(ptd->hw_base + WPT_TSEL);
  165. writeb(tsel & 0xFE, ptd->hw_base + WPT_TSEL);
  166. return 0;
  167. }
  168. static int pch_wpt_resume(struct pch_thermal_device *ptd)
  169. {
  170. u8 tsel;
  171. if (ptd->bios_enabled)
  172. return 0;
  173. tsel = readb(ptd->hw_base + WPT_TSEL);
  174. writeb(tsel | WPT_TSEL_ETS, ptd->hw_base + WPT_TSEL);
  175. return 0;
  176. }
  177. struct pch_dev_ops {
  178. int (*hw_init)(struct pch_thermal_device *ptd, int *nr_trips);
  179. int (*get_temp)(struct pch_thermal_device *ptd, int *temp);
  180. int (*suspend)(struct pch_thermal_device *ptd);
  181. int (*resume)(struct pch_thermal_device *ptd);
  182. };
  183. /* dev ops for Wildcat Point */
  184. static const struct pch_dev_ops pch_dev_ops_wpt = {
  185. .hw_init = pch_wpt_init,
  186. .get_temp = pch_wpt_get_temp,
  187. .suspend = pch_wpt_suspend,
  188. .resume = pch_wpt_resume,
  189. };
  190. static int pch_thermal_get_temp(struct thermal_zone_device *tzd, int *temp)
  191. {
  192. struct pch_thermal_device *ptd = tzd->devdata;
  193. return ptd->ops->get_temp(ptd, temp);
  194. }
  195. static int pch_get_trip_type(struct thermal_zone_device *tzd, int trip,
  196. enum thermal_trip_type *type)
  197. {
  198. struct pch_thermal_device *ptd = tzd->devdata;
  199. if (ptd->crt_trip_id == trip)
  200. *type = THERMAL_TRIP_CRITICAL;
  201. else if (ptd->hot_trip_id == trip)
  202. *type = THERMAL_TRIP_HOT;
  203. else if (ptd->psv_trip_id == trip)
  204. *type = THERMAL_TRIP_PASSIVE;
  205. else
  206. return -EINVAL;
  207. return 0;
  208. }
  209. static int pch_get_trip_temp(struct thermal_zone_device *tzd, int trip, int *temp)
  210. {
  211. struct pch_thermal_device *ptd = tzd->devdata;
  212. if (ptd->crt_trip_id == trip)
  213. *temp = ptd->crt_temp;
  214. else if (ptd->hot_trip_id == trip)
  215. *temp = ptd->hot_temp;
  216. else if (ptd->psv_trip_id == trip)
  217. *temp = ptd->psv_temp;
  218. else
  219. return -EINVAL;
  220. return 0;
  221. }
  222. static struct thermal_zone_device_ops tzd_ops = {
  223. .get_temp = pch_thermal_get_temp,
  224. .get_trip_type = pch_get_trip_type,
  225. .get_trip_temp = pch_get_trip_temp,
  226. };
  227. static int intel_pch_thermal_probe(struct pci_dev *pdev,
  228. const struct pci_device_id *id)
  229. {
  230. struct pch_thermal_device *ptd;
  231. int err;
  232. int nr_trips;
  233. char *dev_name;
  234. ptd = devm_kzalloc(&pdev->dev, sizeof(*ptd), GFP_KERNEL);
  235. if (!ptd)
  236. return -ENOMEM;
  237. switch (pdev->device) {
  238. case PCH_THERMAL_DID_WPT:
  239. ptd->ops = &pch_dev_ops_wpt;
  240. dev_name = "pch_wildcat_point";
  241. break;
  242. case PCH_THERMAL_DID_SKL:
  243. ptd->ops = &pch_dev_ops_wpt;
  244. dev_name = "pch_skylake";
  245. break;
  246. case PCH_THERMAL_DID_HSW_1:
  247. case PCH_THERMAL_DID_HSW_2:
  248. ptd->ops = &pch_dev_ops_wpt;
  249. dev_name = "pch_haswell";
  250. break;
  251. default:
  252. dev_err(&pdev->dev, "unknown pch thermal device\n");
  253. return -ENODEV;
  254. }
  255. pci_set_drvdata(pdev, ptd);
  256. ptd->pdev = pdev;
  257. err = pci_enable_device(pdev);
  258. if (err) {
  259. dev_err(&pdev->dev, "failed to enable pci device\n");
  260. return err;
  261. }
  262. err = pci_request_regions(pdev, driver_name);
  263. if (err) {
  264. dev_err(&pdev->dev, "failed to request pci region\n");
  265. goto error_disable;
  266. }
  267. ptd->hw_base = pci_ioremap_bar(pdev, 0);
  268. if (!ptd->hw_base) {
  269. err = -ENOMEM;
  270. dev_err(&pdev->dev, "failed to map mem base\n");
  271. goto error_release;
  272. }
  273. err = ptd->ops->hw_init(ptd, &nr_trips);
  274. if (err)
  275. goto error_cleanup;
  276. ptd->tzd = thermal_zone_device_register(dev_name, nr_trips, 0, ptd,
  277. &tzd_ops, NULL, 0, 0);
  278. if (IS_ERR(ptd->tzd)) {
  279. dev_err(&pdev->dev, "Failed to register thermal zone %s\n",
  280. dev_name);
  281. err = PTR_ERR(ptd->tzd);
  282. goto error_cleanup;
  283. }
  284. return 0;
  285. error_cleanup:
  286. iounmap(ptd->hw_base);
  287. error_release:
  288. pci_release_regions(pdev);
  289. error_disable:
  290. pci_disable_device(pdev);
  291. dev_err(&pdev->dev, "pci device failed to probe\n");
  292. return err;
  293. }
  294. static void intel_pch_thermal_remove(struct pci_dev *pdev)
  295. {
  296. struct pch_thermal_device *ptd = pci_get_drvdata(pdev);
  297. thermal_zone_device_unregister(ptd->tzd);
  298. iounmap(ptd->hw_base);
  299. pci_set_drvdata(pdev, NULL);
  300. pci_release_region(pdev, 0);
  301. pci_disable_device(pdev);
  302. }
  303. static int intel_pch_thermal_suspend(struct device *device)
  304. {
  305. struct pci_dev *pdev = to_pci_dev(device);
  306. struct pch_thermal_device *ptd = pci_get_drvdata(pdev);
  307. return ptd->ops->suspend(ptd);
  308. }
  309. static int intel_pch_thermal_resume(struct device *device)
  310. {
  311. struct pci_dev *pdev = to_pci_dev(device);
  312. struct pch_thermal_device *ptd = pci_get_drvdata(pdev);
  313. return ptd->ops->resume(ptd);
  314. }
  315. static struct pci_device_id intel_pch_thermal_id[] = {
  316. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_WPT) },
  317. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_SKL) },
  318. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_HSW_1) },
  319. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_HSW_2) },
  320. { 0, },
  321. };
  322. MODULE_DEVICE_TABLE(pci, intel_pch_thermal_id);
  323. static const struct dev_pm_ops intel_pch_pm_ops = {
  324. .suspend = intel_pch_thermal_suspend,
  325. .resume = intel_pch_thermal_resume,
  326. };
  327. static struct pci_driver intel_pch_thermal_driver = {
  328. .name = "intel_pch_thermal",
  329. .id_table = intel_pch_thermal_id,
  330. .probe = intel_pch_thermal_probe,
  331. .remove = intel_pch_thermal_remove,
  332. .driver.pm = &intel_pch_pm_ops,
  333. };
  334. module_pci_driver(intel_pch_thermal_driver);
  335. MODULE_LICENSE("GPL v2");
  336. MODULE_DESCRIPTION("Intel PCH Thermal driver");