tsens1xxx.c 18 KB

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  1. /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. */
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. #include <linux/err.h>
  17. #include <linux/of.h>
  18. #include <linux/vmalloc.h>
  19. #include "tsens.h"
  20. #include "thermal_core.h"
  21. #define TSENS_DRIVER_NAME "msm-tsens"
  22. #define TSENS_UPPER_LOWER_INTERRUPT_CTRL(n) (n)
  23. #define TSENS_INTERRUPT_EN BIT(0)
  24. #define TSENS_S0_UPPER_LOWER_STATUS_CTRL_ADDR(n) ((n) + 0x04)
  25. #define TSENS_UPPER_STATUS_CLR BIT(21)
  26. #define TSENS_LOWER_STATUS_CLR BIT(20)
  27. #define TSENS_UPPER_THRESHOLD_MASK 0xffc00
  28. #define TSENS_LOWER_THRESHOLD_MASK 0x3ff
  29. #define TSENS_UPPER_THRESHOLD_SHIFT 10
  30. #define TSENS_S0_STATUS_ADDR(n) ((n) + 0x30)
  31. #define TSENS_SN_ADDR_OFFSET 0x4
  32. #define TSENS_SN_STATUS_TEMP_MASK 0x3ff
  33. #define TSENS_SN_STATUS_LOWER_STATUS BIT(11)
  34. #define TSENS_SN_STATUS_UPPER_STATUS BIT(12)
  35. #define TSENS_STATUS_ADDR_OFFSET 2
  36. #define TSENS_TRDY_MASK BIT(0)
  37. #define TSENS_SN_STATUS_ADDR(n) ((n) + 0x44)
  38. #define TSENS_SN_STATUS_VALID BIT(14)
  39. #define TSENS_SN_STATUS_VALID_MASK 0x4000
  40. #define TSENS_TRDY_ADDR(n) ((n) + 0x84)
  41. #define TSENS_CTRL_ADDR(n) (n)
  42. #define TSENS_EN BIT(0)
  43. #define TSENS_CTRL_SENSOR_EN_MASK(n) ((n >> 3) & 0x7ff)
  44. #define TSENS_TRDY_RDY_MIN_TIME 2000
  45. #define TSENS_TRDY_RDY_MAX_TIME 2100
  46. #define TSENS_THRESHOLD_MAX_CODE 0x3ff
  47. #define TSENS_THRESHOLD_MIN_CODE 0x0
  48. #define TSENS_SCALE_MILLIDEG 1000
  49. /* eeprom layout data for 8937 */
  50. #define BASE0_MASK 0x000000ff
  51. #define BASE1_MASK 0xff000000
  52. #define BASE1_SHIFT 24
  53. #define S0_P1_MASK 0x000001f8
  54. #define S1_P1_MASK 0x001f8000
  55. #define S2_P1_MASK_0_4 0xf8000000
  56. #define S2_P1_MASK_5 0x00000001
  57. #define S3_P1_MASK 0x00001f80
  58. #define S4_P1_MASK 0x01f80000
  59. #define S5_P1_MASK 0x00003f00
  60. #define S6_P1_MASK 0x03f00000
  61. #define S7_P1_MASK 0x0000003f
  62. #define S8_P1_MASK 0x0003f000
  63. #define S9_P1_MASK 0x0000003f
  64. #define S10_P1_MASK 0x0003f000
  65. #define S0_P2_MASK 0x00007e00
  66. #define S1_P2_MASK 0x07e00000
  67. #define S2_P2_MASK 0x0000007e
  68. #define S3_P2_MASK 0x0007e000
  69. #define S4_P2_MASK 0x7e000000
  70. #define S5_P2_MASK 0x000fc000
  71. #define S6_P2_MASK 0xfc000000
  72. #define S7_P2_MASK 0x00000fc0
  73. #define S8_P2_MASK 0x00fc0000
  74. #define S9_P2_MASK 0x00000fc0
  75. #define S10_P2_MASK 0x00fc0000
  76. #define S0_P1_SHIFT 3
  77. #define S1_P1_SHIFT 15
  78. #define S2_P1_SHIFT_0_4 27
  79. #define S2_P1_SHIFT_5 5
  80. #define S3_P1_SHIFT 7
  81. #define S4_P1_SHIFT 19
  82. #define S5_P1_SHIFT 8
  83. #define S6_P1_SHIFT 20
  84. #define S8_P1_SHIFT 12
  85. #define S10_P1_SHIFT 12
  86. #define S0_P2_SHIFT 9
  87. #define S1_P2_SHIFT 21
  88. #define S2_P2_SHIFT 1
  89. #define S3_P2_SHIFT 13
  90. #define S4_P2_SHIFT 25
  91. #define S5_P2_SHIFT 14
  92. #define S6_P2_SHIFT 26
  93. #define S7_P2_SHIFT 6
  94. #define S8_P2_SHIFT 18
  95. #define S9_P2_SHIFT 6
  96. #define S10_P2_SHIFT 18
  97. #define CAL_SEL_MASK 0x00000007
  98. #define CAL_DEGC_PT1 30
  99. #define CAL_DEGC_PT2 120
  100. #define SLOPE_FACTOR 1000
  101. #define SLOPE_DEFAULT 3200
  102. /*
  103. * Use this function on devices where slope and offset calculations
  104. * depend on calibration data read from qfprom. On others the slope
  105. * and offset values are derived from tz->tzp->slope and tz->tzp->offset
  106. * resp.
  107. */
  108. static void compute_intercept_slope(struct tsens_device *tmdev, u32 *p1,
  109. u32 *p2, u32 mode)
  110. {
  111. int i;
  112. int num, den;
  113. for (i = 0; i < TSENS_1x_MAX_SENSORS; i++) {
  114. pr_debug(
  115. "sensor%d - data_point1:%#x data_point2:%#x\n",
  116. i, p1[i], p2[i]);
  117. tmdev->sensor[i].slope = SLOPE_DEFAULT;
  118. if (mode == TWO_PT_CALIB) {
  119. /*
  120. * slope (m) = adc_code2 - adc_code1 (y2 - y1)/
  121. * temp_120_degc - temp_30_degc (x2 - x1)
  122. */
  123. num = p2[i] - p1[i];
  124. num *= SLOPE_FACTOR;
  125. den = CAL_DEGC_PT2 - CAL_DEGC_PT1;
  126. tmdev->sensor[i].slope = num / den;
  127. }
  128. tmdev->sensor[i].offset = (p1[i] * SLOPE_FACTOR) -
  129. (CAL_DEGC_PT1 *
  130. tmdev->sensor[i].slope);
  131. pr_debug("offset:%d\n", tmdev->sensor[i].offset);
  132. }
  133. }
  134. static int code_to_degc(u32 adc_code, const struct tsens_sensor *sensor)
  135. {
  136. int degc, num, den;
  137. num = (adc_code * SLOPE_FACTOR) - sensor->offset;
  138. den = sensor->slope;
  139. if (num > 0)
  140. degc = num + (den / 2);
  141. else if (num < 0)
  142. degc = num - (den / 2);
  143. else
  144. degc = num;
  145. degc /= den;
  146. return degc;
  147. }
  148. static int degc_to_code(int degc, const struct tsens_sensor *sensor)
  149. {
  150. int code = ((degc * sensor->slope)
  151. + sensor->offset)/SLOPE_FACTOR;
  152. if (code > TSENS_THRESHOLD_MAX_CODE)
  153. code = TSENS_THRESHOLD_MAX_CODE;
  154. else if (code < TSENS_THRESHOLD_MIN_CODE)
  155. code = TSENS_THRESHOLD_MIN_CODE;
  156. pr_debug("raw_code:0x%x, degc:%d\n",
  157. code, degc);
  158. return code;
  159. }
  160. static int calibrate_8937(struct tsens_device *tmdev)
  161. {
  162. int base0 = 0, base1 = 0, i;
  163. u32 p1[TSENS_1x_MAX_SENSORS], p2[TSENS_1x_MAX_SENSORS];
  164. int mode = 0, tmp = 0;
  165. u32 qfprom_cdata[5] = {0, 0, 0, 0, 0};
  166. qfprom_cdata[0] = readl_relaxed(tmdev->tsens_calib_addr + 0x1D8);
  167. qfprom_cdata[1] = readl_relaxed(tmdev->tsens_calib_addr + 0x1DC);
  168. qfprom_cdata[2] = readl_relaxed(tmdev->tsens_calib_addr + 0x210);
  169. qfprom_cdata[3] = readl_relaxed(tmdev->tsens_calib_addr + 0x214);
  170. qfprom_cdata[4] = readl_relaxed(tmdev->tsens_calib_addr + 0x230);
  171. mode = (qfprom_cdata[2] & CAL_SEL_MASK);
  172. pr_debug("calibration mode is %d\n", mode);
  173. switch (mode) {
  174. case TWO_PT_CALIB:
  175. base1 = (qfprom_cdata[1] & BASE1_MASK) >> BASE1_SHIFT;
  176. p2[0] = (qfprom_cdata[2] & S0_P2_MASK) >> S0_P2_SHIFT;
  177. p2[1] = (qfprom_cdata[2] & S1_P2_MASK) >> S1_P2_SHIFT;
  178. p2[2] = (qfprom_cdata[3] & S2_P2_MASK) >> S2_P2_SHIFT;
  179. p2[3] = (qfprom_cdata[3] & S3_P2_MASK) >> S3_P2_SHIFT;
  180. p2[4] = (qfprom_cdata[3] & S4_P2_MASK) >> S4_P2_SHIFT;
  181. p2[5] = (qfprom_cdata[0] & S5_P2_MASK) >> S5_P2_SHIFT;
  182. p2[6] = (qfprom_cdata[0] & S6_P2_MASK) >> S6_P2_SHIFT;
  183. p2[7] = (qfprom_cdata[1] & S7_P2_MASK) >> S7_P2_SHIFT;
  184. p2[8] = (qfprom_cdata[1] & S8_P2_MASK) >> S8_P2_SHIFT;
  185. p2[9] = (qfprom_cdata[4] & S9_P2_MASK) >> S9_P2_SHIFT;
  186. p2[10] = (qfprom_cdata[4] & S10_P2_MASK) >> S10_P2_SHIFT;
  187. for (i = 0; i < TSENS_1x_MAX_SENSORS; i++)
  188. p2[i] = ((base1 + p2[i]) << 2);
  189. /* Fall through */
  190. case ONE_PT_CALIB2:
  191. base0 = (qfprom_cdata[0] & BASE0_MASK);
  192. p1[0] = (qfprom_cdata[2] & S0_P1_MASK) >> S0_P1_SHIFT;
  193. p1[1] = (qfprom_cdata[2] & S1_P1_MASK) >> S1_P1_SHIFT;
  194. p1[2] = (qfprom_cdata[2] & S2_P1_MASK_0_4) >> S2_P1_SHIFT_0_4;
  195. tmp = (qfprom_cdata[3] & S2_P1_MASK_5) << S2_P1_SHIFT_5;
  196. p1[2] |= tmp;
  197. p1[3] = (qfprom_cdata[3] & S3_P1_MASK) >> S3_P1_SHIFT;
  198. p1[4] = (qfprom_cdata[3] & S4_P1_MASK) >> S4_P1_SHIFT;
  199. p1[5] = (qfprom_cdata[0] & S5_P1_MASK) >> S5_P1_SHIFT;
  200. p1[6] = (qfprom_cdata[0] & S6_P1_MASK) >> S6_P1_SHIFT;
  201. p1[7] = (qfprom_cdata[1] & S7_P1_MASK);
  202. p1[8] = (qfprom_cdata[1] & S8_P1_MASK) >> S8_P1_SHIFT;
  203. p1[9] = (qfprom_cdata[4] & S9_P1_MASK);
  204. p1[10] = (qfprom_cdata[4] & S10_P1_MASK) >> S10_P1_SHIFT;
  205. for (i = 0; i < TSENS_1x_MAX_SENSORS; i++)
  206. p1[i] = (((base0) + p1[i]) << 2);
  207. break;
  208. default:
  209. for (i = 0; i < TSENS_1x_MAX_SENSORS; i++) {
  210. p1[i] = 500;
  211. p2[i] = 780;
  212. }
  213. break;
  214. }
  215. compute_intercept_slope(tmdev, p1, p2, mode);
  216. return 0;
  217. }
  218. static int tsens1xxx_get_temp(struct tsens_sensor *sensor, int *temp)
  219. {
  220. struct tsens_device *tmdev = NULL;
  221. unsigned int code;
  222. void __iomem *sensor_addr;
  223. void __iomem *trdy_addr;
  224. int last_temp = 0, last_temp2 = 0, last_temp3 = 0;
  225. bool last_temp_valid = false, last_temp2_valid = false;
  226. bool last_temp3_valid = false;
  227. if (!sensor)
  228. return -EINVAL;
  229. tmdev = sensor->tmdev;
  230. trdy_addr = TSENS_TRDY_ADDR(tmdev->tsens_tm_addr);
  231. sensor_addr = TSENS_SN_STATUS_ADDR(tmdev->tsens_tm_addr);
  232. code = readl_relaxed(sensor_addr +
  233. (sensor->hw_id << TSENS_STATUS_ADDR_OFFSET));
  234. last_temp = code & TSENS_SN_STATUS_TEMP_MASK;
  235. if (tmdev->ctrl_data->valid_status_check) {
  236. if (code & TSENS_SN_STATUS_VALID)
  237. last_temp_valid = true;
  238. else {
  239. code = readl_relaxed(sensor_addr +
  240. (sensor->hw_id << TSENS_STATUS_ADDR_OFFSET));
  241. last_temp2 = code & TSENS_SN_STATUS_TEMP_MASK;
  242. if (code & TSENS_SN_STATUS_VALID) {
  243. last_temp = last_temp2;
  244. last_temp2_valid = true;
  245. } else {
  246. code = readl_relaxed(sensor_addr +
  247. (sensor->hw_id <<
  248. TSENS_STATUS_ADDR_OFFSET));
  249. last_temp3 = code & TSENS_SN_STATUS_TEMP_MASK;
  250. if (code & TSENS_SN_STATUS_VALID) {
  251. last_temp = last_temp3;
  252. last_temp3_valid = true;
  253. }
  254. }
  255. }
  256. }
  257. if ((tmdev->ctrl_data->valid_status_check) &&
  258. (!last_temp_valid && !last_temp2_valid && !last_temp3_valid)) {
  259. if (last_temp == last_temp2)
  260. last_temp = last_temp2;
  261. else if (last_temp2 == last_temp3)
  262. last_temp = last_temp3;
  263. }
  264. *temp = code_to_degc(last_temp, sensor);
  265. *temp = *temp * TSENS_SCALE_MILLIDEG;
  266. if (tmdev->ops->dbg)
  267. tmdev->ops->dbg(tmdev, (u32)sensor->hw_id,
  268. TSENS_DBG_LOG_TEMP_READS, temp);
  269. return 0;
  270. }
  271. static int tsens_tz_activate_trip_type(struct tsens_sensor *tm_sensor,
  272. int trip, enum thermal_device_mode mode)
  273. {
  274. struct tsens_device *tmdev = NULL;
  275. unsigned int reg_cntl, code, hi_code, lo_code, mask;
  276. /* clear the interrupt and unmask */
  277. if (!tm_sensor || trip < 0)
  278. return -EINVAL;
  279. tmdev = tm_sensor->tmdev;
  280. if (!tmdev)
  281. return -EINVAL;
  282. lo_code = TSENS_THRESHOLD_MIN_CODE;
  283. hi_code = TSENS_THRESHOLD_MAX_CODE;
  284. reg_cntl = readl_relaxed((TSENS_S0_UPPER_LOWER_STATUS_CTRL_ADDR
  285. (tmdev->tsens_tm_addr) +
  286. (tm_sensor->hw_id *
  287. TSENS_SN_ADDR_OFFSET)));
  288. switch (trip) {
  289. case THERMAL_TRIP_CONFIGURABLE_HI:
  290. tmdev->sensor[tm_sensor->hw_id].thr_state.high_th_state = mode;
  291. code = (reg_cntl & TSENS_UPPER_THRESHOLD_MASK)
  292. >> TSENS_UPPER_THRESHOLD_SHIFT;
  293. mask = TSENS_UPPER_STATUS_CLR;
  294. if (!(reg_cntl & TSENS_LOWER_STATUS_CLR))
  295. lo_code = (reg_cntl & TSENS_LOWER_THRESHOLD_MASK);
  296. break;
  297. case THERMAL_TRIP_CONFIGURABLE_LOW:
  298. tmdev->sensor[tm_sensor->hw_id].thr_state.low_th_state = mode;
  299. code = (reg_cntl & TSENS_LOWER_THRESHOLD_MASK);
  300. mask = TSENS_LOWER_STATUS_CLR;
  301. if (!(reg_cntl & TSENS_UPPER_STATUS_CLR))
  302. hi_code = (reg_cntl & TSENS_UPPER_THRESHOLD_MASK)
  303. >> TSENS_UPPER_THRESHOLD_SHIFT;
  304. break;
  305. default:
  306. return -EINVAL;
  307. }
  308. if (mode == THERMAL_DEVICE_DISABLED)
  309. writel_relaxed(reg_cntl | mask,
  310. (TSENS_S0_UPPER_LOWER_STATUS_CTRL_ADDR(tmdev->tsens_tm_addr) +
  311. (tm_sensor->hw_id * TSENS_SN_ADDR_OFFSET)));
  312. else
  313. writel_relaxed(reg_cntl & ~mask,
  314. (TSENS_S0_UPPER_LOWER_STATUS_CTRL_ADDR(tmdev->tsens_tm_addr) +
  315. (tm_sensor->hw_id * TSENS_SN_ADDR_OFFSET)));
  316. /* Enable the thresholds */
  317. mb();
  318. return 0;
  319. }
  320. static int tsens1xxx_set_trip_temp(struct tsens_sensor *tm_sensor,
  321. int low_temp, int high_temp)
  322. {
  323. unsigned int reg_cntl;
  324. unsigned long flags;
  325. struct tsens_device *tmdev = NULL;
  326. int high_code, low_code, rc = 0;
  327. if (!tm_sensor)
  328. return -EINVAL;
  329. tmdev = tm_sensor->tmdev;
  330. if (!tmdev)
  331. return -EINVAL;
  332. spin_lock_irqsave(&tmdev->tsens_upp_low_lock, flags);
  333. if (high_temp != INT_MAX) {
  334. high_temp /= TSENS_SCALE_MILLIDEG;
  335. high_code = degc_to_code(high_temp, tm_sensor);
  336. tmdev->sensor[tm_sensor->hw_id].thr_state.high_adc_code =
  337. high_code;
  338. tmdev->sensor[tm_sensor->hw_id].thr_state.high_temp =
  339. high_temp;
  340. reg_cntl = readl_relaxed(TSENS_S0_UPPER_LOWER_STATUS_CTRL_ADDR
  341. (tmdev->tsens_tm_addr) +
  342. (tm_sensor->hw_id *
  343. TSENS_SN_ADDR_OFFSET));
  344. high_code <<= TSENS_UPPER_THRESHOLD_SHIFT;
  345. reg_cntl &= ~TSENS_UPPER_THRESHOLD_MASK;
  346. writel_relaxed(reg_cntl | high_code,
  347. (TSENS_S0_UPPER_LOWER_STATUS_CTRL_ADDR
  348. (tmdev->tsens_tm_addr) +
  349. (tm_sensor->hw_id *
  350. TSENS_SN_ADDR_OFFSET)));
  351. }
  352. if (low_temp != INT_MIN) {
  353. low_temp /= TSENS_SCALE_MILLIDEG;
  354. low_code = degc_to_code(low_temp, tm_sensor);
  355. tmdev->sensor[tm_sensor->hw_id].thr_state.low_adc_code =
  356. low_code;
  357. tmdev->sensor[tm_sensor->hw_id].thr_state.low_temp =
  358. low_temp;
  359. reg_cntl = readl_relaxed(TSENS_S0_UPPER_LOWER_STATUS_CTRL_ADDR
  360. (tmdev->tsens_tm_addr) +
  361. (tm_sensor->hw_id *
  362. TSENS_SN_ADDR_OFFSET));
  363. reg_cntl &= ~TSENS_LOWER_THRESHOLD_MASK;
  364. writel_relaxed(reg_cntl | low_code,
  365. (TSENS_S0_UPPER_LOWER_STATUS_CTRL_ADDR
  366. (tmdev->tsens_tm_addr) +
  367. (tm_sensor->hw_id *
  368. TSENS_SN_ADDR_OFFSET)));
  369. }
  370. /* Set trip temperature thresholds */
  371. mb();
  372. if (high_temp != INT_MAX) {
  373. rc = tsens_tz_activate_trip_type(tm_sensor,
  374. THERMAL_TRIP_CONFIGURABLE_HI,
  375. THERMAL_DEVICE_ENABLED);
  376. if (rc) {
  377. pr_err("trip high enable error :%d\n", rc);
  378. goto fail;
  379. }
  380. } else {
  381. rc = tsens_tz_activate_trip_type(tm_sensor,
  382. THERMAL_TRIP_CONFIGURABLE_HI,
  383. THERMAL_DEVICE_DISABLED);
  384. if (rc) {
  385. pr_err("trip high disable error :%d\n", rc);
  386. goto fail;
  387. }
  388. }
  389. if (low_temp != INT_MIN) {
  390. rc = tsens_tz_activate_trip_type(tm_sensor,
  391. THERMAL_TRIP_CONFIGURABLE_LOW,
  392. THERMAL_DEVICE_ENABLED);
  393. if (rc) {
  394. pr_err("trip low enable activation error :%d\n", rc);
  395. goto fail;
  396. }
  397. } else {
  398. rc = tsens_tz_activate_trip_type(tm_sensor,
  399. THERMAL_TRIP_CONFIGURABLE_LOW,
  400. THERMAL_DEVICE_DISABLED);
  401. if (rc) {
  402. pr_err("trip low disable error :%d\n", rc);
  403. goto fail;
  404. }
  405. }
  406. fail:
  407. spin_unlock_irqrestore(&tmdev->tsens_upp_low_lock, flags);
  408. return rc;
  409. }
  410. static irqreturn_t tsens_irq_thread(int irq, void *data)
  411. {
  412. struct tsens_device *tm = data;
  413. unsigned int i, status, threshold, temp, th_temp;
  414. unsigned long flags;
  415. void __iomem *sensor_status_addr;
  416. void __iomem *sensor_status_ctrl_addr;
  417. u32 rc = 0, addr_offset;
  418. sensor_status_addr = TSENS_SN_STATUS_ADDR(tm->tsens_tm_addr);
  419. sensor_status_ctrl_addr =
  420. TSENS_S0_UPPER_LOWER_STATUS_CTRL_ADDR(tm->tsens_tm_addr);
  421. for (i = 0; i < TSENS_1x_MAX_SENSORS; i++) {
  422. bool upper_thr = false, lower_thr = false;
  423. if (IS_ERR(tm->sensor[i].tzd))
  424. continue;
  425. rc = tsens1xxx_get_temp(&tm->sensor[i], &temp);
  426. if (rc) {
  427. pr_debug("Error:%d reading temp sensor:%d\n", rc, i);
  428. continue;
  429. }
  430. spin_lock_irqsave(&tm->tsens_upp_low_lock, flags);
  431. addr_offset = tm->sensor[i].hw_id *
  432. TSENS_SN_ADDR_OFFSET;
  433. status = readl_relaxed(sensor_status_addr + addr_offset);
  434. threshold = readl_relaxed(sensor_status_ctrl_addr +
  435. addr_offset);
  436. if (status & TSENS_SN_STATUS_UPPER_STATUS) {
  437. writel_relaxed(threshold | TSENS_UPPER_STATUS_CLR,
  438. TSENS_S0_UPPER_LOWER_STATUS_CTRL_ADDR(
  439. tm->tsens_tm_addr + addr_offset));
  440. th_temp = code_to_degc((threshold &
  441. TSENS_UPPER_THRESHOLD_MASK) >>
  442. TSENS_UPPER_THRESHOLD_SHIFT,
  443. (tm->sensor + i));
  444. if (th_temp > (temp/TSENS_SCALE_MILLIDEG)) {
  445. pr_debug("Re-arm high threshold\n");
  446. rc = tsens_tz_activate_trip_type(
  447. &tm->sensor[i],
  448. THERMAL_TRIP_CONFIGURABLE_HI,
  449. THERMAL_DEVICE_ENABLED);
  450. if (rc)
  451. pr_err("high rearm failed");
  452. } else {
  453. upper_thr = true;
  454. tm->sensor[i].thr_state.high_th_state =
  455. THERMAL_DEVICE_DISABLED;
  456. }
  457. }
  458. if (status & TSENS_SN_STATUS_LOWER_STATUS) {
  459. writel_relaxed(threshold | TSENS_LOWER_STATUS_CLR,
  460. TSENS_S0_UPPER_LOWER_STATUS_CTRL_ADDR(
  461. tm->tsens_tm_addr + addr_offset));
  462. th_temp = code_to_degc((threshold &
  463. TSENS_LOWER_THRESHOLD_MASK),
  464. (tm->sensor + i));
  465. if (th_temp < (temp/TSENS_SCALE_MILLIDEG)) {
  466. pr_debug("Re-arm Low threshold\n");
  467. rc = tsens_tz_activate_trip_type(
  468. &tm->sensor[i],
  469. THERMAL_TRIP_CONFIGURABLE_LOW,
  470. THERMAL_DEVICE_ENABLED);
  471. if (rc)
  472. pr_err("low rearm failed");
  473. } else {
  474. lower_thr = true;
  475. tm->sensor[i].thr_state.low_th_state =
  476. THERMAL_DEVICE_DISABLED;
  477. }
  478. }
  479. spin_unlock_irqrestore(&tm->tsens_upp_low_lock, flags);
  480. if (upper_thr || lower_thr) {
  481. pr_debug("sensor:%d trigger temp (%d degC)\n",
  482. tm->sensor[i].hw_id,
  483. code_to_degc((status &
  484. TSENS_SN_STATUS_TEMP_MASK),
  485. tm->sensor));
  486. of_thermal_handle_trip(tm->sensor[i].tzd);
  487. }
  488. }
  489. /* Disable monitoring sensor trip threshold for triggered sensor */
  490. mb();
  491. if (tm->ops->dbg)
  492. tm->ops->dbg(tm, 0, TSENS_DBG_LOG_INTERRUPT_TIMESTAMP, NULL);
  493. return IRQ_HANDLED;
  494. }
  495. static int tsens1xxx_hw_sensor_en(struct tsens_device *tmdev,
  496. u32 sensor_id)
  497. {
  498. void __iomem *srot_addr;
  499. unsigned int srot_val, sensor_en;
  500. srot_addr = TSENS_CTRL_ADDR(tmdev->tsens_srot_addr + 0x4);
  501. srot_val = readl_relaxed(srot_addr);
  502. srot_val = TSENS_CTRL_SENSOR_EN_MASK(srot_val);
  503. sensor_en = ((1 << sensor_id) & srot_val);
  504. return sensor_en;
  505. }
  506. static int tsens1xxx_hw_init(struct tsens_device *tmdev)
  507. {
  508. void __iomem *srot_addr;
  509. unsigned int srot_val;
  510. srot_addr = TSENS_CTRL_ADDR(tmdev->tsens_srot_addr + 0x4);
  511. srot_val = readl_relaxed(srot_addr);
  512. if (!(srot_val & TSENS_EN)) {
  513. pr_err("TSENS device is not enabled\n");
  514. return -ENODEV;
  515. }
  516. writel_relaxed(TSENS_INTERRUPT_EN,
  517. TSENS_UPPER_LOWER_INTERRUPT_CTRL(tmdev->tsens_tm_addr));
  518. spin_lock_init(&tmdev->tsens_upp_low_lock);
  519. if (tmdev->ctrl_data->mtc) {
  520. if (tmdev->ops->dbg)
  521. tmdev->ops->dbg(tmdev, 0, TSENS_DBG_MTC_DATA, NULL);
  522. }
  523. return 0;
  524. }
  525. static const struct tsens_irqs tsens1xxx_irqs[] = {
  526. { "tsens-upper-lower", tsens_irq_thread},
  527. };
  528. static int tsens1xxx_register_interrupts(struct tsens_device *tmdev)
  529. {
  530. struct platform_device *pdev;
  531. int i, rc;
  532. if (!tmdev)
  533. return -EINVAL;
  534. pdev = tmdev->pdev;
  535. for (i = 0; i < ARRAY_SIZE(tsens1xxx_irqs); i++) {
  536. int irq;
  537. irq = platform_get_irq_byname(pdev, tsens1xxx_irqs[i].name);
  538. if (irq < 0) {
  539. dev_err(&pdev->dev, "failed to get irq %s\n",
  540. tsens1xxx_irqs[i].name);
  541. return irq;
  542. }
  543. rc = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  544. tsens1xxx_irqs[i].handler,
  545. IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
  546. tsens1xxx_irqs[i].name, tmdev);
  547. if (rc) {
  548. dev_err(&pdev->dev, "failed to get irq %s\n",
  549. tsens1xxx_irqs[i].name);
  550. return rc;
  551. }
  552. enable_irq_wake(irq);
  553. }
  554. return 0;
  555. }
  556. static const struct tsens_ops ops_tsens1xxx = {
  557. .hw_init = tsens1xxx_hw_init,
  558. .get_temp = tsens1xxx_get_temp,
  559. .set_trips = tsens1xxx_set_trip_temp,
  560. .interrupts_reg = tsens1xxx_register_interrupts,
  561. .sensor_en = tsens1xxx_hw_sensor_en,
  562. .calibrate = calibrate_8937,
  563. .dbg = tsens2xxx_dbg,
  564. };
  565. const struct tsens_data data_tsens14xx = {
  566. .ops = &ops_tsens1xxx,
  567. .valid_status_check = true,
  568. .mtc = true,
  569. .ver_major = 1,
  570. .ver_minor = 4,
  571. };