nhi.c 18 KB

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  1. /*
  2. * Thunderbolt Cactus Ridge driver - NHI driver
  3. *
  4. * The NHI (native host interface) is the pci device that allows us to send and
  5. * receive frames from the thunderbolt bus.
  6. *
  7. * Copyright (c) 2014 Andreas Noever <[email protected]>
  8. */
  9. #include <linux/pm_runtime.h>
  10. #include <linux/slab.h>
  11. #include <linux/errno.h>
  12. #include <linux/pci.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/module.h>
  15. #include <linux/dmi.h>
  16. #include "nhi.h"
  17. #include "nhi_regs.h"
  18. #include "tb.h"
  19. #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
  20. static int ring_interrupt_index(struct tb_ring *ring)
  21. {
  22. int bit = ring->hop;
  23. if (!ring->is_tx)
  24. bit += ring->nhi->hop_count;
  25. return bit;
  26. }
  27. /**
  28. * ring_interrupt_active() - activate/deactivate interrupts for a single ring
  29. *
  30. * ring->nhi->lock must be held.
  31. */
  32. static void ring_interrupt_active(struct tb_ring *ring, bool active)
  33. {
  34. int reg = REG_RING_INTERRUPT_BASE +
  35. ring_interrupt_index(ring) / 32 * 4;
  36. int bit = ring_interrupt_index(ring) & 31;
  37. int mask = 1 << bit;
  38. u32 old, new;
  39. old = ioread32(ring->nhi->iobase + reg);
  40. if (active)
  41. new = old | mask;
  42. else
  43. new = old & ~mask;
  44. dev_info(&ring->nhi->pdev->dev,
  45. "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
  46. active ? "enabling" : "disabling", reg, bit, old, new);
  47. if (new == old)
  48. dev_WARN(&ring->nhi->pdev->dev,
  49. "interrupt for %s %d is already %s\n",
  50. RING_TYPE(ring), ring->hop,
  51. active ? "enabled" : "disabled");
  52. iowrite32(new, ring->nhi->iobase + reg);
  53. }
  54. /**
  55. * nhi_disable_interrupts() - disable interrupts for all rings
  56. *
  57. * Use only during init and shutdown.
  58. */
  59. static void nhi_disable_interrupts(struct tb_nhi *nhi)
  60. {
  61. int i = 0;
  62. /* disable interrupts */
  63. for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
  64. iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i);
  65. /* clear interrupt status bits */
  66. for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
  67. ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i);
  68. }
  69. /* ring helper methods */
  70. static void __iomem *ring_desc_base(struct tb_ring *ring)
  71. {
  72. void __iomem *io = ring->nhi->iobase;
  73. io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
  74. io += ring->hop * 16;
  75. return io;
  76. }
  77. static void __iomem *ring_options_base(struct tb_ring *ring)
  78. {
  79. void __iomem *io = ring->nhi->iobase;
  80. io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
  81. io += ring->hop * 32;
  82. return io;
  83. }
  84. static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
  85. {
  86. /*
  87. * The other 16-bits in the register is read-only and writes to it
  88. * are ignored by the hardware so we can save one ioread32() by
  89. * filling the read-only bits with zeroes.
  90. */
  91. iowrite32(cons, ring_desc_base(ring) + 8);
  92. }
  93. static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
  94. {
  95. /* See ring_iowrite_cons() above for explanation */
  96. iowrite32(prod << 16, ring_desc_base(ring) + 8);
  97. }
  98. static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
  99. {
  100. iowrite32(value, ring_desc_base(ring) + offset);
  101. }
  102. static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
  103. {
  104. iowrite32(value, ring_desc_base(ring) + offset);
  105. iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
  106. }
  107. static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
  108. {
  109. iowrite32(value, ring_options_base(ring) + offset);
  110. }
  111. static bool ring_full(struct tb_ring *ring)
  112. {
  113. return ((ring->head + 1) % ring->size) == ring->tail;
  114. }
  115. static bool ring_empty(struct tb_ring *ring)
  116. {
  117. return ring->head == ring->tail;
  118. }
  119. /**
  120. * ring_write_descriptors() - post frames from ring->queue to the controller
  121. *
  122. * ring->lock is held.
  123. */
  124. static void ring_write_descriptors(struct tb_ring *ring)
  125. {
  126. struct ring_frame *frame, *n;
  127. struct ring_desc *descriptor;
  128. list_for_each_entry_safe(frame, n, &ring->queue, list) {
  129. if (ring_full(ring))
  130. break;
  131. list_move_tail(&frame->list, &ring->in_flight);
  132. descriptor = &ring->descriptors[ring->head];
  133. descriptor->phys = frame->buffer_phy;
  134. descriptor->time = 0;
  135. descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
  136. if (ring->is_tx) {
  137. descriptor->length = frame->size;
  138. descriptor->eof = frame->eof;
  139. descriptor->sof = frame->sof;
  140. }
  141. ring->head = (ring->head + 1) % ring->size;
  142. if (ring->is_tx)
  143. ring_iowrite_prod(ring, ring->head);
  144. else
  145. ring_iowrite_cons(ring, ring->head);
  146. }
  147. }
  148. /**
  149. * ring_work() - progress completed frames
  150. *
  151. * If the ring is shutting down then all frames are marked as canceled and
  152. * their callbacks are invoked.
  153. *
  154. * Otherwise we collect all completed frame from the ring buffer, write new
  155. * frame to the ring buffer and invoke the callbacks for the completed frames.
  156. */
  157. static void ring_work(struct work_struct *work)
  158. {
  159. struct tb_ring *ring = container_of(work, typeof(*ring), work);
  160. struct ring_frame *frame;
  161. bool canceled = false;
  162. LIST_HEAD(done);
  163. mutex_lock(&ring->lock);
  164. if (!ring->running) {
  165. /* Move all frames to done and mark them as canceled. */
  166. list_splice_tail_init(&ring->in_flight, &done);
  167. list_splice_tail_init(&ring->queue, &done);
  168. canceled = true;
  169. goto invoke_callback;
  170. }
  171. while (!ring_empty(ring)) {
  172. if (!(ring->descriptors[ring->tail].flags
  173. & RING_DESC_COMPLETED))
  174. break;
  175. frame = list_first_entry(&ring->in_flight, typeof(*frame),
  176. list);
  177. list_move_tail(&frame->list, &done);
  178. if (!ring->is_tx) {
  179. frame->size = ring->descriptors[ring->tail].length;
  180. frame->eof = ring->descriptors[ring->tail].eof;
  181. frame->sof = ring->descriptors[ring->tail].sof;
  182. frame->flags = ring->descriptors[ring->tail].flags;
  183. if (frame->sof != 0)
  184. dev_WARN(&ring->nhi->pdev->dev,
  185. "%s %d got unexpected SOF: %#x\n",
  186. RING_TYPE(ring), ring->hop,
  187. frame->sof);
  188. /*
  189. * known flags:
  190. * raw not enabled, interupt not set: 0x2=0010
  191. * raw enabled: 0xa=1010
  192. * raw not enabled: 0xb=1011
  193. * partial frame (>MAX_FRAME_SIZE): 0xe=1110
  194. */
  195. if (frame->flags != 0xa)
  196. dev_WARN(&ring->nhi->pdev->dev,
  197. "%s %d got unexpected flags: %#x\n",
  198. RING_TYPE(ring), ring->hop,
  199. frame->flags);
  200. }
  201. ring->tail = (ring->tail + 1) % ring->size;
  202. }
  203. ring_write_descriptors(ring);
  204. invoke_callback:
  205. mutex_unlock(&ring->lock); /* allow callbacks to schedule new work */
  206. while (!list_empty(&done)) {
  207. frame = list_first_entry(&done, typeof(*frame), list);
  208. /*
  209. * The callback may reenqueue or delete frame.
  210. * Do not hold on to it.
  211. */
  212. list_del_init(&frame->list);
  213. frame->callback(ring, frame, canceled);
  214. }
  215. }
  216. int __ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
  217. {
  218. int ret = 0;
  219. mutex_lock(&ring->lock);
  220. if (ring->running) {
  221. list_add_tail(&frame->list, &ring->queue);
  222. ring_write_descriptors(ring);
  223. } else {
  224. ret = -ESHUTDOWN;
  225. }
  226. mutex_unlock(&ring->lock);
  227. return ret;
  228. }
  229. static struct tb_ring *ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
  230. bool transmit)
  231. {
  232. struct tb_ring *ring = NULL;
  233. dev_info(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
  234. transmit ? "TX" : "RX", hop, size);
  235. mutex_lock(&nhi->lock);
  236. if (hop >= nhi->hop_count) {
  237. dev_WARN(&nhi->pdev->dev, "invalid hop: %d\n", hop);
  238. goto err;
  239. }
  240. if (transmit && nhi->tx_rings[hop]) {
  241. dev_WARN(&nhi->pdev->dev, "TX hop %d already allocated\n", hop);
  242. goto err;
  243. } else if (!transmit && nhi->rx_rings[hop]) {
  244. dev_WARN(&nhi->pdev->dev, "RX hop %d already allocated\n", hop);
  245. goto err;
  246. }
  247. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  248. if (!ring)
  249. goto err;
  250. mutex_init(&ring->lock);
  251. INIT_LIST_HEAD(&ring->queue);
  252. INIT_LIST_HEAD(&ring->in_flight);
  253. INIT_WORK(&ring->work, ring_work);
  254. ring->nhi = nhi;
  255. ring->hop = hop;
  256. ring->is_tx = transmit;
  257. ring->size = size;
  258. ring->head = 0;
  259. ring->tail = 0;
  260. ring->running = false;
  261. ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
  262. size * sizeof(*ring->descriptors),
  263. &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
  264. if (!ring->descriptors)
  265. goto err;
  266. if (transmit)
  267. nhi->tx_rings[hop] = ring;
  268. else
  269. nhi->rx_rings[hop] = ring;
  270. mutex_unlock(&nhi->lock);
  271. return ring;
  272. err:
  273. if (ring)
  274. mutex_destroy(&ring->lock);
  275. kfree(ring);
  276. mutex_unlock(&nhi->lock);
  277. return NULL;
  278. }
  279. struct tb_ring *ring_alloc_tx(struct tb_nhi *nhi, int hop, int size)
  280. {
  281. return ring_alloc(nhi, hop, size, true);
  282. }
  283. struct tb_ring *ring_alloc_rx(struct tb_nhi *nhi, int hop, int size)
  284. {
  285. return ring_alloc(nhi, hop, size, false);
  286. }
  287. /**
  288. * ring_start() - enable a ring
  289. *
  290. * Must not be invoked in parallel with ring_stop().
  291. */
  292. void ring_start(struct tb_ring *ring)
  293. {
  294. mutex_lock(&ring->nhi->lock);
  295. mutex_lock(&ring->lock);
  296. if (ring->running) {
  297. dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
  298. goto err;
  299. }
  300. dev_info(&ring->nhi->pdev->dev, "starting %s %d\n",
  301. RING_TYPE(ring), ring->hop);
  302. ring_iowrite64desc(ring, ring->descriptors_dma, 0);
  303. if (ring->is_tx) {
  304. ring_iowrite32desc(ring, ring->size, 12);
  305. ring_iowrite32options(ring, 0, 4); /* time releated ? */
  306. ring_iowrite32options(ring,
  307. RING_FLAG_ENABLE | RING_FLAG_RAW, 0);
  308. } else {
  309. ring_iowrite32desc(ring,
  310. (TB_FRAME_SIZE << 16) | ring->size, 12);
  311. ring_iowrite32options(ring, 0xffffffff, 4); /* SOF EOF mask */
  312. ring_iowrite32options(ring,
  313. RING_FLAG_ENABLE | RING_FLAG_RAW, 0);
  314. }
  315. ring_interrupt_active(ring, true);
  316. ring->running = true;
  317. err:
  318. mutex_unlock(&ring->lock);
  319. mutex_unlock(&ring->nhi->lock);
  320. }
  321. /**
  322. * ring_stop() - shutdown a ring
  323. *
  324. * Must not be invoked from a callback.
  325. *
  326. * This method will disable the ring. Further calls to ring_tx/ring_rx will
  327. * return -ESHUTDOWN until ring_stop has been called.
  328. *
  329. * All enqueued frames will be canceled and their callbacks will be executed
  330. * with frame->canceled set to true (on the callback thread). This method
  331. * returns only after all callback invocations have finished.
  332. */
  333. void ring_stop(struct tb_ring *ring)
  334. {
  335. mutex_lock(&ring->nhi->lock);
  336. mutex_lock(&ring->lock);
  337. dev_info(&ring->nhi->pdev->dev, "stopping %s %d\n",
  338. RING_TYPE(ring), ring->hop);
  339. if (!ring->running) {
  340. dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
  341. RING_TYPE(ring), ring->hop);
  342. goto err;
  343. }
  344. ring_interrupt_active(ring, false);
  345. ring_iowrite32options(ring, 0, 0);
  346. ring_iowrite64desc(ring, 0, 0);
  347. ring_iowrite32desc(ring, 0, 8);
  348. ring_iowrite32desc(ring, 0, 12);
  349. ring->head = 0;
  350. ring->tail = 0;
  351. ring->running = false;
  352. err:
  353. mutex_unlock(&ring->lock);
  354. mutex_unlock(&ring->nhi->lock);
  355. /*
  356. * schedule ring->work to invoke callbacks on all remaining frames.
  357. */
  358. schedule_work(&ring->work);
  359. flush_work(&ring->work);
  360. }
  361. /*
  362. * ring_free() - free ring
  363. *
  364. * When this method returns all invocations of ring->callback will have
  365. * finished.
  366. *
  367. * Ring must be stopped.
  368. *
  369. * Must NOT be called from ring_frame->callback!
  370. */
  371. void ring_free(struct tb_ring *ring)
  372. {
  373. mutex_lock(&ring->nhi->lock);
  374. /*
  375. * Dissociate the ring from the NHI. This also ensures that
  376. * nhi_interrupt_work cannot reschedule ring->work.
  377. */
  378. if (ring->is_tx)
  379. ring->nhi->tx_rings[ring->hop] = NULL;
  380. else
  381. ring->nhi->rx_rings[ring->hop] = NULL;
  382. if (ring->running) {
  383. dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
  384. RING_TYPE(ring), ring->hop);
  385. }
  386. dma_free_coherent(&ring->nhi->pdev->dev,
  387. ring->size * sizeof(*ring->descriptors),
  388. ring->descriptors, ring->descriptors_dma);
  389. ring->descriptors = NULL;
  390. ring->descriptors_dma = 0;
  391. dev_info(&ring->nhi->pdev->dev,
  392. "freeing %s %d\n",
  393. RING_TYPE(ring),
  394. ring->hop);
  395. mutex_unlock(&ring->nhi->lock);
  396. /**
  397. * ring->work can no longer be scheduled (it is scheduled only by
  398. * nhi_interrupt_work and ring_stop). Wait for it to finish before
  399. * freeing the ring.
  400. */
  401. flush_work(&ring->work);
  402. mutex_destroy(&ring->lock);
  403. kfree(ring);
  404. }
  405. static void nhi_interrupt_work(struct work_struct *work)
  406. {
  407. struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
  408. int value = 0; /* Suppress uninitialized usage warning. */
  409. int bit;
  410. int hop = -1;
  411. int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
  412. struct tb_ring *ring;
  413. mutex_lock(&nhi->lock);
  414. /*
  415. * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
  416. * (TX, RX, RX overflow). We iterate over the bits and read a new
  417. * dwords as required. The registers are cleared on read.
  418. */
  419. for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
  420. if (bit % 32 == 0)
  421. value = ioread32(nhi->iobase
  422. + REG_RING_NOTIFY_BASE
  423. + 4 * (bit / 32));
  424. if (++hop == nhi->hop_count) {
  425. hop = 0;
  426. type++;
  427. }
  428. if ((value & (1 << (bit % 32))) == 0)
  429. continue;
  430. if (type == 2) {
  431. dev_warn(&nhi->pdev->dev,
  432. "RX overflow for ring %d\n",
  433. hop);
  434. continue;
  435. }
  436. if (type == 0)
  437. ring = nhi->tx_rings[hop];
  438. else
  439. ring = nhi->rx_rings[hop];
  440. if (ring == NULL) {
  441. dev_warn(&nhi->pdev->dev,
  442. "got interrupt for inactive %s ring %d\n",
  443. type ? "RX" : "TX",
  444. hop);
  445. continue;
  446. }
  447. /* we do not check ring->running, this is done in ring->work */
  448. schedule_work(&ring->work);
  449. }
  450. mutex_unlock(&nhi->lock);
  451. }
  452. static irqreturn_t nhi_msi(int irq, void *data)
  453. {
  454. struct tb_nhi *nhi = data;
  455. schedule_work(&nhi->interrupt_work);
  456. return IRQ_HANDLED;
  457. }
  458. static int nhi_suspend_noirq(struct device *dev)
  459. {
  460. struct pci_dev *pdev = to_pci_dev(dev);
  461. struct tb *tb = pci_get_drvdata(pdev);
  462. thunderbolt_suspend(tb);
  463. return 0;
  464. }
  465. static int nhi_resume_noirq(struct device *dev)
  466. {
  467. struct pci_dev *pdev = to_pci_dev(dev);
  468. struct tb *tb = pci_get_drvdata(pdev);
  469. thunderbolt_resume(tb);
  470. return 0;
  471. }
  472. static void nhi_shutdown(struct tb_nhi *nhi)
  473. {
  474. int i;
  475. dev_info(&nhi->pdev->dev, "shutdown\n");
  476. for (i = 0; i < nhi->hop_count; i++) {
  477. if (nhi->tx_rings[i])
  478. dev_WARN(&nhi->pdev->dev,
  479. "TX ring %d is still active\n", i);
  480. if (nhi->rx_rings[i])
  481. dev_WARN(&nhi->pdev->dev,
  482. "RX ring %d is still active\n", i);
  483. }
  484. nhi_disable_interrupts(nhi);
  485. /*
  486. * We have to release the irq before calling flush_work. Otherwise an
  487. * already executing IRQ handler could call schedule_work again.
  488. */
  489. devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
  490. flush_work(&nhi->interrupt_work);
  491. mutex_destroy(&nhi->lock);
  492. }
  493. static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  494. {
  495. struct tb_nhi *nhi;
  496. struct tb *tb;
  497. int res;
  498. res = pcim_enable_device(pdev);
  499. if (res) {
  500. dev_err(&pdev->dev, "cannot enable PCI device, aborting\n");
  501. return res;
  502. }
  503. res = pci_enable_msi(pdev);
  504. if (res) {
  505. dev_err(&pdev->dev, "cannot enable MSI, aborting\n");
  506. return res;
  507. }
  508. res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
  509. if (res) {
  510. dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
  511. return res;
  512. }
  513. nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
  514. if (!nhi)
  515. return -ENOMEM;
  516. nhi->pdev = pdev;
  517. /* cannot fail - table is allocated bin pcim_iomap_regions */
  518. nhi->iobase = pcim_iomap_table(pdev)[0];
  519. nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
  520. if (nhi->hop_count != 12 && nhi->hop_count != 32)
  521. dev_warn(&pdev->dev, "unexpected hop count: %d\n",
  522. nhi->hop_count);
  523. INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
  524. nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
  525. sizeof(*nhi->tx_rings), GFP_KERNEL);
  526. nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
  527. sizeof(*nhi->rx_rings), GFP_KERNEL);
  528. if (!nhi->tx_rings || !nhi->rx_rings)
  529. return -ENOMEM;
  530. nhi_disable_interrupts(nhi); /* In case someone left them on. */
  531. res = devm_request_irq(&pdev->dev, pdev->irq, nhi_msi,
  532. IRQF_NO_SUSPEND, /* must work during _noirq */
  533. "thunderbolt", nhi);
  534. if (res) {
  535. dev_err(&pdev->dev, "request_irq failed, aborting\n");
  536. return res;
  537. }
  538. mutex_init(&nhi->lock);
  539. pci_set_master(pdev);
  540. /* magic value - clock related? */
  541. iowrite32(3906250 / 10000, nhi->iobase + 0x38c00);
  542. dev_info(&nhi->pdev->dev, "NHI initialized, starting thunderbolt\n");
  543. tb = thunderbolt_alloc_and_start(nhi);
  544. if (!tb) {
  545. /*
  546. * At this point the RX/TX rings might already have been
  547. * activated. Do a proper shutdown.
  548. */
  549. nhi_shutdown(nhi);
  550. return -EIO;
  551. }
  552. pci_set_drvdata(pdev, tb);
  553. return 0;
  554. }
  555. static void nhi_remove(struct pci_dev *pdev)
  556. {
  557. struct tb *tb = pci_get_drvdata(pdev);
  558. struct tb_nhi *nhi = tb->nhi;
  559. thunderbolt_shutdown_and_free(tb);
  560. nhi_shutdown(nhi);
  561. }
  562. /*
  563. * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
  564. * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
  565. * resume_noirq until we are done.
  566. */
  567. static const struct dev_pm_ops nhi_pm_ops = {
  568. .suspend_noirq = nhi_suspend_noirq,
  569. .resume_noirq = nhi_resume_noirq,
  570. .freeze_noirq = nhi_suspend_noirq, /*
  571. * we just disable hotplug, the
  572. * pci-tunnels stay alive.
  573. */
  574. .thaw_noirq = nhi_resume_noirq,
  575. .restore_noirq = nhi_resume_noirq,
  576. };
  577. static struct pci_device_id nhi_ids[] = {
  578. /*
  579. * We have to specify class, the TB bridges use the same device and
  580. * vendor (sub)id on gen 1 and gen 2 controllers.
  581. */
  582. {
  583. .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
  584. .vendor = PCI_VENDOR_ID_INTEL,
  585. .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
  586. .subvendor = 0x2222, .subdevice = 0x1111,
  587. },
  588. {
  589. .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
  590. .vendor = PCI_VENDOR_ID_INTEL,
  591. .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
  592. .subvendor = 0x2222, .subdevice = 0x1111,
  593. },
  594. {
  595. .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
  596. .vendor = PCI_VENDOR_ID_INTEL,
  597. .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
  598. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
  599. },
  600. {
  601. .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
  602. .vendor = PCI_VENDOR_ID_INTEL,
  603. .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
  604. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
  605. },
  606. { 0,}
  607. };
  608. MODULE_DEVICE_TABLE(pci, nhi_ids);
  609. MODULE_LICENSE("GPL");
  610. static struct pci_driver nhi_driver = {
  611. .name = "thunderbolt",
  612. .id_table = nhi_ids,
  613. .probe = nhi_probe,
  614. .remove = nhi_remove,
  615. .driver.pm = &nhi_pm_ops,
  616. };
  617. static int __init nhi_init(void)
  618. {
  619. if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
  620. return -ENOSYS;
  621. return pci_register_driver(&nhi_driver);
  622. }
  623. static void __exit nhi_unload(void)
  624. {
  625. pci_unregister_driver(&nhi_driver);
  626. }
  627. module_init(nhi_init);
  628. module_exit(nhi_unload);