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- /*
- * GXBB clock tree IDs
- */
- #ifndef __GXBB_CLKC_H
- #define __GXBB_CLKC_H
- #define CLKID_CPUCLK 1
- #define CLKID_HDMI_PLL 2
- #define CLKID_FCLK_DIV2 4
- #define CLKID_FCLK_DIV3 5
- #define CLKID_FCLK_DIV4 6
- #define CLKID_CLK81 12
- #define CLKID_MPLL2 15
- #define CLKID_SPI 34
- #define CLKID_I2C 22
- #define CLKID_ETH 36
- #define CLKID_USB0 50
- #define CLKID_USB1 51
- #define CLKID_USB 55
- #define CLKID_USB1_DDR_BRIDGE 64
- #define CLKID_USB0_DDR_BRIDGE 65
- #define CLKID_AO_I2C 93
- #define CLKID_SD_EMMC_A 94
- #define CLKID_SD_EMMC_B 95
- #define CLKID_SD_EMMC_C 96
- #endif /* __GXBB_CLKC_H */
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