msm-clocks-8909.h 9.4 KB

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  1. /*
  2. * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #ifndef __MSM_CLOCKS_8909_H
  14. #define __MSM_CLOCKS_8909_H
  15. /* GPLLs */
  16. #define clk_gpll0_clk_src 0x5933b69f
  17. #define clk_gpll0_ao_clk_src 0x6b2fb034
  18. #define clk_gpll1_clk_src 0x916f8847
  19. #define clk_gpll2_clk_src 0x7c34503b
  20. /* SR2PLL */
  21. #define clk_a7sspll 0xf761da94
  22. /* SRCs */
  23. #define clk_apss_ahb_clk_src 0x36f8495f
  24. #define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e
  25. #define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa
  26. #define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79
  27. #define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a
  28. #define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902
  29. #define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f
  30. #define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68
  31. #define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb
  32. #define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804
  33. #define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f
  34. #define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803
  35. #define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4
  36. #define clk_blsp1_uart1_apps_clk_src 0xf8146114
  37. #define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73
  38. #define clk_byte0_clk_src 0x75cc885b
  39. #define clk_cci_clk_src 0x822f3d97
  40. #define clk_cpp_clk_src 0x8382f56d
  41. #define clk_camss_top_ahb_clk_src 0xf92304fb
  42. #define clk_camss_gp0_clk_src 0x43b063e9
  43. #define clk_camss_gp1_clk_src 0xa3315f1b
  44. #define clk_crypto_clk_src 0x37a21414
  45. #define clk_csi0_clk_src 0x227e65bc
  46. #define clk_csi1_clk_src 0x6a2a6c36
  47. #define clk_csi0phytimer_clk_src 0xc8a309be
  48. #define clk_csi1phytimer_clk_src 0x7c0fe23a
  49. #define clk_esc0_clk_src 0xb41d7c38
  50. #define clk_gfx3d_clk_src 0x917f76ef
  51. #define clk_gp1_clk_src 0xad85b97a
  52. #define clk_gp2_clk_src 0xfb1f0065
  53. #define clk_gp3_clk_src 0x63b693d6
  54. #define clk_jpeg0_clk_src 0x9a0a0ac3
  55. #define clk_mdp_clk_src 0x6dc1f8f1
  56. #define clk_mclk0_clk_src 0x266b3853
  57. #define clk_mclk1_clk_src 0xa73cad0c
  58. #define clk_pclk0_clk_src 0xccac1f35
  59. #define clk_pdm2_clk_src 0x31e494fd
  60. #define clk_sdcc1_apps_clk_src 0xd4975db2
  61. #define clk_sdcc2_apps_clk_src 0xfc46c821
  62. #define clk_usb_hs_system_clk_src 0x28385546
  63. #define clk_gcc_qusb2_phy_clk 0x996884d5
  64. #define clk_gcc_usb2_hs_phy_only_clk 0x0047179d
  65. #define clk_vsync_clk_src 0xecb43940
  66. #define clk_vfe0_clk_src 0xa0c2bd8f
  67. #define clk_vcodec0_clk_src 0xbc193019
  68. /* BRANCHEs*/
  69. #define clk_gcc_apss_ahb_clk 0x2b0d39ff
  70. #define clk_gcc_blsp1_ahb_clk 0x8caa5b4f
  71. #define clk_gcc_boot_rom_ahb_clk 0xde2adeb1
  72. #define clk_gcc_crypto_ahb_clk 0x94de4919
  73. #define clk_gcc_crypto_axi_clk 0xd4415c9b
  74. #define clk_gcc_crypto_clk 0x00d390d2
  75. #define clk_gcc_prng_ahb_clk 0x397e7eaa
  76. #define clk_gcc_apss_tcu_clk 0xaf56a329
  77. #define clk_gcc_gfx_tbu_clk 0x18bb9a90
  78. #define clk_gcc_gtcu_ahb_clk 0xb432168e
  79. #define clk_gcc_jpeg_tbu_clk 0xcf8fd944
  80. #define clk_gcc_mdp_tbu_clk 0x82287f76
  81. #define clk_gcc_smmu_cfg_clk 0x75eaefa5
  82. #define clk_gcc_venus_tbu_clk 0x7e0b97ce
  83. #define clk_gcc_vfe_tbu_clk 0x061f2f95
  84. #define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9
  85. #define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0
  86. #define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220
  87. #define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f
  88. #define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82
  89. #define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880
  90. #define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f
  91. #define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f
  92. #define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604
  93. #define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7
  94. #define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820
  95. #define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85
  96. #define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90
  97. #define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96
  98. #define clk_gcc_camss_cci_ahb_clk 0xa81c11ba
  99. #define clk_gcc_camss_cci_clk 0xb7dd8824
  100. #define clk_gcc_camss_csi0_ahb_clk 0x175d672a
  101. #define clk_gcc_camss_csi0_clk 0x6b01b3e1
  102. #define clk_gcc_camss_csi0phy_clk 0x06a41ff7
  103. #define clk_gcc_camss_csi0pix_clk 0x61a8a930
  104. #define clk_gcc_camss_csi0rdi_clk 0x7053c7ae
  105. #define clk_gcc_camss_csi1_ahb_clk 0x2c2dc261
  106. #define clk_gcc_camss_csi1_clk 0x1aba4a8c
  107. #define clk_gcc_camss_csi1phy_clk 0x0fd1d1fa
  108. #define clk_gcc_camss_csi1pix_clk 0x87fc98d8
  109. #define clk_gcc_camss_csi1rdi_clk 0x6ac996fe
  110. #define clk_gcc_camss_csi_vfe0_clk 0xcc73453c
  111. #define clk_gcc_camss_gp0_clk 0xd2bc3892
  112. #define clk_gcc_camss_gp1_clk 0xe4c013e1
  113. #define clk_gcc_camss_ispif_ahb_clk 0x3c0a858f
  114. #define clk_gcc_camss_jpeg0_clk 0x1ed3f032
  115. #define clk_gcc_camss_jpeg_ahb_clk 0x3bfa7603
  116. #define clk_gcc_camss_jpeg_axi_clk 0x3e278896
  117. #define clk_gcc_camss_mclk0_clk 0x80902deb
  118. #define clk_gcc_camss_mclk1_clk 0x5002d85f
  119. #define clk_gcc_camss_micro_ahb_clk 0xfbbee8cf
  120. #define clk_gcc_camss_csi0phytimer_clk 0xf8897589
  121. #define clk_gcc_camss_csi1phytimer_clk 0x4d26438f
  122. #define clk_gcc_camss_ahb_clk 0x9894b414
  123. #define clk_gcc_camss_top_ahb_clk 0x4e814a78
  124. #define clk_gcc_camss_cpp_ahb_clk 0x4ac95e14
  125. #define clk_gcc_camss_cpp_clk 0x7118a0de
  126. #define clk_gcc_camss_vfe0_clk 0xaaa3cd97
  127. #define clk_gcc_camss_vfe_ahb_clk 0x4050f47a
  128. #define clk_gcc_camss_vfe_axi_clk 0x77fe2384
  129. #define clk_gcc_oxili_gmem_clk 0x5620913a
  130. #define clk_gcc_gp1_clk 0x057f7b69
  131. #define clk_gcc_gp2_clk 0x9bf83ffd
  132. #define clk_gcc_gp3_clk 0xec6539ee
  133. #define clk_gcc_mdss_ahb_clk 0xbfb92ed3
  134. #define clk_gcc_mdss_axi_clk 0x668f51de
  135. #define clk_gcc_mdss_byte0_clk 0x35da7862
  136. #define clk_gcc_mdss_esc0_clk 0xaec5cb25
  137. #define clk_gcc_mdss_mdp_clk 0x22f3521f
  138. #define clk_gcc_mdss_pclk0_clk 0xcc5c5c77
  139. #define clk_gcc_mdss_vsync_clk 0x32a09f1f
  140. #define clk_gcc_mss_cfg_ahb_clk 0x111cde81
  141. #define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62
  142. #define clk_gcc_oxili_ahb_clk 0xd15c8a00
  143. #define clk_gcc_oxili_gfx3d_clk 0x49a51fd9
  144. #define clk_gcc_pdm2_clk 0x99d55711
  145. #define clk_gcc_pdm_ahb_clk 0x365664f6
  146. #define clk_gcc_sdcc1_ahb_clk 0x691e0caa
  147. #define clk_gcc_sdcc1_apps_clk 0x9ad6fb96
  148. #define clk_gcc_sdcc2_ahb_clk 0x23d5727f
  149. #define clk_gcc_sdcc2_apps_clk 0x861b20ac
  150. #define clk_gcc_usb2a_phy_sleep_clk 0x6caa736f
  151. #define clk_gcc_usb_hs_phy_cfg_ahb_clk 0xe13808fd
  152. #define clk_gcc_usb_hs_ahb_clk 0x72ce8032
  153. #define clk_gcc_usb_hs_system_clk 0xa11972e5
  154. #define clk_gcc_venus0_ahb_clk 0x08d778c6
  155. #define clk_gcc_venus0_axi_clk 0xcdf4c8f6
  156. #define clk_gcc_venus0_vcodec0_clk 0xf76a02bb
  157. #define clk_gcc_venus0_core0_vcodec0_clk 0x83a7f549
  158. #define clk_gcc_gfx_tcu_clk 0x59505e55
  159. #define clk_gcc_gtcu_ahb_bridge_clk 0x19d2c5fe
  160. #define clk_gcc_bimc_gpu_clk 0x19922503
  161. #define clk_gcc_bimc_gfx_clk 0x3edd69ad
  162. #define clk_gcc_snoc_qosgen_clk 0x37d40ce2
  163. #define clk_pixel_clk_src 0x8b6f83d8
  164. #define clk_byte_clk_src 0x3a911c53
  165. #define clk_dsi_pll0_byte_clk_src 0x44539836
  166. #define clk_dsi_pll0_pixel_clk_src 0x5767c287
  167. /* RPM */
  168. #define clk_pcnoc_clk 0xc1296d0f
  169. #define clk_pcnoc_a_clk 0x9bcffee4
  170. #define clk_pcnoc_msmbus_clk 0x2b53b688
  171. #define clk_pcnoc_msmbus_a_clk 0x9753a54f
  172. #define clk_pcnoc_keepalive_a_clk 0x9464f720
  173. #define clk_pcnoc_usb_a_clk 0x11d6a74e
  174. #define clk_snoc_clk 0x2c341aa0
  175. #define clk_snoc_a_clk 0x8fcef2af
  176. #define clk_snoc_msmbus_clk 0xe6900bb6
  177. #define clk_snoc_msmbus_a_clk 0x5d4683bd
  178. #define clk_snoc_mmnoc_axi_clk 0xfedd4bd5
  179. #define clk_snoc_mmnoc_ahb_clk 0xd2149dbb
  180. #define clk_snoc_usb_a_clk 0x34b7821b
  181. #define clk_snoc_mm_msmbus_clk 0x5e221ca4
  182. #define clk_snoc_mm_msmbus_a_clk 0x5950f9ea
  183. #define clk_bimc_clk 0x4b80bf00
  184. #define clk_bimc_a_clk 0x4b25668a
  185. #define clk_bimc_acpu_a_clk 0x4446311b
  186. #define clk_bimc_msmbus_clk 0xd212feea
  187. #define clk_bimc_msmbus_a_clk 0x71d1a499
  188. #define clk_bimc_usb_a_clk 0xea410834
  189. #define clk_qdss_clk 0x1492202a
  190. #define clk_qdss_a_clk 0xdd121669
  191. #define clk_xo_clk_src 0x23f5649f
  192. #define clk_xo_a_clk_src 0x2fdd2c7c
  193. #define clk_xo_otg_clk 0x79bca5cc
  194. #define clk_xo_lpm_clk 0x2be48257
  195. #define clk_xo_pil_mss_clk 0xe97a8354
  196. #define clk_xo_pil_pronto_clk 0x89dae6d0
  197. #define clk_xo_wlan_clk 0x0116b76f
  198. #define clk_qpic_clk 0x3ce6f7bb
  199. #define clk_qpic_a_clk 0xd70ccb7c
  200. #define clk_bb_clk1 0xf5304268
  201. #define clk_bb_clk1_pin 0x6dd0a779
  202. #define clk_bb_clk2 0xfe15cb87
  203. #define clk_bb_clk2_pin 0x498938e5
  204. #define clk_bb_clk3 0x3a9e99a8
  205. #define clk_bb_clk3_pin 0x3a96c14c
  206. #define clk_rf_clk1 0xaabeea5a
  207. #define clk_rf_clk1_pin 0x8f463562
  208. #define clk_rf_clk2 0x24a30992
  209. #define clk_rf_clk2_pin 0xa7c5602a
  210. /* DEBUG */
  211. #define clk_gcc_debug_mux 0x8121ac15
  212. #define clk_rpm_debug_mux 0x25cd1f3a
  213. #define clk_wcnss_m_clk 0x709f430b
  214. #define clk_apss_debug_pri_mux 0xc691ff55
  215. #define clk_apss_debug_sec_mux 0xc0b680f9
  216. #define clk_apss_debug_ter_mux 0x32041c48
  217. #define clk_apc0_m_clk 0xce1e9473
  218. #define clk_apc1_m_clk 0x990fbaf7
  219. #define clk_apc2_m_clk 0x252cd4ae
  220. #define clk_apc3_m_clk 0x78c64486
  221. #define clk_l2_m_clk 0x4bedf4d0
  222. #define clk_audio_ap_clk 0x312ac429
  223. #define clk_audio_pmi_clk 0xb7ba2274
  224. #define clk_audio_lpass_mclk 0x575ec22b
  225. /* GCC block resets */
  226. #define GCC_USB_HS_BCR 0
  227. #define GCC_USB2_HS_PHY_ONLY_BCR 1
  228. #define GCC_QUSB2_PHY_BCR 2
  229. #endif