msm-clocks-8953.h 15 KB

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  1. /*
  2. * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #ifndef __MSM_CLOCKS_8953_H
  14. #define __MSM_CLOCKS_8953_H
  15. #define clk_gpll0_clk_src 0x5933b69f
  16. #define clk_gpll0_ao_clk_src 0x6b2fb034
  17. #define clk_gpll2_clk_src 0x7c34503b
  18. #define clk_gpll3_clk_src 0x5b1eccd5
  19. #define clk_gpll4_clk_src 0x10525d57
  20. #define clk_gpll6_clk_src 0x17dceaad
  21. #define clk_gpll0_main_clk_src 0xf6e5be93
  22. #define clk_gpll0_main_div2_cci_clk_src 0x614e4b7e
  23. #define clk_gpll0_main_div2_clk_src 0x3037cffb
  24. #define clk_gpll0_main_div2_mm_clk_src 0xcf89c5ba
  25. #define clk_gpll0_main_div2_usb3_clk_src 0x23944173
  26. #define clk_gpll0_main_mock_clk_src 0xdc903e09
  27. #define clk_gpll2_out_main_clk_src 0xfcdbeff8
  28. #define clk_gpll2_vcodec_clk_src 0xa2cbc782
  29. #define clk_gpll6_aux_clk_src 0x81187caa
  30. #define clk_gpll6_main_clk_src 0xb9a328d6
  31. #define clk_gpll6_main_div2_clk_src 0x6f0016a9
  32. #define clk_gpll6_main_div2_gfx_clk_src 0xf29e5e5c
  33. #define clk_gpll6_main_gfx_clk_src 0x5aee405b
  34. #define clk_gpll6_out_aux_clk_src 0xb3fcaa27
  35. #define clk_xo_clk_src 0x23f5649f
  36. #define clk_xo_a_clk_src 0x2fdd2c7c
  37. #define clk_bimc_clk 0x4b80bf00
  38. #define clk_bimc_a_clk 0x4b25668a
  39. #define clk_pcnoc_clk 0xc1296d0f
  40. #define clk_pcnoc_a_clk 0x9bcffee4
  41. #define clk_snoc_clk 0x2c341aa0
  42. #define clk_snoc_a_clk 0x8fcef2af
  43. #define clk_sysmmnoc_clk 0xebb1df78
  44. #define clk_sysmmnoc_a_clk 0x6ca682a2
  45. #define clk_ipa_clk 0xfa685cda
  46. #define clk_ipa_a_clk 0xeeec2919
  47. #define clk_qdss_clk 0x1492202a
  48. #define clk_qdss_a_clk 0xdd121669
  49. #define clk_bimc_msmbus_clk 0xd212feea
  50. #define clk_bimc_msmbus_a_clk 0x71d1a499
  51. #define clk_bimc_usb_clk 0x9bd2b2bf
  52. #define clk_bimc_usb_a_clk 0xea410834
  53. #define clk_bimc_wcnss_a_clk 0x5a6df715
  54. #define clk_pcnoc_keepalive_a_clk 0x9464f720
  55. #define clk_pcnoc_msmbus_clk 0x2b53b688
  56. #define clk_pcnoc_msmbus_a_clk 0x9753a54f
  57. #define clk_pcnoc_usb_clk 0x57adc448
  58. #define clk_pcnoc_usb_a_clk 0x11d6a74e
  59. #define clk_snoc_msmbus_clk 0xe6900bb6
  60. #define clk_snoc_msmbus_a_clk 0x5d4683bd
  61. #define clk_snoc_usb_clk 0x29f9d73d
  62. #define clk_snoc_usb_a_clk 0x34b7821b
  63. #define clk_snoc_wcnss_a_clk 0xd3949ebc
  64. #define clk_sysmmnoc_msmbus_a_clk 0x50600f1b
  65. #define clk_sysmmnoc_msmbus_clk 0xd61e5721
  66. #define clk_xo_dwc3_clk 0xfad488ce
  67. #define clk_xo_lpm_clk 0x2be48257
  68. #define clk_xo_pil_lpass_clk 0xb72aa4c9
  69. #define clk_xo_pil_mss_clk 0xe97a8354
  70. #define clk_xo_pil_pronto_clk 0x89dae6d0
  71. #define clk_xo_wlan_clk 0x0116b76f
  72. #define clk_xo_pipe_clk_src 0x8eac73d8
  73. #define clk_gcc_apss_ahb_clk 0x2b0d39ff
  74. #define clk_gcc_apss_axi_clk 0x1d47f4ff
  75. #define clk_gcc_blsp1_ahb_clk 0x8caa5b4f
  76. #define clk_gcc_blsp2_ahb_clk 0x8f283c1d
  77. #define clk_gcc_boot_rom_ahb_clk 0xde2adeb1
  78. #define clk_gcc_crypto_ahb_clk 0x94de4919
  79. #define clk_gcc_crypto_axi_clk 0xd4415c9b
  80. #define clk_gcc_crypto_clk 0x00d390d2
  81. #define clk_gcc_prng_ahb_clk 0x397e7eaa
  82. #define clk_gcc_qdss_dap_clk 0x7fa9aa73
  83. #define clk_gcc_apss_tcu_async_clk 0x8fbc51da
  84. #define clk_gcc_cpp_tbu_clk 0xab6f19ab
  85. #define clk_gcc_jpeg_tbu_clk 0xcf8fd944
  86. #define clk_gcc_mdp_tbu_clk 0x82287f76
  87. #define clk_gcc_smmu_cfg_clk 0x75eaefa5
  88. #define clk_gcc_venus_tbu_clk 0x7e0b97ce
  89. #define clk_gcc_vfe1_tbu_clk 0x4888e70f
  90. #define clk_gcc_vfe_tbu_clk 0x061f2f95
  91. #define clk_camss_top_ahb_clk_src 0xf92304fb
  92. #define clk_csi0_clk_src 0x227e65bc
  93. #define clk_apss_ahb_clk_src 0x36f8495f
  94. #define clk_csi1_clk_src 0x6a2a6c36
  95. #define clk_csi2_clk_src 0x4113589f
  96. #define clk_vfe0_clk_src 0xa0c2bd8f
  97. #define clk_gfx3d_clk_src 0x917f76ef
  98. #define clk_vcodec0_clk_src 0xbc193019
  99. #define clk_cpp_clk_src 0x8382f56d
  100. #define clk_jpeg0_clk_src 0x9a0a0ac3
  101. #define clk_mdp_clk_src 0x6dc1f8f1
  102. #define clk_pclk0_clk_src 0xccac1f35
  103. #define clk_ext_pclk0_clk_src 0x087c1612
  104. #define clk_pclk1_clk_src 0x090f68ac
  105. #define clk_ext_pclk1_clk_src 0x8067c5a3
  106. #define clk_mdss_mdp_vote_clk 0x588460a4
  107. #define clk_mdss_rotator_vote_clk 0x5b1f675e
  108. #define clk_usb30_master_clk_src 0xc6262f89
  109. #define clk_vfe1_clk_src 0x4e357366
  110. #define clk_apc0_droop_detector_clk_src 0x824a5cb7
  111. #define clk_apc1_droop_detector_clk_src 0x8708fba4
  112. #define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e
  113. #define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa
  114. #define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79
  115. #define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a
  116. #define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902
  117. #define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f
  118. #define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68
  119. #define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb
  120. #define clk_blsp1_uart1_apps_clk_src 0xf8146114
  121. #define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73
  122. #define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d
  123. #define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365
  124. #define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51
  125. #define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44
  126. #define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c
  127. #define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92
  128. #define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c
  129. #define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1
  130. #define clk_blsp2_uart1_apps_clk_src 0x562c66dc
  131. #define clk_blsp2_uart2_apps_clk_src 0xdd448080
  132. #define clk_cci_clk_src 0x822f3d97
  133. #define clk_csi0p_clk_src 0xf1b8f4e7
  134. #define clk_csi1p_clk_src 0x08d1986c
  135. #define clk_csi2p_clk_src 0x7ebc4951
  136. #define clk_camss_gp0_clk_src 0x43b063e9
  137. #define clk_camss_gp1_clk_src 0xa3315f1b
  138. #define clk_mclk0_clk_src 0x266b3853
  139. #define clk_mclk1_clk_src 0xa73cad0c
  140. #define clk_mclk2_clk_src 0x42545468
  141. #define clk_mclk3_clk_src 0x2bfbb714
  142. #define clk_csi0phytimer_clk_src 0xc8a309be
  143. #define clk_csi1phytimer_clk_src 0x7c0fe23a
  144. #define clk_csi2phytimer_clk_src 0x62ffea9c
  145. #define clk_crypto_clk_src 0x37a21414
  146. #define clk_gp1_clk_src 0xad85b97a
  147. #define clk_gp2_clk_src 0xfb1f0065
  148. #define clk_gp3_clk_src 0x63b693d6
  149. #define clk_byte0_clk_src 0x75cc885b
  150. #define clk_ext_byte0_clk_src 0xfb32f31e
  151. #define clk_byte1_clk_src 0x63c2c955
  152. #define clk_ext_byte1_clk_src 0x585ef6d4
  153. #define clk_esc0_clk_src 0xb41d7c38
  154. #define clk_esc1_clk_src 0x3b0afa42
  155. #define clk_vsync_clk_src 0xecb43940
  156. #define clk_pdm2_clk_src 0x31e494fd
  157. #define clk_rbcpr_gfx_clk_src 0x37f04b53
  158. #define clk_sdcc1_apps_clk_src 0xd4975db2
  159. #define clk_sdcc1_ice_core_clk_src 0xfd6a4301
  160. #define clk_sdcc2_apps_clk_src 0xfc46c821
  161. #define clk_usb30_mock_utmi_clk_src 0xa024a976
  162. #define clk_usb3_aux_clk_src 0xfde7ae09
  163. #define clk_usb3_pipe_clk_src 0x8b922db4
  164. #define clk_gcc_apc0_droop_detector_gpll0_clk 0x514e25ca
  165. #define clk_gcc_apc1_droop_detector_gpll0_clk 0x0c9c03ee
  166. #define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9
  167. #define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0
  168. #define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220
  169. #define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f
  170. #define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82
  171. #define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880
  172. #define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f
  173. #define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f
  174. #define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90
  175. #define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96
  176. #define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd
  177. #define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc
  178. #define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e
  179. #define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d
  180. #define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170
  181. #define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6
  182. #define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d
  183. #define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93
  184. #define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff
  185. #define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3
  186. #define clk_gcc_camss_cci_ahb_clk 0xa81c11ba
  187. #define clk_gcc_camss_cci_clk 0xb7dd8824
  188. #define clk_gcc_camss_cpp_ahb_clk 0x4ac95e14
  189. #define clk_gcc_camss_cpp_axi_clk 0xbbf73861
  190. #define clk_gcc_camss_cpp_clk 0x7118a0de
  191. #define clk_gcc_camss_csi0_ahb_clk 0x175d672a
  192. #define clk_gcc_camss_csi0_clk 0x6b01b3e1
  193. #define clk_gcc_camss_csi0_csiphy_3p_clk 0x6a23bd3d
  194. #define clk_gcc_camss_csi0phy_clk 0x06a41ff7
  195. #define clk_gcc_camss_csi0pix_clk 0x61a8a930
  196. #define clk_gcc_camss_csi0rdi_clk 0x7053c7ae
  197. #define clk_gcc_camss_csi1_ahb_clk 0x2c2dc261
  198. #define clk_gcc_camss_csi1_clk 0x1aba4a8c
  199. #define clk_gcc_camss_csi1_csiphy_3p_clk 0x7d45d937
  200. #define clk_gcc_camss_csi1phy_clk 0x0fd1d1fa
  201. #define clk_gcc_camss_csi1pix_clk 0x87fc98d8
  202. #define clk_gcc_camss_csi1rdi_clk 0x6ac996fe
  203. #define clk_gcc_camss_csi2_ahb_clk 0xf3f25940
  204. #define clk_gcc_camss_csi2_clk 0xb6857fa2
  205. #define clk_gcc_camss_csi2_csiphy_3p_clk 0x27d7be82
  206. #define clk_gcc_camss_csi2phy_clk 0xbeeffbcd
  207. #define clk_gcc_camss_csi2pix_clk 0xa619561a
  208. #define clk_gcc_camss_csi2rdi_clk 0x019fd3f1
  209. #define clk_gcc_camss_csi_vfe0_clk 0xcc73453c
  210. #define clk_gcc_camss_csi_vfe1_clk 0xb1ef6e8b
  211. #define clk_gcc_camss_gp0_clk 0xd2bc3892
  212. #define clk_gcc_camss_gp1_clk 0xe4c013e1
  213. #define clk_gcc_camss_ispif_ahb_clk 0x3c0a858f
  214. #define clk_gcc_camss_jpeg0_clk 0x1ed3f032
  215. #define clk_gcc_camss_jpeg_ahb_clk 0x3bfa7603
  216. #define clk_gcc_camss_jpeg_axi_clk 0x3e278896
  217. #define clk_gcc_camss_mclk0_clk 0x80902deb
  218. #define clk_gcc_camss_mclk1_clk 0x5002d85f
  219. #define clk_gcc_camss_mclk2_clk 0x222f8fff
  220. #define clk_gcc_camss_mclk3_clk 0x73802c85
  221. #define clk_gcc_camss_micro_ahb_clk 0xfbbee8cf
  222. #define clk_gcc_camss_csi0phytimer_clk 0xf8897589
  223. #define clk_gcc_camss_csi1phytimer_clk 0x4d26438f
  224. #define clk_gcc_camss_csi2phytimer_clk 0xe768898c
  225. #define clk_gcc_camss_ahb_clk 0x9894b414
  226. #define clk_gcc_camss_top_ahb_clk 0x4e814a78
  227. #define clk_gcc_camss_vfe0_clk 0xaaa3cd97
  228. #define clk_gcc_camss_vfe_ahb_clk 0x4050f47a
  229. #define clk_gcc_camss_vfe_axi_clk 0x77fe2384
  230. #define clk_gcc_camss_vfe1_ahb_clk 0x634a738a
  231. #define clk_gcc_camss_vfe1_axi_clk 0xaf7463b3
  232. #define clk_gcc_camss_vfe1_clk 0xcaf20d99
  233. #define clk_gcc_dcc_clk 0xd1000c50
  234. #define clk_gcc_gp1_clk 0x057f7b69
  235. #define clk_gcc_gp2_clk 0x9bf83ffd
  236. #define clk_gcc_gp3_clk 0xec6539ee
  237. #define clk_gcc_mdss_ahb_clk 0xbfb92ed3
  238. #define clk_gcc_mdss_axi_clk 0x668f51de
  239. #define clk_gcc_mdss_byte0_clk 0x35da7862
  240. #define clk_gcc_mdss_byte1_clk 0x41f97fd8
  241. #define clk_gcc_mdss_esc0_clk 0xaec5cb25
  242. #define clk_gcc_mdss_esc1_clk 0x34653cc7
  243. #define clk_gcc_mdss_mdp_clk 0x22f3521f
  244. #define clk_gcc_mdss_pclk0_clk 0xcc5c5c77
  245. #define clk_gcc_mdss_pclk1_clk 0x9a9c430d
  246. #define clk_gcc_mdss_vsync_clk 0x32a09f1f
  247. #define clk_gcc_mss_cfg_ahb_clk 0x111cde81
  248. #define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62
  249. #define clk_gcc_bimc_gfx_clk 0x3edd69ad
  250. #define clk_gcc_bimc_gpu_clk 0x19922503
  251. #define clk_gcc_oxili_ahb_clk 0xd15c8a00
  252. #define clk_gcc_oxili_aon_clk 0xae18e54d
  253. #define clk_gcc_oxili_gfx3d_clk 0x49a51fd9
  254. #define clk_gcc_oxili_timer_clk 0x1180db06
  255. #define clk_gcc_pcnoc_usb3_axi_clk 0xf7f4b314
  256. #define clk_gcc_pdm2_clk 0x99d55711
  257. #define clk_gcc_pdm_ahb_clk 0x365664f6
  258. #define clk_gcc_rbcpr_gfx_clk 0x20c0af83
  259. #define clk_gcc_sdcc1_ahb_clk 0x691e0caa
  260. #define clk_gcc_sdcc1_apps_clk 0x9ad6fb96
  261. #define clk_gcc_sdcc1_ice_core_clk 0x0fd5680a
  262. #define clk_gcc_sdcc2_ahb_clk 0x23d5727f
  263. #define clk_gcc_sdcc2_apps_clk 0x861b20ac
  264. #define clk_gcc_usb30_master_clk 0xb3b4e2cb
  265. #define clk_gcc_usb30_mock_utmi_clk 0xa800b65a
  266. #define clk_gcc_usb30_sleep_clk 0xd0b65c92
  267. #define clk_gcc_usb3_aux_clk 0x555d16b2
  268. #define clk_gcc_usb_phy_cfg_ahb_clk 0xccb7e26f
  269. #define clk_gcc_venus0_ahb_clk 0x08d778c6
  270. #define clk_gcc_venus0_axi_clk 0xcdf4c8f6
  271. #define clk_gcc_venus0_core0_vcodec0_clk 0x83a7f549
  272. #define clk_gcc_venus0_vcodec0_clk 0xf76a02bb
  273. #define clk_gcc_qusb_ref_clk 0x16e35a90
  274. #define clk_gcc_usb_ss_ref_clk 0xb85dadfa
  275. #define clk_gcc_usb3_pipe_clk 0x26f8a97a
  276. #define clk_gcc_qusb2_phy_reset 0x3ce5fa84
  277. #define clk_gcc_usb3_phy_reset 0x03d559f1
  278. #define clk_gcc_usb3phy_phy_reset 0xb1a4f885
  279. #define clk_bb_clk1 0xf5304268
  280. #define clk_bb_clk1_a 0xfa113810
  281. #define clk_bb_clk1_pin 0x6dd0a779
  282. #define clk_bb_clk1_a_pin 0x9b637772
  283. #define clk_bb_clk2 0xfe15cb87
  284. #define clk_bb_clk2_a 0x59682706
  285. #define clk_bb_clk2_pin 0x498938e5
  286. #define clk_bb_clk2_a_pin 0x52513787
  287. #define clk_rf_clk2 0x24a30992
  288. #define clk_rf_clk2_a 0x944d8bbd
  289. #define clk_rf_clk3 0xb673936b
  290. #define clk_rf_clk3_a 0xf7975f21
  291. #define clk_div_clk2 0xd454019f
  292. #define clk_div_clk2_a 0x4bd7bfa8
  293. /* clock_debug controlled clocks */
  294. #define clk_gcc_debug_mux 0x8121ac15
  295. #define clk_wcnss_m_clk 0x709f430b
  296. #define clk_apcs_hf_pll 0x8fef0444
  297. #define clk_apcs_hf_pll_main 0xef871ccf
  298. #define clk_ccissmux 0x839fb2ef
  299. #define clk_a53_perf_clk 0xa0a0dc7f
  300. #define clk_a53_pwr_clk 0x2e6af930
  301. #define clk_a53ssmux_pwr 0x48a50c99
  302. #define clk_a53ssmux_perf 0x154acbc9
  303. #define clk_cci_clk 0x96854074
  304. #define clk_apc0_m_clk 0xce1e9473
  305. #define clk_apc1_m_clk 0x990fbaf7
  306. #define clk_cci_m_clk 0xec7e8afc
  307. #define clk_apss_debug_pri_mux 0xc691ff55
  308. #define clk_cpu_debug_pri_mux 0x61a2945f
  309. #define clk_debug_cpu_clk 0x0e696b2b
  310. #define clk_apcs_c0_pll 0xfbc57bbd
  311. #define clk_apcs_c1_pll 0x17d32f1e
  312. #define clk_apcs_cci_pll 0x09affb3c
  313. #define clk_a53ssmux_cci 0x15560bd5
  314. #define clk_perf_cpussmux 0xe6532496
  315. #define clk_pwr_cpussmux 0xde339cf1
  316. #define clk_cci_cpussmux 0xcaeb1b94
  317. #define clk_pwr_clk 0x9283a6d8
  318. #define clk_perf_clk 0x98d6ee40
  319. #define clk_a53_cci_clk 0x4cdbbe58
  320. #define clk_audio_ap_clk 0x312ac429
  321. #define clk_audio_pmi_clk 0xb7ba2274
  322. #define clk_audio_ap_clk2 0xf0fbaf5b
  323. /* external multimedia clocks */
  324. #define clk_dsi0pll_pixel_clk_mux 0x792379e1
  325. #define clk_dsi0pll_byte_clk_mux 0x60e83f06
  326. #define clk_dsi0pll_byte_clk_src 0xbbaa30be
  327. #define clk_dsi0pll_pixel_clk_src 0x45b3260f
  328. #define clk_dsi0pll_n2_div_clk 0x1474c213
  329. #define clk_dsi0pll_post_n1_div_clk 0xdab8c389
  330. #define clk_dsi0pll_vco_clk 0x15940d40
  331. #define clk_dsi1pll_pixel_clk_mux 0x36458019
  332. #define clk_dsi1pll_byte_clk_mux 0xb5a42b7b
  333. #define clk_dsi1pll_byte_clk_src 0x63930a8f
  334. #define clk_dsi1pll_pixel_clk_src 0x0e4c9b56
  335. #define clk_dsi1pll_n2_div_clk 0x2c9d4007
  336. #define clk_dsi1pll_post_n1_div_clk 0x03020041
  337. #define clk_dsi1pll_vco_clk 0x99797b50
  338. #define clk_mdss_dsi1_vco_clk_src 0xfcd15658
  339. #define clk_dsi0pll_shadow_byte_clk_src 0x177c029c
  340. #define clk_dsi0pll_shadow_pixel_clk_src 0x98ae3c92
  341. #define clk_dsi1pll_shadow_byte_clk_src 0xfc021ce5
  342. #define clk_dsi1pll_shadow_pixel_clk_src 0xdcca3ffc
  343. /* GCC block resets */
  344. #define GCC_QUSB2_PHY_BCR 0
  345. #define GCC_USB3_PHY_BCR 1
  346. #define GCC_USB3PHY_PHY_BCR 2
  347. #define GCC_USB_30_BCR 3
  348. #define GCC_CAMSS_MICRO_BCR 4
  349. #endif