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android10
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kernel
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include
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dt-bindings
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clock
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qcom,dispcc-sdm845.h

qcom,dispcc-sdm845.h 2.3 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify
    5. 

  5.  * it under the terms of the GNU General Public License version 2 and
    6. 

  6.  * only version 2 as published by the Free Software Foundation.
    7. 

  7.  *
    8. 

  8.  * This program is distributed in the hope that it will be useful,
    9. 

  9.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    10. 

  10.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    11. 

  11.  * GNU General Public License for more details.
    12. 

  12.  */
    13. 

  13. 

  14. #ifndef _DT_BINDINGS_CLK_MSM_DISP_CC_SDM845_H
    15. 

  15. #define _DT_BINDINGS_CLK_MSM_DISP_CC_SDM845_H
    16. 

  16. 

  17. #define DISP_CC_MDSS_AHB_CLK					0
    18. 

  18. #define DISP_CC_MDSS_AXI_CLK					1
    19. 

  19. #define DISP_CC_MDSS_BYTE0_CLK					2
    20. 

  20. #define DISP_CC_MDSS_BYTE0_CLK_SRC				3
    21. 

  21. #define DISP_CC_MDSS_BYTE0_INTF_CLK				4
    22. 

  22. #define DISP_CC_MDSS_BYTE1_CLK					5
    23. 

  23. #define DISP_CC_MDSS_BYTE1_CLK_SRC				6
    24. 

  24. #define DISP_CC_MDSS_BYTE1_INTF_CLK				7
    25. 

  25. #define DISP_CC_MDSS_DP_AUX_CLK					8
    26. 

  26. #define DISP_CC_MDSS_DP_AUX_CLK_SRC				9
    27. 

  27. #define DISP_CC_MDSS_DP_CRYPTO_CLK				10
    28. 

  28. #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				11
    29. 

  29. #define DISP_CC_MDSS_DP_LINK_CLK				12
    30. 

  30. #define DISP_CC_MDSS_DP_LINK_CLK_SRC				13
    31. 

  31. #define DISP_CC_MDSS_DP_LINK_INTF_CLK				14
    32. 

  32. #define DISP_CC_MDSS_DP_PIXEL1_CLK				15
    33. 

  33. #define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				16
    34. 

  34. #define DISP_CC_MDSS_DP_PIXEL_CLK				17
    35. 

  35. #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				18
    36. 

  36. #define DISP_CC_MDSS_ESC0_CLK					19
    37. 

  37. #define DISP_CC_MDSS_ESC0_CLK_SRC				20
    38. 

  38. #define DISP_CC_MDSS_ESC1_CLK					21
    39. 

  39. #define DISP_CC_MDSS_ESC1_CLK_SRC				22
    40. 

  40. #define DISP_CC_MDSS_MDP_CLK					23
    41. 

  41. #define DISP_CC_MDSS_MDP_CLK_SRC				24
    42. 

  42. #define DISP_CC_MDSS_MDP_LUT_CLK				25
    43. 

  43. #define DISP_CC_MDSS_PCLK0_CLK					26
    44. 

  44. #define DISP_CC_MDSS_PCLK0_CLK_SRC				27
    45. 

  45. #define DISP_CC_MDSS_PCLK1_CLK					28
    46. 

  46. #define DISP_CC_MDSS_PCLK1_CLK_SRC				29
    47. 

  47. #define DISP_CC_MDSS_QDSS_AT_CLK				30
    48. 

  48. #define DISP_CC_MDSS_QDSS_TSCTR_DIV8_CLK			31
    49. 

  49. #define DISP_CC_MDSS_ROT_CLK					32
    50. 

  50. #define DISP_CC_MDSS_ROT_CLK_SRC				33
    51. 

  51. #define DISP_CC_MDSS_RSCC_AHB_CLK				34
    52. 

  52. #define DISP_CC_MDSS_RSCC_VSYNC_CLK				35
    53. 

  53. #define DISP_CC_MDSS_VSYNC_CLK					36
    54. 

  54. #define DISP_CC_MDSS_VSYNC_CLK_SRC				37
    55. 

  55. #define DISP_CC_PLL0						38
    56. 

  56. #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				39
    57. 

  57. #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				40
    58. 

  58. 

  59. #define DISP_CC_MDSS_RSCC_BCR					0
    60. 

  60. 

  61. #endif
    62.