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- * Samsung Exynos5410 Clock Controller
- The Exynos5410 clock controller generates and supplies clock to various
- controllers within the Exynos5410 SoC.
- Required Properties:
- - compatible: should be "samsung,exynos5410-clock"
- - reg: physical base address of the controller and length of memory mapped
- region.
- - #clock-cells: should be 1.
- - clocks: should contain an entry specifying the root clock from external
- oscillator supplied through XXTI or XusbXTI pin. This clock should be
- defined using standard clock bindings with "fin_pll" clock-output-name.
- That clock is being passed internally to the 9 PLLs.
- All available clocks are defined as preprocessor macros in
- dt-bindings/clock/exynos5410.h header and can be used in device
- tree sources.
- Example 1: An example of a clock controller node is listed below.
- fin_pll: xxti {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "fin_pll";
- #clock-cells = <0>;
- };
- clock: clock-controller@0x10010000 {
- compatible = "samsung,exynos5410-clock";
- reg = <0x10010000 0x30000>;
- #clock-cells = <1>;
- clocks = <&fin_pll>;
- };
- Example 2: UART controller node that consumes the clock generated by the clock
- controller. Refer to the standard clock bindings for information
- about 'clocks' and 'clock-names' property.
- serial@12C20000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C00000 0x100>;
- interrupts = <0 51 0>;
- clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
- clock-names = "uart", "clk_uart_baud0";
- };
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